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authorJonas Gorski <jonas.gorski@gmail.com>2012-10-28 08:17:55 -0400
committerJohn Crispin <blogic@openwrt.org>2012-11-09 05:37:18 -0500
commitba00e2e5c24f447fb09437a99df697787103f0cd (patch)
tree89188f75eb09cca6daea06d327fa3689b1151fda /arch/mips/pci/pci-bcm63xx.c
parent799faa626c71fbd92396abea28f7e3586de3c7f5 (diff)
MIPS: BCM63XX: use the new reset helper
Use the new reset helper where appropriate. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4453 Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/pci/pci-bcm63xx.c')
-rw-r--r--arch/mips/pci/pci-bcm63xx.c19
1 files changed, 6 insertions, 13 deletions
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index fa8c320936fe..ca179b6ff39b 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -14,6 +14,8 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <asm/bootinfo.h> 15#include <asm/bootinfo.h>
16 16
17#include <bcm63xx_reset.h>
18
17#include "pci-bcm63xx.h" 19#include "pci-bcm63xx.h"
18 20
19/* 21/*
@@ -126,23 +128,14 @@ static void __init bcm63xx_reset_pcie(void)
126 bcm_misc_writel(val, MISC_SERDES_CTRL_REG); 128 bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
127 129
128 /* reset the PCIe core */ 130 /* reset the PCIe core */
129 val = bcm_perf_readl(PERF_SOFTRESET_6328_REG); 131 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
130 132 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
131 val &= ~SOFTRESET_6328_PCIE_MASK;
132 val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
133 val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
134 val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
135 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
136 mdelay(10); 133 mdelay(10);
137 134
138 val |= SOFTRESET_6328_PCIE_MASK; 135 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
139 val |= SOFTRESET_6328_PCIE_CORE_MASK;
140 val |= SOFTRESET_6328_PCIE_HARD_MASK;
141 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
142 mdelay(10); 136 mdelay(10);
143 137
144 val |= SOFTRESET_6328_PCIE_EXT_MASK; 138 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
145 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
146 mdelay(200); 139 mdelay(200);
147} 140}
148 141