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authorRalf Baechle <ralf@linux-mips.org>2005-02-21 11:18:36 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:42 -0400
commitc4ed38a0c6e2e5c4906296758f816ee71373792f (patch)
tree65ebab9ca61ea6d03109c53acd2989b626dce52a /arch/mips/pci/fixup-cobalt.c
parent049b13c358f0187cf3c5003d5fb9848dbcb28bc3 (diff)
Resurrect Cobalt support for 2.6.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci/fixup-cobalt.c')
-rw-r--r--arch/mips/pci/fixup-cobalt.c55
1 files changed, 52 insertions, 3 deletions
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 57e1ca2116bb..909292f50d06 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -21,6 +21,20 @@
21 21
22extern int cobalt_board_id; 22extern int cobalt_board_id;
23 23
24static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
25{
26 if (dev->devfn == PCI_DEVFN(0, 0) &&
27 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
28
29 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
30
31 printk(KERN_INFO "Galileo: fixed bridge class\n");
32 }
33}
34
35DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
36 qube_raq_galileo_early_fixup);
37
24static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) 38static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
25{ 39{
26 unsigned short cfgword; 40 unsigned short cfgword;
@@ -48,6 +62,9 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
48{ 62{
49 unsigned short galileo_id; 63 unsigned short galileo_id;
50 64
65 if (dev->devfn != PCI_DEVFN(0, 0))
66 return;
67
51 /* Fix PCI latency-timer and cache-line-size values in Galileo 68 /* Fix PCI latency-timer and cache-line-size values in Galileo
52 * host bridge. 69 * host bridge.
53 */ 70 */
@@ -55,6 +72,13 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
55 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); 72 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
56 73
57 /* 74 /*
75 * The code described by the comment below has been removed
76 * as it causes bus mastering by the Ethernet controllers
77 * to break under any kind of network load. We always set
78 * the retry timeouts to their maximum.
79 *
80 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
81 *
58 * On all machines prior to Q2, we had the STOP line disconnected 82 * On all machines prior to Q2, we had the STOP line disconnected
59 * from Galileo to VIA on PCI. The new Galileo does not function 83 * from Galileo to VIA on PCI. The new Galileo does not function
60 * correctly unless we have it connected. 84 * correctly unless we have it connected.
@@ -64,21 +88,43 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
64 */ 88 */
65 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); 89 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
66 galileo_id &= 0xff; /* mask off class info */ 90 galileo_id &= 0xff; /* mask off class info */
91
92 printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
93
94#if 0
67 if (galileo_id >= 0x10) { 95 if (galileo_id >= 0x10) {
68 /* New Galileo, assumes PCI stop line to VIA is connected. */ 96 /* New Galileo, assumes PCI stop line to VIA is connected. */
69 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); 97 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
70 } else if (galileo_id == 0x1 || galileo_id == 0x2) { 98 } else if (galileo_id == 0x1 || galileo_id == 0x2)
99#endif
100 {
71 signed int timeo; 101 signed int timeo;
72 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
73 timeo = GALILEO_INL(GT_PCI0_TOR_OFS); 103 timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
74 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
75 GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS); 105 GALILEO_OUTL(
106 (0xff << 16) | /* retry count */
107 (0xff << 8) | /* timeout 1 */
108 0xff, /* timeout 0 */
109 GT_PCI0_TOR_OFS);
110
111 /* enable PCI retry exceeded interrupt */
112 GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
76 } 113 }
77} 114}
78 115
79DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, 116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
80 qube_raq_galileo_fixup); 117 qube_raq_galileo_fixup);
81 118
119static char irq_tab_qube1[] __initdata = {
120 [COBALT_PCICONF_CPU] = 0,
121 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
122 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
123 [COBALT_PCICONF_VIA] = 0,
124 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
125 [COBALT_PCICONF_ETH1] = 0
126};
127
82static char irq_tab_cobalt[] __initdata = { 128static char irq_tab_cobalt[] __initdata = {
83 [COBALT_PCICONF_CPU] = 0, 129 [COBALT_PCICONF_CPU] = 0,
84 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 130 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
@@ -99,6 +145,9 @@ static char irq_tab_raq2[] __initdata = {
99 145
100int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 146int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
101{ 147{
148 if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
149 return irq_tab_qube1[slot];
150
102 if (cobalt_board_id == COBALT_BRD_ID_RAQ2) 151 if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
103 return irq_tab_raq2[slot]; 152 return irq_tab_raq2[slot];
104 153