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authorBen Hutchings <ben@decadent.org.uk>2010-06-13 17:22:59 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-07-26 14:08:19 -0400
commit8faf2e6c201d95b780cd3b4674b7a55ede6dcbbb (patch)
treeccae9e193f41652a4cd1fb9db371298d6ea586e5 /arch/mips/nxp
parent0d5977d652fa5fd4e9a56127b109e5e28d4db95d (diff)
MIPS: Set io_map_base for several PCI bridges lacking it
Several MIPS platforms don't set pci_controller::io_map_base for their PCI bridges. This results in a panic in pci_iomap(). (The panic is conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI MIPS systems.) Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: linux-mips@linux-mips.org Cc: Martin Michlmayr <tbm@cyrius.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: 584784@bugs.debian.org Patchwork: https://patchwork.linux-mips.org/patch/1377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/nxp')
-rw-r--r--arch/mips/nxp/pnx8550/common/pci.c1
-rw-r--r--arch/mips/nxp/pnx8550/common/setup.c2
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/nxp/pnx8550/common/pci.c b/arch/mips/nxp/pnx8550/common/pci.c
index eee4f3dfc410..98e86ddb86cc 100644
--- a/arch/mips/nxp/pnx8550/common/pci.c
+++ b/arch/mips/nxp/pnx8550/common/pci.c
@@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops;
44 44
45static struct pci_controller pnx8550_controller = { 45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops, 46 .pci_ops = &pnx8550_pci_ops,
47 .io_map_base = PNX8550_PORT_BASE,
47 .io_resource = &pci_io_resource, 48 .io_resource = &pci_io_resource,
48 .mem_resource = &pci_mem_resource, 49 .mem_resource = &pci_mem_resource,
49}; 50};
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
index 2aed50fef10f..64246c9c875c 100644
--- a/arch/mips/nxp/pnx8550/common/setup.c
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -113,7 +113,7 @@ void __init plat_mem_setup(void)
113 PNX8550_GLB2_ENAB_INTA_O = 0; 113 PNX8550_GLB2_ENAB_INTA_O = 0;
114 114
115 /* IO/MEM resources. */ 115 /* IO/MEM resources. */
116 set_io_port_base(KSEG1); 116 set_io_port_base(PNX8550_PORT_BASE);
117 ioport_resource.start = 0; 117 ioport_resource.start = 0;
118 ioport_resource.end = ~0; 118 ioport_resource.end = ~0;
119 iomem_resource.start = 0; 119 iomem_resource.start = 0;