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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-30 20:20:32 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-30 20:20:32 -0500
commitcdfc83075fb76369a31e6c187d0cebcab9f8b9c8 (patch)
tree33d1cdca3e2cb610451ed30943189f55652bac4c /arch/mips/netlogic
parent04a24ae45d018e177db7e4ae2d03a70f79149782 (diff)
parentb26a21c1eacdb7daf22a304fa857413df2650cfe (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include <linux/init.h> MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ...
Diffstat (limited to 'arch/mips/netlogic')
-rw-r--r--arch/mips/netlogic/Kconfig9
-rw-r--r--arch/mips/netlogic/common/earlycons.c2
-rw-r--r--arch/mips/netlogic/common/irq.c72
-rw-r--r--arch/mips/netlogic/common/reset.S63
-rw-r--r--arch/mips/netlogic/common/smp.c8
-rw-r--r--arch/mips/netlogic/common/smpboot.S4
-rw-r--r--arch/mips/netlogic/dts/Makefile1
-rw-r--r--arch/mips/netlogic/dts/xlp_gvp.dts76
-rw-r--r--arch/mips/netlogic/xlp/dt.c7
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c71
-rw-r--r--arch/mips/netlogic/xlp/setup.c25
-rw-r--r--arch/mips/netlogic/xlp/usb-init-xlp2.c88
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c92
-rw-r--r--arch/mips/netlogic/xlr/platform.c4
-rw-r--r--arch/mips/netlogic/xlr/setup.c20
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c3
16 files changed, 429 insertions, 116 deletions
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 852a4ee09954..4eb683aef7d7 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -28,6 +28,15 @@ config DT_XLP_FVP
28 pointer to the kernel. The corresponding DTS file is at 28 pointer to the kernel. The corresponding DTS file is at
29 arch/mips/netlogic/dts/xlp_fvp.dts 29 arch/mips/netlogic/dts/xlp_fvp.dts
30 30
31config DT_XLP_GVP
32 bool "Built-in device tree for XLP GVP boards"
33 default y
34 help
35 Add an FDT blob for XLP GVP board into the kernel.
36 This DTB will be used if the firmware does not pass in a DTB
37 pointer to the kernel. The corresponding DTS file is at
38 arch/mips/netlogic/dts/xlp_gvp.dts
39
31config NLM_MULTINODE 40config NLM_MULTINODE
32 bool "Support for multi-chip boards" 41 bool "Support for multi-chip boards"
33 depends on NLM_XLP_BOARD 42 depends on NLM_XLP_BOARD
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
index 1902fa22d277..769f93032c53 100644
--- a/arch/mips/netlogic/common/earlycons.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -37,9 +37,11 @@
37 37
38#include <asm/mipsregs.h> 38#include <asm/mipsregs.h>
39#include <asm/netlogic/haldefs.h> 39#include <asm/netlogic/haldefs.h>
40#include <asm/netlogic/common.h>
40 41
41#if defined(CONFIG_CPU_XLP) 42#if defined(CONFIG_CPU_XLP)
42#include <asm/netlogic/xlp-hal/iomap.h> 43#include <asm/netlogic/xlp-hal/iomap.h>
44#include <asm/netlogic/xlp-hal/xlp.h>
43#include <asm/netlogic/xlp-hal/uart.h> 45#include <asm/netlogic/xlp-hal/uart.h>
44#elif defined(CONFIG_CPU_XLR) 46#elif defined(CONFIG_CPU_XLR)
45#include <asm/netlogic/xlr/iomap.h> 47#include <asm/netlogic/xlr/iomap.h>
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index 1c7e3a1b81ab..5afc4b7fce0f 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -180,6 +180,7 @@ static void __init nlm_init_percpu_irqs(void)
180#endif 180#endif
181} 181}
182 182
183
183void nlm_setup_pic_irq(int node, int picirq, int irq, int irt) 184void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
184{ 185{
185 struct nlm_pic_irq *pic_data; 186 struct nlm_pic_irq *pic_data;
@@ -207,32 +208,32 @@ void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
207 208
208static void nlm_init_node_irqs(int node) 209static void nlm_init_node_irqs(int node)
209{ 210{
210 int i, irt;
211 uint64_t irqmask;
212 struct nlm_soc_info *nodep; 211 struct nlm_soc_info *nodep;
212 int i, irt;
213 213
214 pr_info("Init IRQ for node %d\n", node); 214 pr_info("Init IRQ for node %d\n", node);
215 nodep = nlm_get_node(node); 215 nodep = nlm_get_node(node);
216 irqmask = PERCPU_IRQ_MASK; 216 nodep->irqmask = PERCPU_IRQ_MASK;
217 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) { 217 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
218 irt = nlm_irq_to_irt(i); 218 irt = nlm_irq_to_irt(i);
219 if (irt == -1) 219 if (irt == -1) /* unused irq */
220 continue; 220 continue;
221 nlm_setup_pic_irq(node, i, i, irt); 221 nodep->irqmask |= 1ull << i;
222 /* set interrupts to first cpu in node */ 222 if (irt == -2) /* not a direct PIC irq */
223 continue;
224
223 nlm_pic_init_irt(nodep->picbase, irt, i, 225 nlm_pic_init_irt(nodep->picbase, irt, i,
224 node * NLM_CPUS_PER_NODE, 0); 226 node * nlm_threads_per_node(), 0);
225 irqmask |= (1ull << i); 227 nlm_setup_pic_irq(node, i, i, irt);
226 } 228 }
227 nodep->irqmask = irqmask;
228} 229}
229 230
230void nlm_smp_irq_init(int hwcpuid) 231void nlm_smp_irq_init(int hwcpuid)
231{ 232{
232 int node, cpu; 233 int node, cpu;
233 234
234 node = hwcpuid / NLM_CPUS_PER_NODE; 235 node = nlm_cpuid_to_node(hwcpuid);
235 cpu = hwcpuid % NLM_CPUS_PER_NODE; 236 cpu = hwcpuid % nlm_threads_per_node();
236 237
237 if (cpu == 0 && node != 0) 238 if (cpu == 0 && node != 0)
238 nlm_init_node_irqs(node); 239 nlm_init_node_irqs(node);
@@ -256,13 +257,23 @@ asmlinkage void plat_irq_dispatch(void)
256 return; 257 return;
257 } 258 }
258 259
260#if defined(CONFIG_PCI_MSI) && defined(CONFIG_CPU_XLP)
261 /* PCI interrupts need a second level dispatch for MSI bits */
262 if (i >= PIC_PCIE_LINK_MSI_IRQ(0) && i <= PIC_PCIE_LINK_MSI_IRQ(3)) {
263 nlm_dispatch_msi(node, i);
264 return;
265 }
266 if (i >= PIC_PCIE_MSIX_IRQ(0) && i <= PIC_PCIE_MSIX_IRQ(3)) {
267 nlm_dispatch_msix(node, i);
268 return;
269 }
270
271#endif
259 /* top level irq handling */ 272 /* top level irq handling */
260 do_IRQ(nlm_irq_to_xirq(node, i)); 273 do_IRQ(nlm_irq_to_xirq(node, i));
261} 274}
262 275
263#ifdef CONFIG_OF 276#ifdef CONFIG_OF
264static struct irq_domain *xlp_pic_domain;
265
266static const struct irq_domain_ops xlp_pic_irq_domain_ops = { 277static const struct irq_domain_ops xlp_pic_irq_domain_ops = {
267 .xlate = irq_domain_xlate_onetwocell, 278 .xlate = irq_domain_xlate_onetwocell,
268}; 279};
@@ -271,8 +282,9 @@ static int __init xlp_of_pic_init(struct device_node *node,
271 struct device_node *parent) 282 struct device_node *parent)
272{ 283{
273 const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1; 284 const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1;
285 struct irq_domain *xlp_pic_domain;
274 struct resource res; 286 struct resource res;
275 int socid, ret; 287 int socid, ret, bus;
276 288
277 /* we need a hack to get the PIC's SoC chip id */ 289 /* we need a hack to get the PIC's SoC chip id */
278 ret = of_address_to_resource(node, 0, &res); 290 ret = of_address_to_resource(node, 0, &res);
@@ -280,7 +292,34 @@ static int __init xlp_of_pic_init(struct device_node *node,
280 pr_err("PIC %s: reg property not found!\n", node->name); 292 pr_err("PIC %s: reg property not found!\n", node->name);
281 return -EINVAL; 293 return -EINVAL;
282 } 294 }
283 socid = (res.start >> 18) & 0x3; 295
296 if (cpu_is_xlp9xx()) {
297 bus = (res.start >> 20) & 0xf;
298 for (socid = 0; socid < NLM_NR_NODES; socid++) {
299 if (!nlm_node_present(socid))
300 continue;
301 if (nlm_get_node(socid)->socbus == bus)
302 break;
303 }
304 if (socid == NLM_NR_NODES) {
305 pr_err("PIC %s: Node mapping for bus %d not found!\n",
306 node->name, bus);
307 return -EINVAL;
308 }
309 } else {
310 socid = (res.start >> 18) & 0x3;
311 if (!nlm_node_present(socid)) {
312 pr_err("PIC %s: node %d does not exist!\n",
313 node->name, socid);
314 return -EINVAL;
315 }
316 }
317
318 if (!nlm_node_present(socid)) {
319 pr_err("PIC %s: node %d does not exist!\n", node->name, socid);
320 return -EINVAL;
321 }
322
284 xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs, 323 xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs,
285 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE, 324 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE,
286 &xlp_pic_irq_domain_ops, NULL); 325 &xlp_pic_irq_domain_ops, NULL);
@@ -288,8 +327,7 @@ static int __init xlp_of_pic_init(struct device_node *node,
288 pr_err("PIC %s: Creating legacy domain failed!\n", node->name); 327 pr_err("PIC %s: Creating legacy domain failed!\n", node->name);
289 return -EINVAL; 328 return -EINVAL;
290 } 329 }
291 pr_info("Node %d: IRQ domain created for PIC@%pa\n", socid, 330 pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res);
292 &res.start);
293 return 0; 331 return 0;
294} 332}
295 333
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index adb18288a6c0..b231fe1e7a09 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -32,10 +32,10 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36 35
37#include <asm/asm.h> 36#include <asm/asm.h>
38#include <asm/asm-offsets.h> 37#include <asm/asm-offsets.h>
38#include <asm/cacheops.h>
39#include <asm/regdef.h> 39#include <asm/regdef.h>
40#include <asm/mipsregs.h> 40#include <asm/mipsregs.h>
41#include <asm/stackframe.h> 41#include <asm/stackframe.h>
@@ -50,8 +50,8 @@
50#include <asm/netlogic/xlp-hal/cpucontrol.h> 50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51 51
52#define CP0_EBASE $15 52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 53#define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 54 XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4 55 SYS_CPU_NONCOHERENT_MODE * 4
56 56
57/* Enable XLP features and workarounds in the LSU */ 57/* Enable XLP features and workarounds in the LSU */
@@ -74,35 +74,55 @@
74.endm 74.endm
75 75
76/* 76/*
77 * Low level flush for L1D cache on XLP, the normal cache ops does 77 * L1D cache has to be flushed before enabling threads in XLP.
78 * not do the complete and correct cache flush. 78 * On XLP8xx/XLP3xx, we do a low level flush using processor control
79 * registers. On XLPII CPUs, usual cache instructions work.
79 */ 80 */
80.macro xlp_flush_l1_dcache 81.macro xlp_flush_l1_dcache
82 mfc0 t0, CP0_EBASE, 0
83 andi t0, t0, 0xff00
84 slt t1, t0, 0x1200
85 beqz t1, 15f
86 nop
87
88 /* XLP8xx low level cache flush */
81 li t0, LSU_DEBUG_DATA0 89 li t0, LSU_DEBUG_DATA0
82 li t1, LSU_DEBUG_ADDR 90 li t1, LSU_DEBUG_ADDR
83 li t2, 0 /* index */ 91 li t2, 0 /* index */
84 li t3, 0x1000 /* loop count */ 92 li t3, 0x1000 /* loop count */
851: 9311:
86 sll v0, t2, 5 94 sll v0, t2, 5
87 mtcr zero, t0 95 mtcr zero, t0
88 ori v1, v0, 0x3 /* way0 | write_enable | write_active */ 96 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
89 mtcr v1, t1 97 mtcr v1, t1
902: 9812:
91 mfcr v1, t1 99 mfcr v1, t1
92 andi v1, 0x1 /* wait for write_active == 0 */ 100 andi v1, 0x1 /* wait for write_active == 0 */
93 bnez v1, 2b 101 bnez v1, 12b
94 nop 102 nop
95 mtcr zero, t0 103 mtcr zero, t0
96 ori v1, v0, 0x7 /* way1 | write_enable | write_active */ 104 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
97 mtcr v1, t1 105 mtcr v1, t1
983: 10613:
99 mfcr v1, t1 107 mfcr v1, t1
100 andi v1, 0x1 /* wait for write_active == 0 */ 108 andi v1, 0x1 /* wait for write_active == 0 */
101 bnez v1, 3b 109 bnez v1, 13b
102 nop 110 nop
103 addi t2, 1 111 addi t2, 1
104 bne t3, t2, 1b 112 bne t3, t2, 11b
113 nop
114 b 17f
115 nop
116
117 /* XLPII CPUs, Invalidate all 64k of L1 D-cache */
11815:
119 li t0, 0x80000000
120 li t1, 0x80010000
12116: cache Index_Writeback_Inv_D, 0(t0)
122 addiu t0, t0, 32
123 bne t0, t1, 16b
105 nop 124 nop
12517:
106.endm 126.endm
107 127
108/* 128/*
@@ -138,6 +158,13 @@ FEXPORT(nlm_reset_entry)
138 nop 158 nop
139 159
1401: /* Entry point on core wakeup */ 1601: /* Entry point on core wakeup */
161 mfc0 t0, CP0_EBASE, 0 /* processor ID */
162 andi t0, 0xff00
163 li t1, 0x1500 /* XLP 9xx */
164 beq t0, t1, 2f /* does not need to set coherent */
165 nop
166
167 /* set bit in SYS coherent register for the core */
141 mfc0 t0, CP0_EBASE, 1 168 mfc0 t0, CP0_EBASE, 1
142 mfc0 t1, CP0_EBASE, 1 169 mfc0 t1, CP0_EBASE, 1
143 srl t1, 5 170 srl t1, 5
@@ -149,7 +176,7 @@ FEXPORT(nlm_reset_entry)
149 li t1, 0x1 176 li t1, 0x1
150 sll t0, t1, t0 177 sll t0, t1, t0
151 nor t0, t0, zero /* t0 <- ~(1 << core) */ 178 nor t0, t0, zero /* t0 <- ~(1 << core) */
152 li t2, SYS_CPU_COHERENT_BASE(0) 179 li t2, SYS_CPU_COHERENT_BASE
153 add t2, t2, t3 /* t2 <- SYS offset for node */ 180 add t2, t2, t3 /* t2 <- SYS offset for node */
154 lw t1, 0(t2) 181 lw t1, 0(t2)
155 and t1, t1, t0 182 and t1, t1, t0
@@ -159,13 +186,13 @@ FEXPORT(nlm_reset_entry)
159 lw t1, 0(t2) 186 lw t1, 0(t2)
160 sync 187 sync
161 188
1892:
162 /* Configure LSU on Non-0 Cores. */ 190 /* Configure LSU on Non-0 Cores. */
163 xlp_config_lsu 191 xlp_config_lsu
164 /* FALL THROUGH */ 192 /* FALL THROUGH */
165 193
166/* 194/*
167 * Wake up sibling threads from the initial thread in 195 * Wake up sibling threads from the initial thread in a core.
168 * a core.
169 */ 196 */
170EXPORT(nlm_boot_siblings) 197EXPORT(nlm_boot_siblings)
171 /* core L1D flush before enable threads */ 198 /* core L1D flush before enable threads */
@@ -181,8 +208,10 @@ EXPORT(nlm_boot_siblings)
181 /* 208 /*
182 * The new hardware thread starts at the next instruction 209 * The new hardware thread starts at the next instruction
183 * For all the cases other than core 0 thread 0, we will 210 * For all the cases other than core 0 thread 0, we will
184 * jump to the secondary wait function. 211 * jump to the secondary wait function.
185 */ 212
213 * NOTE: All GPR contents are lost after the mtcr above!
214 */
186 mfc0 v0, CP0_EBASE, 1 215 mfc0 v0, CP0_EBASE, 1
187 andi v0, 0x3ff /* v0 <- node/core */ 216 andi v0, 0x3ff /* v0 <- node/core */
188 217
@@ -196,7 +225,7 @@ EXPORT(nlm_boot_siblings)
196#endif 225#endif
197 mtc0 t1, CP0_STATUS 226 mtc0 t1, CP0_STATUS
198 227
199 /* mark CPU ready, careful here, previous mtcr trashed registers */ 228 /* mark CPU ready */
200 li t3, CKSEG1ADDR(RESET_DATA_PHYS) 229 li t3, CKSEG1ADDR(RESET_DATA_PHYS)
201 ADDIU t1, t3, BOOT_CPU_READY 230 ADDIU t1, t3, BOOT_CPU_READY
202 sll v1, v0, 2 231 sll v1, v0, 2
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index c0eded01fde9..6baae15cc7b1 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -63,7 +63,7 @@ void nlm_send_ipi_single(int logical_cpu, unsigned int action)
63 uint64_t picbase; 63 uint64_t picbase;
64 64
65 cpu = cpu_logical_map(logical_cpu); 65 cpu = cpu_logical_map(logical_cpu);
66 node = cpu / NLM_CPUS_PER_NODE; 66 node = nlm_cpuid_to_node(cpu);
67 picbase = nlm_get_node(node)->picbase; 67 picbase = nlm_get_node(node)->picbase;
68 68
69 if (action & SMP_CALL_FUNCTION) 69 if (action & SMP_CALL_FUNCTION)
@@ -152,7 +152,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
152 int cpu, node; 152 int cpu, node;
153 153
154 cpu = cpu_logical_map(logical_cpu); 154 cpu = cpu_logical_map(logical_cpu);
155 node = cpu / NLM_CPUS_PER_NODE; 155 node = nlm_cpuid_to_node(logical_cpu);
156 nlm_next_sp = (unsigned long)__KSTK_TOS(idle); 156 nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
157 nlm_next_gp = (unsigned long)task_thread_info(idle); 157 nlm_next_gp = (unsigned long)task_thread_info(idle);
158 158
@@ -164,7 +164,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
164void __init nlm_smp_setup(void) 164void __init nlm_smp_setup(void)
165{ 165{
166 unsigned int boot_cpu; 166 unsigned int boot_cpu;
167 int num_cpus, i, ncore; 167 int num_cpus, i, ncore, node;
168 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 168 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
169 char buf[64]; 169 char buf[64];
170 170
@@ -187,6 +187,8 @@ void __init nlm_smp_setup(void)
187 __cpu_number_map[i] = num_cpus; 187 __cpu_number_map[i] = num_cpus;
188 __cpu_logical_map[num_cpus] = i; 188 __cpu_logical_map[num_cpus] = i;
189 set_cpu_possible(num_cpus, true); 189 set_cpu_possible(num_cpus, true);
190 node = nlm_cpuid_to_node(i);
191 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
190 ++num_cpus; 192 ++num_cpus;
191 } 193 }
192 } 194 }
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index aa6cff0a229b..8597657c27fc 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -32,7 +32,6 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36 35
37#include <asm/asm.h> 36#include <asm/asm.h>
38#include <asm/asm-offsets.h> 37#include <asm/asm-offsets.h>
@@ -98,7 +97,7 @@ END(nlm_boot_secondary_cpus)
98 * In case of RMIboot bootloader which is used on XLR boards, the CPUs 97 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
99 * be already woken up and waiting in bootloader code. 98 * be already woken up and waiting in bootloader code.
100 * This will get them out of the bootloader code and into linux. Needed 99 * This will get them out of the bootloader code and into linux. Needed
101 * because the bootloader area will be taken and initialized by linux. 100 * because the bootloader area will be taken and initialized by linux.
102 */ 101 */
103NESTED(nlm_rmiboot_preboot, 16, sp) 102NESTED(nlm_rmiboot_preboot, 16, sp)
104 mfc0 t0, $15, 1 /* read ebase */ 103 mfc0 t0, $15, 1 /* read ebase */
@@ -133,6 +132,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
133 or t1, t2, v1 /* put in new value */ 132 or t1, t2, v1 /* put in new value */
134 mtcr t1, t0 /* update core control */ 133 mtcr t1, t0 /* update core control */
135 134
135 /* wait for NMI to hit */
1361: wait 1361: wait
137 b 1b 137 b 1b
138 nop 138 nop
diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile
index 0b9be5fd2e46..25c8e873ee25 100644
--- a/arch/mips/netlogic/dts/Makefile
+++ b/arch/mips/netlogic/dts/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o 1obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
2obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o 2obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
3obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o 3obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o
4obj-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb.o
diff --git a/arch/mips/netlogic/dts/xlp_gvp.dts b/arch/mips/netlogic/dts/xlp_gvp.dts
new file mode 100644
index 000000000000..047d27f54487
--- /dev/null
+++ b/arch/mips/netlogic/dts/xlp_gvp.dts
@@ -0,0 +1,76 @@
1/*
2 * XLP9XX Device Tree Source for GVP boards
3 */
4
5/dts-v1/;
6/ {
7 model = "netlogic,XLP-GVP";
8 compatible = "netlogic,xlp";
9 #address-cells = <2>;
10 #size-cells = <2>;
11
12 soc {
13 #address-cells = <2>;
14 #size-cells = <1>;
15 compatible = "simple-bus";
16 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
17 1 0 0 0x16000000 0x02000000>; // GBU chipselects
18
19 serial0: serial@30000 {
20 device_type = "serial";
21 compatible = "ns16550";
22 reg = <0 0x112100 0xa00>;
23 reg-shift = <2>;
24 reg-io-width = <4>;
25 clock-frequency = <125000000>;
26 interrupt-parent = <&pic>;
27 interrupts = <17>;
28 };
29 pic: pic@4000 {
30 interrupt-controller;
31 #address-cells = <0>;
32 #interrupt-cells = <1>;
33 reg = <0 0x110000 0x200>;
34 };
35
36 nor_flash@1,0 {
37 compatible = "cfi-flash";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 bank-width = <2>;
41 reg = <1 0 0x1000000>;
42
43 partition@0 {
44 label = "x-loader";
45 reg = <0x0 0x100000>; /* 1M */
46 read-only;
47 };
48
49 partition@100000 {
50 label = "u-boot";
51 reg = <0x100000 0x100000>; /* 1M */
52 };
53
54 partition@200000 {
55 label = "kernel";
56 reg = <0x200000 0x500000>; /* 5M */
57 };
58
59 partition@700000 {
60 label = "rootfs";
61 reg = <0x700000 0x800000>; /* 8M */
62 };
63
64 partition@f00000 {
65 label = "env";
66 reg = <0xf00000 0x100000>; /* 1M */
67 read-only;
68 };
69 };
70
71 };
72
73 chosen {
74 bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
75 };
76};
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
index 8316d5454b17..5754097b9cde 100644
--- a/arch/mips/netlogic/xlp/dt.c
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -42,13 +42,18 @@
42#include <asm/prom.h> 42#include <asm/prom.h>
43 43
44extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], 44extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
45 __dtb_xlp_fvp_begin[], __dtb_start[]; 45 __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[], __dtb_start[];
46static void *xlp_fdt_blob; 46static void *xlp_fdt_blob;
47 47
48void __init *xlp_dt_init(void *fdtp) 48void __init *xlp_dt_init(void *fdtp)
49{ 49{
50 if (!fdtp) { 50 if (!fdtp) {
51 switch (current_cpu_data.processor_id & 0xff00) { 51 switch (current_cpu_data.processor_id & 0xff00) {
52#ifdef CONFIG_DT_XLP_GVP
53 case PRID_IMP_NETLOGIC_XLP9XX:
54 fdtp = __dtb_xlp_gvp_begin;
55 break;
56#endif
52#ifdef CONFIG_DT_XLP_FVP 57#ifdef CONFIG_DT_XLP_FVP
53 case PRID_IMP_NETLOGIC_XLP2XX: 58 case PRID_IMP_NETLOGIC_XLP2XX:
54 fdtp = __dtb_xlp_fvp_begin; 59 fdtp = __dtb_xlp_fvp_begin;
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 56c50ba43c9b..997cd9ee10de 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -57,6 +57,10 @@ void nlm_node_init(int node)
57 nodep->sysbase = nlm_get_sys_regbase(node); 57 nodep->sysbase = nlm_get_sys_regbase(node);
58 nodep->picbase = nlm_get_pic_regbase(node); 58 nodep->picbase = nlm_get_pic_regbase(node);
59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); 59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
60 if (cpu_is_xlp9xx())
61 nodep->socbus = xlp9xx_get_socbus(node);
62 else
63 nodep->socbus = 0;
60 spin_lock_init(&nodep->piclock); 64 spin_lock_init(&nodep->piclock);
61} 65}
62 66
@@ -65,6 +69,26 @@ int nlm_irq_to_irt(int irq)
65 uint64_t pcibase; 69 uint64_t pcibase;
66 int devoff, irt; 70 int devoff, irt;
67 71
72 /* bypass for 9xx */
73 if (cpu_is_xlp9xx()) {
74 switch (irq) {
75 case PIC_9XX_XHCI_0_IRQ:
76 return 114;
77 case PIC_9XX_XHCI_1_IRQ:
78 return 115;
79 case PIC_UART_0_IRQ:
80 return 133;
81 case PIC_UART_1_IRQ:
82 return 134;
83 case PIC_PCIE_LINK_LEGACY_IRQ(0):
84 case PIC_PCIE_LINK_LEGACY_IRQ(1):
85 case PIC_PCIE_LINK_LEGACY_IRQ(2):
86 case PIC_PCIE_LINK_LEGACY_IRQ(3):
87 return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
88 }
89 return -1;
90 }
91
68 devoff = 0; 92 devoff = 0;
69 switch (irq) { 93 switch (irq) {
70 case PIC_UART_0_IRQ: 94 case PIC_UART_0_IRQ:
@@ -135,9 +159,17 @@ int nlm_irq_to_irt(int irq)
135 case PIC_I2C_3_IRQ: 159 case PIC_I2C_3_IRQ:
136 irt = irt + 3; break; 160 irt = irt + 3; break;
137 } 161 }
138 } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) { 162 } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
163 irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
139 /* HW bug, PCI IRT entries are bad on early silicon, fix */ 164 /* HW bug, PCI IRT entries are bad on early silicon, fix */
140 irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ); 165 irt = PIC_IRT_PCIE_LINK_INDEX(irq -
166 PIC_PCIE_LINK_LEGACY_IRQ_BASE);
167 } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
168 irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
169 irt = -2;
170 } else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
171 irq <= PIC_PCIE_MSIX_IRQ(3)) {
172 irt = -2;
141 } else { 173 } else {
142 irt = -1; 174 irt = -1;
143 } 175 }
@@ -151,7 +183,10 @@ unsigned int nlm_get_core_frequency(int node, int core)
151 uint64_t num, sysbase; 183 uint64_t num, sysbase;
152 184
153 sysbase = nlm_get_node(node)->sysbase; 185 sysbase = nlm_get_node(node)->sysbase;
154 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); 186 if (cpu_is_xlp9xx())
187 rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
188 else
189 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
155 if (cpu_is_xlpii()) { 190 if (cpu_is_xlpii()) {
156 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26)); 191 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
157 denom = 3; 192 denom = 3;
@@ -265,6 +300,10 @@ static unsigned int nlm_2xx_get_pic_frequency(int node)
265 300
266unsigned int nlm_get_pic_frequency(int node) 301unsigned int nlm_get_pic_frequency(int node)
267{ 302{
303 /* TODO Has to calculate freq as like 2xx */
304 if (cpu_is_xlp9xx())
305 return 250000000;
306
268 if (cpu_is_xlpii()) 307 if (cpu_is_xlpii())
269 return nlm_2xx_get_pic_frequency(node); 308 return nlm_2xx_get_pic_frequency(node);
270 else 309 else
@@ -284,21 +323,33 @@ int xlp_get_dram_map(int n, uint64_t *dram_map)
284{ 323{
285 uint64_t bridgebase, base, lim; 324 uint64_t bridgebase, base, lim;
286 uint32_t val; 325 uint32_t val;
326 unsigned int barreg, limreg, xlatreg;
287 int i, node, rv; 327 int i, node, rv;
288 328
289 /* Look only at mapping on Node 0, we don't handle crazy configs */ 329 /* Look only at mapping on Node 0, we don't handle crazy configs */
290 bridgebase = nlm_get_bridge_regbase(0); 330 bridgebase = nlm_get_bridge_regbase(0);
291 rv = 0; 331 rv = 0;
292 for (i = 0; i < 8; i++) { 332 for (i = 0; i < 8; i++) {
293 val = nlm_read_bridge_reg(bridgebase, 333 if (cpu_is_xlp9xx()) {
294 BRIDGE_DRAM_NODE_TRANSLN(i)); 334 barreg = BRIDGE_9XX_DRAM_BAR(i);
295 node = (val >> 1) & 0x3; 335 limreg = BRIDGE_9XX_DRAM_LIMIT(i);
296 if (n >= 0 && n != node) 336 xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
297 continue; 337 } else {
298 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i)); 338 barreg = BRIDGE_DRAM_BAR(i);
339 limreg = BRIDGE_DRAM_LIMIT(i);
340 xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
341 }
342 if (n >= 0) {
343 /* node specified, get node mapping of BAR */
344 val = nlm_read_bridge_reg(bridgebase, xlatreg);
345 node = (val >> 1) & 0x3;
346 if (n != node)
347 continue;
348 }
349 val = nlm_read_bridge_reg(bridgebase, barreg);
299 val = (val >> 12) & 0xfffff; 350 val = (val >> 12) & 0xfffff;
300 base = (uint64_t) val << 20; 351 base = (uint64_t) val << 20;
301 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i)); 352 val = nlm_read_bridge_reg(bridgebase, limreg);
302 val = (val >> 12) & 0xfffff; 353 val = (val >> 12) & 0xfffff;
303 if (val == 0) /* BAR not used */ 354 if (val == 0) /* BAR not used */
304 continue; 355 continue;
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 54e75c77184b..8c60a2dd9ef6 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -51,12 +51,16 @@ uint64_t nlm_io_base;
51struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 51struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
52cpumask_t nlm_cpumask = CPU_MASK_CPU0; 52cpumask_t nlm_cpumask = CPU_MASK_CPU0;
53unsigned int nlm_threads_per_core; 53unsigned int nlm_threads_per_core;
54unsigned int xlp_cores_per_node;
54 55
55static void nlm_linux_exit(void) 56static void nlm_linux_exit(void)
56{ 57{
57 uint64_t sysbase = nlm_get_node(0)->sysbase; 58 uint64_t sysbase = nlm_get_node(0)->sysbase;
58 59
59 nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1); 60 if (cpu_is_xlp9xx())
61 nlm_write_sys_reg(sysbase, SYS_9XX_CHIP_RESET, 1);
62 else
63 nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
60 for ( ; ; ) 64 for ( ; ; )
61 cpu_wait(); 65 cpu_wait();
62} 66}
@@ -92,6 +96,14 @@ static void __init xlp_init_mem_from_bars(void)
92 96
93void __init plat_mem_setup(void) 97void __init plat_mem_setup(void)
94{ 98{
99#ifdef CONFIG_SMP
100 nlm_wakeup_secondary_cpus();
101
102 /* update TLB size after waking up threads */
103 current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
104
105 register_smp_ops(&nlm_smp_ops);
106#endif
95 _machine_restart = (void (*)(char *))nlm_linux_exit; 107 _machine_restart = (void (*)(char *))nlm_linux_exit;
96 _machine_halt = nlm_linux_exit; 108 _machine_halt = nlm_linux_exit;
97 pm_power_off = nlm_linux_exit; 109 pm_power_off = nlm_linux_exit;
@@ -110,6 +122,7 @@ void __init plat_mem_setup(void)
110const char *get_system_type(void) 122const char *get_system_type(void)
111{ 123{
112 switch (read_c0_prid() & 0xff00) { 124 switch (read_c0_prid() & 0xff00) {
125 case PRID_IMP_NETLOGIC_XLP9XX:
113 case PRID_IMP_NETLOGIC_XLP2XX: 126 case PRID_IMP_NETLOGIC_XLP2XX:
114 return "Broadcom XLPII Series"; 127 return "Broadcom XLPII Series";
115 default: 128 default:
@@ -149,6 +162,10 @@ void __init prom_init(void)
149 void *reset_vec; 162 void *reset_vec;
150 163
151 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); 164 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
165 if (cpu_is_xlp9xx())
166 xlp_cores_per_node = 32;
167 else
168 xlp_cores_per_node = 8;
152 nlm_init_boot_cpu(); 169 nlm_init_boot_cpu();
153 xlp_mmu_init(); 170 xlp_mmu_init();
154 nlm_node_init(0); 171 nlm_node_init(0);
@@ -162,11 +179,5 @@ void __init prom_init(void)
162 179
163#ifdef CONFIG_SMP 180#ifdef CONFIG_SMP
164 cpumask_setall(&nlm_cpumask); 181 cpumask_setall(&nlm_cpumask);
165 nlm_wakeup_secondary_cpus();
166
167 /* update TLB size after waking up threads */
168 current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
169
170 register_smp_ops(&nlm_smp_ops);
171#endif 182#endif
172} 183}
diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c
index 36e9c22afc46..17ade1ce5dfd 100644
--- a/arch/mips/netlogic/xlp/usb-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c
@@ -37,6 +37,7 @@
37#include <linux/delay.h> 37#include <linux/delay.h>
38#include <linux/init.h> 38#include <linux/init.h>
39#include <linux/pci.h> 39#include <linux/pci.h>
40#include <linux/pci_ids.h>
40#include <linux/platform_device.h> 41#include <linux/platform_device.h>
41#include <linux/irq.h> 42#include <linux/irq.h>
42 43
@@ -83,12 +84,14 @@
83#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) 84#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
84#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) 85#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
85 86
86#define nlm_xlpii_get_usb_pcibase(node, inst) \ 87#define nlm_xlpii_get_usb_pcibase(node, inst) \
87 nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst)) 88 nlm_pcicfg_base(cpu_is_xlp9xx() ? \
89 XLP9XX_IO_USB_OFFSET(node, inst) : \
90 XLP2XX_IO_USB_OFFSET(node, inst))
88#define nlm_xlpii_get_usb_regbase(node, inst) \ 91#define nlm_xlpii_get_usb_regbase(node, inst) \
89 (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 92 (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
90 93
91static void xlpii_usb_ack(struct irq_data *data) 94static void xlp2xx_usb_ack(struct irq_data *data)
92{ 95{
93 u64 port_addr; 96 u64 port_addr;
94 97
@@ -109,6 +112,29 @@ static void xlpii_usb_ack(struct irq_data *data)
109 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); 112 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
110} 113}
111 114
115static void xlp9xx_usb_ack(struct irq_data *data)
116{
117 u64 port_addr;
118 int node, irq;
119
120 /* Find the node and irq on the node */
121 irq = data->irq % NLM_IRQS_PER_NODE;
122 node = data->irq / NLM_IRQS_PER_NODE;
123
124 switch (irq) {
125 case PIC_9XX_XHCI_0_IRQ:
126 port_addr = nlm_xlpii_get_usb_regbase(node, 1);
127 break;
128 case PIC_9XX_XHCI_1_IRQ:
129 port_addr = nlm_xlpii_get_usb_regbase(node, 2);
130 break;
131 default:
132 pr_err("No matching USB irq %d node %d!\n", irq, node);
133 return;
134 }
135 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
136}
137
112static void nlm_xlpii_usb_hw_reset(int node, int port) 138static void nlm_xlpii_usb_hw_reset(int node, int port)
113{ 139{
114 u64 port_addr, xhci_base, pci_base; 140 u64 port_addr, xhci_base, pci_base;
@@ -178,17 +204,33 @@ static void nlm_xlpii_usb_hw_reset(int node, int port)
178 204
179static int __init nlm_platform_xlpii_usb_init(void) 205static int __init nlm_platform_xlpii_usb_init(void)
180{ 206{
207 int node;
208
181 if (!cpu_is_xlpii()) 209 if (!cpu_is_xlpii())
182 return 0; 210 return 0;
183 211
184 pr_info("Initializing 2XX USB Interface\n"); 212 if (!cpu_is_xlp9xx()) {
185 nlm_xlpii_usb_hw_reset(0, 1); 213 /* XLP 2XX single node */
186 nlm_xlpii_usb_hw_reset(0, 2); 214 pr_info("Initializing 2XX USB Interface\n");
187 nlm_xlpii_usb_hw_reset(0, 3); 215 nlm_xlpii_usb_hw_reset(0, 1);
188 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack); 216 nlm_xlpii_usb_hw_reset(0, 2);
189 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack); 217 nlm_xlpii_usb_hw_reset(0, 3);
190 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack); 218 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlp2xx_usb_ack);
219 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlp2xx_usb_ack);
220 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlp2xx_usb_ack);
221 return 0;
222 }
191 223
224 /* XLP 9XX, multi-node */
225 pr_info("Initializing 9XX USB Interface\n");
226 for (node = 0; node < NLM_NR_NODES; node++) {
227 if (!nlm_node_present(node))
228 continue;
229 nlm_xlpii_usb_hw_reset(node, 1);
230 nlm_xlpii_usb_hw_reset(node, 2);
231 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack);
232 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack);
233 }
192 return 0; 234 return 0;
193} 235}
194 236
@@ -196,8 +238,26 @@ arch_initcall(nlm_platform_xlpii_usb_init);
196 238
197static u64 xlp_usb_dmamask = ~(u32)0; 239static u64 xlp_usb_dmamask = ~(u32)0;
198 240
199/* Fixup IRQ for USB devices on XLP the SoC PCIe bus */ 241/* Fixup the IRQ for USB devices which is exist on XLP9XX SOC PCIE bus */
200static void nlm_usb_fixup_final(struct pci_dev *dev) 242static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev)
243{
244 int node;
245
246 node = xlp_socdev_to_node(dev);
247 dev->dev.dma_mask = &xlp_usb_dmamask;
248 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
249 switch (dev->devfn) {
250 case 0x21:
251 dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_0_IRQ);
252 break;
253 case 0x22:
254 dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ);
255 break;
256 }
257}
258
259/* Fixup the IRQ for USB devices which is exist on XLP2XX SOC PCIE bus */
260static void nlm_xlp2xx_usb_fixup_final(struct pci_dev *dev)
201{ 261{
202 dev->dev.dma_mask = &xlp_usb_dmamask; 262 dev->dev.dma_mask = &xlp_usb_dmamask;
203 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 263 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
@@ -214,5 +274,7 @@ static void nlm_usb_fixup_final(struct pci_dev *dev)
214 } 274 }
215} 275}
216 276
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_XHCI,
278 nlm_xlp9xx_usb_fixup_final);
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI, 279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
218 nlm_usb_fixup_final); 280 nlm_xlp2xx_usb_fixup_final);
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index 682d5638dc01..9a92617a2af5 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -32,7 +32,6 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36#include <linux/kernel.h> 35#include <linux/kernel.h>
37#include <linux/threads.h> 36#include <linux/threads.h>
38 37
@@ -47,14 +46,14 @@
47#include <asm/netlogic/mips-extns.h> 46#include <asm/netlogic/mips-extns.h>
48 47
49#include <asm/netlogic/xlp-hal/iomap.h> 48#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/pic.h>
51#include <asm/netlogic/xlp-hal/xlp.h> 49#include <asm/netlogic/xlp-hal/xlp.h>
50#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/sys.h> 51#include <asm/netlogic/xlp-hal/sys.h>
53 52
54static int xlp_wakeup_core(uint64_t sysbase, int node, int core) 53static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
55{ 54{
56 uint32_t coremask, value; 55 uint32_t coremask, value;
57 int count; 56 int count, resetreg;
58 57
59 coremask = (1 << core); 58 coremask = (1 << core);
60 59
@@ -65,12 +64,24 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
65 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); 64 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
66 } 65 }
67 66
67 /* On 9XX, mark coherent first */
68 if (cpu_is_xlp9xx()) {
69 value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
70 value &= ~coremask;
71 nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
72 }
73
68 /* Remove CPU Reset */ 74 /* Remove CPU Reset */
69 value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET); 75 resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
76 value = nlm_read_sys_reg(sysbase, resetreg);
70 value &= ~coremask; 77 value &= ~coremask;
71 nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value); 78 nlm_write_sys_reg(sysbase, resetreg, value);
79
80 /* We are done on 9XX */
81 if (cpu_is_xlp9xx())
82 return 1;
72 83
73 /* Poll for CPU to mark itself coherent */ 84 /* Poll for CPU to mark itself coherent on other type of XLP */
74 count = 100000; 85 count = 100000;
75 do { 86 do {
76 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE); 87 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
@@ -84,7 +95,7 @@ static int wait_for_cpus(int cpu, int bootcpu)
84 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 95 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
85 int i, count, notready; 96 int i, count, notready;
86 97
87 count = 0x20000000; 98 count = 0x800000;
88 do { 99 do {
89 notready = nlm_threads_per_core; 100 notready = nlm_threads_per_core;
90 for (i = 0; i < nlm_threads_per_core; i++) 101 for (i = 0; i < nlm_threads_per_core; i++)
@@ -98,27 +109,62 @@ static int wait_for_cpus(int cpu, int bootcpu)
98static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) 109static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
99{ 110{
100 struct nlm_soc_info *nodep; 111 struct nlm_soc_info *nodep;
101 uint64_t syspcibase; 112 uint64_t syspcibase, fusebase;
102 uint32_t syscoremask; 113 uint32_t syscoremask, mask, fusemask;
103 int core, n, cpu; 114 int core, n, cpu;
104 115
105 for (n = 0; n < NLM_NR_NODES; n++) { 116 for (n = 0; n < NLM_NR_NODES; n++) {
106 syspcibase = nlm_get_sys_pcibase(n); 117 if (n != 0) {
107 if (nlm_read_reg(syspcibase, 0) == 0xffffffff) 118 /* check if node exists and is online */
108 break; 119 if (cpu_is_xlp9xx()) {
120 int b = xlp9xx_get_socbus(n);
121 pr_info("Node %d SoC PCI bus %d.\n", n, b);
122 if (b == 0)
123 break;
124 } else {
125 syspcibase = nlm_get_sys_pcibase(n);
126 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
127 break;
128 }
129 nlm_node_init(n);
130 }
109 131
110 /* read cores in reset from SYS */ 132 /* read cores in reset from SYS */
111 if (n != 0)
112 nlm_node_init(n);
113 nodep = nlm_get_node(n); 133 nodep = nlm_get_node(n);
114 syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET); 134
135 if (cpu_is_xlp9xx()) {
136 fusebase = nlm_get_fuse_regbase(n);
137 fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
138 mask = 0xfffff;
139 } else {
140 fusemask = nlm_read_sys_reg(nodep->sysbase,
141 SYS_EFUSE_DEVICE_CFG_STATUS0);
142 switch (read_c0_prid() & 0xff00) {
143 case PRID_IMP_NETLOGIC_XLP3XX:
144 mask = 0xf;
145 break;
146 case PRID_IMP_NETLOGIC_XLP2XX:
147 mask = 0x3;
148 break;
149 case PRID_IMP_NETLOGIC_XLP8XX:
150 default:
151 mask = 0xff;
152 break;
153 }
154 }
155
156 /*
157 * Fused out cores are set in the fusemask, and the remaining
158 * cores are renumbered to range 0 .. nactive-1
159 */
160 syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
161
115 /* The boot cpu */ 162 /* The boot cpu */
116 if (n == 0) { 163 if (n == 0)
117 syscoremask |= 1;
118 nodep->coremask = 1; 164 nodep->coremask = 1;
119 }
120 165
121 for (core = 0; core < NLM_CORES_PER_NODE; core++) { 166 pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
167 for (core = 0; core < nlm_cores_per_node(); core++) {
122 /* we will be on node 0 core 0 */ 168 /* we will be on node 0 core 0 */
123 if (n == 0 && core == 0) 169 if (n == 0 && core == 0)
124 continue; 170 continue;
@@ -128,7 +174,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
128 continue; 174 continue;
129 175
130 /* see if at least the first hw thread is enabled */ 176 /* see if at least the first hw thread is enabled */
131 cpu = (n * NLM_CORES_PER_NODE + core) 177 cpu = (n * nlm_cores_per_node() + core)
132 * NLM_THREADS_PER_CORE; 178 * NLM_THREADS_PER_CORE;
133 if (!cpumask_test_cpu(cpu, wakeup_mask)) 179 if (!cpumask_test_cpu(cpu, wakeup_mask))
134 continue; 180 continue;
@@ -141,7 +187,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
141 nodep->coremask |= 1u << core; 187 nodep->coremask |= 1u << core;
142 188
143 /* spin until the hw threads sets their ready */ 189 /* spin until the hw threads sets their ready */
144 wait_for_cpus(cpu, 0); 190 if (!wait_for_cpus(cpu, 0))
191 pr_err("Node %d : timeout core %d\n", n, core);
145 } 192 }
146 } 193 }
147} 194}
@@ -153,7 +200,8 @@ void xlp_wakeup_secondary_cpus()
153 * first wakeup core 0 threads 200 * first wakeup core 0 threads
154 */ 201 */
155 xlp_boot_core0_siblings(); 202 xlp_boot_core0_siblings();
156 wait_for_cpus(0, 0); 203 if (!wait_for_cpus(0, 0))
204 pr_err("Node 0 : timeout core 0\n");
157 205
158 /* now get other cores out of reset */ 206 /* now get other cores out of reset */
159 xlp_enable_secondary_cores(&nlm_cpumask); 207 xlp_enable_secondary_cores(&nlm_cpumask);
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 7b96a91f4773..4785932af248 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -23,7 +23,7 @@
23#include <asm/netlogic/xlr/pic.h> 23#include <asm/netlogic/xlr/pic.h>
24#include <asm/netlogic/xlr/xlr.h> 24#include <asm/netlogic/xlr/xlr.h>
25 25
26unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 26static unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
27{ 27{
28 uint64_t uartbase; 28 uint64_t uartbase;
29 unsigned int value; 29 unsigned int value;
@@ -41,7 +41,7 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
41 return value; 41 return value;
42} 42}
43 43
44void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 44static void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
45{ 45{
46 uint64_t uartbase; 46 uint64_t uartbase;
47 47
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index 921be5f77797..d118b9aa7647 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -60,25 +60,6 @@ unsigned int nlm_threads_per_core = 1;
60struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 60struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
61cpumask_t nlm_cpumask = CPU_MASK_CPU0; 61cpumask_t nlm_cpumask = CPU_MASK_CPU0;
62 62
63static void __init nlm_early_serial_setup(void)
64{
65 struct uart_port s;
66 unsigned long uart_base;
67
68 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
69 memset(&s, 0, sizeof(s));
70 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
71 s.iotype = UPIO_MEM32;
72 s.regshift = 2;
73 s.irq = PIC_UART_0_IRQ;
74 s.uartclk = PIC_CLK_HZ;
75 s.serial_in = nlm_xlr_uart_in;
76 s.serial_out = nlm_xlr_uart_out;
77 s.mapbase = uart_base;
78 s.membase = (unsigned char __iomem *)uart_base;
79 early_serial_setup(&s);
80}
81
82static void nlm_linux_exit(void) 63static void nlm_linux_exit(void)
83{ 64{
84 uint64_t gpiobase; 65 uint64_t gpiobase;
@@ -214,7 +195,6 @@ void __init prom_init(void)
214 memcpy(reset_vec, (void *)nlm_reset_entry, 195 memcpy(reset_vec, (void *)nlm_reset_entry,
215 (nlm_reset_entry_end - nlm_reset_entry)); 196 (nlm_reset_entry_end - nlm_reset_entry));
216 197
217 nlm_early_serial_setup();
218 build_arcs_cmdline(argv); 198 build_arcs_cmdline(argv);
219 prom_add_memory(); 199 prom_add_memory();
220 200
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
index 9fb81fa6272a..d61cba1e9c65 100644
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -32,7 +32,6 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36#include <linux/delay.h> 35#include <linux/delay.h>
37#include <linux/threads.h> 36#include <linux/threads.h>
38 37
@@ -70,7 +69,7 @@ int xlr_wakeup_secondary_cpus(void)
70 69
71 /* Fill up the coremask early */ 70 /* Fill up the coremask early */
72 nodep->coremask = 1; 71 nodep->coremask = 1;
73 for (i = 1; i < NLM_CORES_PER_NODE; i++) { 72 for (i = 1; i < nlm_cores_per_node(); i++) {
74 for (j = 1000000; j > 0; j--) { 73 for (j = 1000000; j > 0; j--) {
75 if (cpu_ready[i * NLM_THREADS_PER_CORE]) 74 if (cpu_ready[i * NLM_THREADS_PER_CORE])
76 break; 75 break;
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-01 14:52:41 -0400