diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2015-04-13 10:03:32 -0400 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-13 10:03:32 -0400 |
commit | 3e20a26b02bd4f24945c87407df51948dd488620 (patch) | |
tree | f466d3b2a47a98ec2910724e17ee2f3a93c1a49e /arch/mips/netlogic | |
parent | 98b0429b7abd5c05efdb23f3eba02ec3f696748e (diff) | |
parent | 5306a5450824691e27d68f711758515debedeeac (diff) |
Merge branch '4.0-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/netlogic')
-rw-r--r-- | arch/mips/netlogic/xlp/ahci-init-xlp2.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/netlogic/xlp/ahci-init-xlp2.c b/arch/mips/netlogic/xlp/ahci-init-xlp2.c index c83dbf3689e2..7b066a44e679 100644 --- a/arch/mips/netlogic/xlp/ahci-init-xlp2.c +++ b/arch/mips/netlogic/xlp/ahci-init-xlp2.c | |||
@@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel) | |||
203 | static void config_sata_phy(u64 regbase) | 203 | static void config_sata_phy(u64 regbase) |
204 | { | 204 | { |
205 | u32 port, i, reg; | 205 | u32 port, i, reg; |
206 | u8 val; | ||
206 | 207 | ||
207 | for (port = 0; port < 2; port++) { | 208 | for (port = 0; port < 2; port++) { |
208 | for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) | 209 | for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) |
@@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase) | |||
210 | 211 | ||
211 | for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) | 212 | for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) |
212 | write_phy_reg(regbase, reg, port, sata_phy_config2[i]); | 213 | write_phy_reg(regbase, reg, port, sata_phy_config2[i]); |
214 | |||
215 | /* Fix for PHY link up failures at lower temperatures */ | ||
216 | write_phy_reg(regbase, 0x800F, port, 0x1f); | ||
217 | |||
218 | val = read_phy_reg(regbase, 0x0029, port); | ||
219 | write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1)); | ||
220 | |||
221 | val = read_phy_reg(regbase, 0x0056, port); | ||
222 | write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3)); | ||
223 | |||
224 | val = read_phy_reg(regbase, 0x0018, port); | ||
225 | write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0)); | ||
213 | } | 226 | } |
214 | } | 227 | } |
215 | 228 | ||