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authorJayachandran C <jayachandranc@netlogicmicro.com>2011-11-11 06:38:29 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:04:55 -0500
commit0c9654072a6e15aa3da9b314f0c5c01e90938268 (patch)
tree865bbcf93aac081b15bf38604384e4bf7620024b /arch/mips/netlogic
parent99fb2f7984726ba03d5634df8e6d26eb891f1ec3 (diff)
MIPS: Netlogic: Move code common with XLP to common/
- Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic')
-rw-r--r--arch/mips/netlogic/Makefile2
-rw-r--r--arch/mips/netlogic/Platform2
-rw-r--r--arch/mips/netlogic/common/Makefile3
-rw-r--r--arch/mips/netlogic/common/earlycons.c (renamed from arch/mips/netlogic/xlr/xlr_console.c)13
-rw-r--r--arch/mips/netlogic/common/irq.c230
-rw-r--r--arch/mips/netlogic/common/smp.c (renamed from arch/mips/netlogic/xlr/smp.c)64
-rw-r--r--arch/mips/netlogic/common/time.c (renamed from arch/mips/netlogic/xlr/time.c)6
-rw-r--r--arch/mips/netlogic/xlr/Makefile5
-rw-r--r--arch/mips/netlogic/xlr/irq.c305
-rw-r--r--arch/mips/netlogic/xlr/platform.c31
-rw-r--r--arch/mips/netlogic/xlr/setup.c24
-rw-r--r--arch/mips/netlogic/xlr/smpboot.S6
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c71
13 files changed, 372 insertions, 390 deletions
diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile
new file mode 100644
index 000000000000..797326da3718
--- /dev/null
+++ b/arch/mips/netlogic/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_NLM_COMMON) += common/
2obj-$(CONFIG_CPU_XLR) += xlr/
diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index 18aaf438ee42..7811b107689d 100644
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -12,5 +12,5 @@ cflags-$(CONFIG_CPU_XLR) += $(call cc-option,-march=xlr,-march=mips64)
12# 12#
13# NETLOGIC processor support 13# NETLOGIC processor support
14# 14#
15platform-$(CONFIG_CPU_XLR) += netlogic/xlr 15platform-$(CONFIG_NLM_COMMON) += netlogic/
16load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000 16load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000
diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile
new file mode 100644
index 000000000000..d4215783c3e5
--- /dev/null
+++ b/arch/mips/netlogic/common/Makefile
@@ -0,0 +1,3 @@
1obj-y += irq.o time.o
2obj-$(CONFIG_SMP) += smp.o
3obj-$(CONFIG_EARLY_PRINTK) += earlycons.o
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/common/earlycons.c
index 759df0692201..28c8fa7a8503 100644
--- a/arch/mips/netlogic/xlr/xlr_console.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -33,14 +33,19 @@
33 */ 33 */
34 34
35#include <linux/types.h> 35#include <linux/types.h>
36#include <linux/serial_reg.h>
37
38#include <asm/mipsregs.h>
39#include <asm/netlogic/haldefs.h>
40
36#include <asm/netlogic/xlr/iomap.h> 41#include <asm/netlogic/xlr/iomap.h>
37 42
38void prom_putchar(char c) 43void prom_putchar(char c)
39{ 44{
40 nlm_reg_t *mmio; 45 uint64_t uartbase;
41 46
42 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 47 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
43 while (netlogic_read_reg(mmio, 0x5) == 0) 48 while (nlm_read_reg(uartbase, UART_LSR) == 0)
44 ; 49 ;
45 netlogic_write_reg(mmio, 0x0, c); 50 nlm_write_reg(uartbase, UART_TX, c);
46} 51}
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
new file mode 100644
index 000000000000..dd0dd626cc8f
--- /dev/null
+++ b/arch/mips/netlogic/common/irq.c
@@ -0,0 +1,230 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41#include <linux/slab.h>
42#include <linux/irq.h>
43
44#include <asm/errno.h>
45#include <asm/signal.h>
46#include <asm/system.h>
47#include <asm/ptrace.h>
48#include <asm/mipsregs.h>
49#include <asm/thread_info.h>
50
51#include <asm/netlogic/mips-extns.h>
52#include <asm/netlogic/interrupt.h>
53#include <asm/netlogic/haldefs.h>
54#include <asm/netlogic/common.h>
55
56#include <asm/netlogic/xlr/iomap.h>
57#include <asm/netlogic/xlr/pic.h>
58/*
59 * These are the routines that handle all the low level interrupt stuff.
60 * Actions handled here are: initialization of the interrupt map, requesting of
61 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
62 * for interrupt lines
63 */
64
65/* Globals */
66static uint64_t nlm_irq_mask;
67static DEFINE_SPINLOCK(nlm_pic_lock);
68
69static void xlp_pic_enable(struct irq_data *d)
70{
71 unsigned long flags;
72 int irt;
73
74 irt = nlm_irq_to_irt(d->irq);
75 if (irt == -1)
76 return;
77 spin_lock_irqsave(&nlm_pic_lock, flags);
78 nlm_pic_enable_irt(nlm_pic_base, irt);
79 spin_unlock_irqrestore(&nlm_pic_lock, flags);
80}
81
82static void xlp_pic_disable(struct irq_data *d)
83{
84 unsigned long flags;
85 int irt;
86
87 irt = nlm_irq_to_irt(d->irq);
88 if (irt == -1)
89 return;
90 spin_lock_irqsave(&nlm_pic_lock, flags);
91 nlm_pic_disable_irt(nlm_pic_base, irt);
92 spin_unlock_irqrestore(&nlm_pic_lock, flags);
93}
94
95static void xlp_pic_mask_ack(struct irq_data *d)
96{
97 uint64_t mask = 1ull << d->irq;
98
99 write_c0_eirr(mask); /* ack by writing EIRR */
100}
101
102static void xlp_pic_unmask(struct irq_data *d)
103{
104 void *hd = irq_data_get_irq_handler_data(d);
105 int irt;
106
107 irt = nlm_irq_to_irt(d->irq);
108 if (irt == -1)
109 return;
110
111 if (hd) {
112 void (*extra_ack)(void *) = hd;
113 extra_ack(d);
114 }
115 /* Ack is a single write, no need to lock */
116 nlm_pic_ack(nlm_pic_base, irt);
117}
118
119static struct irq_chip xlp_pic = {
120 .name = "XLP-PIC",
121 .irq_enable = xlp_pic_enable,
122 .irq_disable = xlp_pic_disable,
123 .irq_mask_ack = xlp_pic_mask_ack,
124 .irq_unmask = xlp_pic_unmask,
125};
126
127static void cpuintr_disable(struct irq_data *d)
128{
129 uint64_t eimr;
130 uint64_t mask = 1ull << d->irq;
131
132 eimr = read_c0_eimr();
133 write_c0_eimr(eimr & ~mask);
134}
135
136static void cpuintr_enable(struct irq_data *d)
137{
138 uint64_t eimr;
139 uint64_t mask = 1ull << d->irq;
140
141 eimr = read_c0_eimr();
142 write_c0_eimr(eimr | mask);
143}
144
145static void cpuintr_ack(struct irq_data *d)
146{
147 uint64_t mask = 1ull << d->irq;
148
149 write_c0_eirr(mask);
150}
151
152static void cpuintr_nop(struct irq_data *d)
153{
154 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
155}
156
157/*
158 * Chip definition for CPU originated interrupts(timer, msg) and
159 * IPIs
160 */
161struct irq_chip nlm_cpu_intr = {
162 .name = "XLP-CPU-INTR",
163 .irq_enable = cpuintr_enable,
164 .irq_disable = cpuintr_disable,
165 .irq_mask = cpuintr_nop,
166 .irq_ack = cpuintr_nop,
167 .irq_eoi = cpuintr_ack,
168};
169
170void __init init_nlm_common_irqs(void)
171{
172 int i, irq, irt;
173
174 for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
175 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
176
177 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
178 irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
179
180#ifdef CONFIG_SMP
181 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
182 nlm_smp_function_ipi_handler);
183 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
184 nlm_smp_resched_ipi_handler);
185 nlm_irq_mask |=
186 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
187#endif
188
189 for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
190 irt = nlm_irq_to_irt(irq);
191 if (irt == -1)
192 continue;
193 nlm_irq_mask |= (1ULL << irq);
194 nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
195 }
196
197 nlm_irq_mask |= (1ULL << IRQ_TIMER);
198}
199
200void __init arch_init_irq(void)
201{
202 /* Initialize the irq descriptors */
203 init_nlm_common_irqs();
204
205 write_c0_eimr(nlm_irq_mask);
206}
207
208void __cpuinit nlm_smp_irq_init(void)
209{
210 /* set interrupt mask for non-zero cpus */
211 write_c0_eimr(nlm_irq_mask);
212}
213
214asmlinkage void plat_irq_dispatch(void)
215{
216 uint64_t eirr;
217 int i;
218
219 eirr = read_c0_eirr() & read_c0_eimr();
220 if (eirr & (1 << IRQ_TIMER)) {
221 do_IRQ(IRQ_TIMER);
222 return;
223 }
224
225 i = __ilog2_u64(eirr);
226 if (i == -1)
227 return;
228
229 do_IRQ(i);
230}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/common/smp.c
index 080284ded508..3b32c834d14c 100644
--- a/arch/mips/netlogic/xlr/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -42,31 +42,20 @@
42 42
43#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h> 44#include <asm/netlogic/mips-extns.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
45 47
46#include <asm/netlogic/xlr/iomap.h> 48#include <asm/netlogic/xlr/iomap.h>
47#include <asm/netlogic/xlr/pic.h> 49#include <asm/netlogic/xlr/pic.h>
48#include <asm/netlogic/xlr/xlr.h>
49 50
50void core_send_ipi(int logical_cpu, unsigned int action) 51void nlm_send_ipi_single(int logical_cpu, unsigned int action)
51{ 52{
52 int cpu = cpu_logical_map(logical_cpu); 53 int cpu = cpu_logical_map(logical_cpu);
53 u32 tid = cpu & 0x3;
54 u32 pid = (cpu >> 2) & 0x07;
55 u32 ipi = (tid << 16) | (pid << 20);
56 54
57 if (action & SMP_CALL_FUNCTION) 55 if (action & SMP_CALL_FUNCTION)
58 ipi |= IRQ_IPI_SMP_FUNCTION; 56 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
59 else if (action & SMP_RESCHEDULE_YOURSELF) 57 if (action & SMP_RESCHEDULE_YOURSELF)
60 ipi |= IRQ_IPI_SMP_RESCHEDULE; 58 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
61 else
62 return;
63
64 pic_send_ipi(ipi);
65}
66
67void nlm_send_ipi_single(int cpu, unsigned int action)
68{
69 core_send_ipi(cpu, action);
70} 59}
71 60
72void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) 61void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -74,7 +63,7 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
74 int cpu; 63 int cpu;
75 64
76 for_each_cpu(cpu, mask) { 65 for_each_cpu(cpu, mask) {
77 core_send_ipi(cpu, action); 66 nlm_send_ipi_single(cpu, action);
78 } 67 }
79} 68}
80 69
@@ -82,21 +71,26 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
82void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) 71void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
83{ 72{
84 smp_call_function_interrupt(); 73 smp_call_function_interrupt();
74 write_c0_eirr(1ull << irq);
85} 75}
86 76
87/* IRQ_IPI_SMP_RESCHEDULE handler */ 77/* IRQ_IPI_SMP_RESCHEDULE handler */
88void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) 78void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
89{ 79{
90 scheduler_ipi(); 80 scheduler_ipi();
81 write_c0_eirr(1ull << irq);
91} 82}
92 83
93/* 84/*
94 * Called before going into mips code, early cpu init 85 * Called before going into mips code, early cpu init
95 */ 86 */
96void nlm_early_init_secondary(void) 87void nlm_early_init_secondary(int cpu)
97{ 88{
98 write_c0_ebase((uint32_t)nlm_common_ebase); 89 write_c0_ebase((uint32_t)nlm_common_ebase);
99 /* TLB partition here later */ 90#ifdef NLM_XLP
91 if (cpu % 4 == 0)
92 xlp_mmu_init();
93#endif
100} 94}
101 95
102/* 96/*
@@ -159,8 +153,8 @@ void __init nlm_smp_setup(void)
159 num_cpus = 1; 153 num_cpus = 1;
160 for (i = 0; i < NR_CPUS; i++) { 154 for (i = 0; i < NR_CPUS; i++) {
161 /* 155 /*
162 * BSP is not set in nlm_cpu_ready array, it is only for 156 * nlm_cpu_ready array is not set for the boot_cpu,
163 * ASPs (goto see smpboot.S) 157 * it is only set for ASPs (see smpboot.S)
164 */ 158 */
165 if (nlm_cpu_ready[i]) { 159 if (nlm_cpu_ready[i]) {
166 cpu_set(i, phys_cpu_present_map); 160 cpu_set(i, phys_cpu_present_map);
@@ -192,29 +186,3 @@ struct plat_smp_ops nlm_smp_ops = {
192 .smp_setup = nlm_smp_setup, 186 .smp_setup = nlm_smp_setup,
193 .prepare_cpus = nlm_prepare_cpus, 187 .prepare_cpus = nlm_prepare_cpus,
194}; 188};
195
196unsigned long secondary_entry_point;
197
198int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
199{
200 unsigned int tid, pid, ipi, i, boot_cpu;
201 void *reset_vec;
202
203 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
204 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
205 memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
206 boot_cpu = hard_smp_processor_id();
207
208 for (i = 0; i < NR_CPUS; i++) {
209 if (i == boot_cpu)
210 continue;
211 if (wakeup_mask & (1u << i)) {
212 tid = i & 0x3;
213 pid = (i >> 2) & 0x7;
214 ipi = (tid << 16) | (pid << 20) | (1 << 8);
215 pic_send_ipi(ipi);
216 }
217 }
218
219 return 0;
220}
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/common/time.c
index 0d81b262593c..bd3e498157ff 100644
--- a/arch/mips/netlogic/xlr/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -36,7 +36,7 @@
36 36
37#include <asm/time.h> 37#include <asm/time.h>
38#include <asm/netlogic/interrupt.h> 38#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/psb-bootinfo.h> 39#include <asm/netlogic/common.h>
40 40
41unsigned int __cpuinit get_c0_compare_int(void) 41unsigned int __cpuinit get_c0_compare_int(void)
42{ 42{
@@ -45,7 +45,7 @@ unsigned int __cpuinit get_c0_compare_int(void)
45 45
46void __init plat_time_init(void) 46void __init plat_time_init(void)
47{ 47{
48 mips_hpt_frequency = nlm_prom_info.cpu_frequency; 48 mips_hpt_frequency = nlm_get_cpu_frequency();
49 pr_info("MIPS counter frequency [%ld]\n", 49 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency); 50 (unsigned long)mips_hpt_frequency);
51} 51}
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 29f1fd5ba806..df245c604547 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,3 +1,2 @@
1obj-y += setup.o platform.o irq.o setup.o time.o 1obj-y += setup.o platform.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o 2obj-$(CONFIG_SMP) += smpboot.o wakeup.o
3obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index fc822c8f0817..000000000000
--- a/arch/mips/netlogic/xlr/irq.c
+++ /dev/null
@@ -1,305 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41#include <linux/msi.h>
42#include <linux/irq.h>
43#include <linux/irqdesc.h>
44#include <linux/pci.h>
45
46#include <asm/mipsregs.h>
47
48#include <asm/netlogic/xlr/msidef.h>
49#include <asm/netlogic/xlr/iomap.h>
50#include <asm/netlogic/xlr/pic.h>
51#include <asm/netlogic/xlr/xlr.h>
52
53#include <asm/netlogic/interrupt.h>
54#include <asm/netlogic/mips-extns.h>
55
56static u64 nlm_irq_mask;
57static DEFINE_SPINLOCK(nlm_pic_lock);
58
59static void xlr_pic_enable(struct irq_data *d)
60{
61 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
62 unsigned long flags;
63 nlm_reg_t reg;
64 int irq = d->irq;
65
66 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
67
68 spin_lock_irqsave(&nlm_pic_lock, flags);
69 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
70 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
71 reg | (1 << 6) | (1 << 30) | (1 << 31));
72 spin_unlock_irqrestore(&nlm_pic_lock, flags);
73}
74
75static void xlr_pic_mask(struct irq_data *d)
76{
77 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
78 unsigned long flags;
79 nlm_reg_t reg;
80 int irq = d->irq;
81
82 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
83
84 spin_lock_irqsave(&nlm_pic_lock, flags);
85 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
86 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
87 reg | (1 << 6) | (1 << 30) | (0 << 31));
88 spin_unlock_irqrestore(&nlm_pic_lock, flags);
89}
90
91#ifdef CONFIG_PCI
92/* Extra ACK needed for XLR on chip PCI controller */
93static void xlr_pci_ack(struct irq_data *d)
94{
95 nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
96
97 netlogic_read_reg(pci_mmio, (0x140 >> 2));
98}
99
100/* Extra ACK needed for XLS on chip PCIe controller */
101static void xls_pcie_ack(struct irq_data *d)
102{
103 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
104
105 switch (d->irq) {
106 case PIC_PCIE_LINK0_IRQ:
107 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
108 break;
109 case PIC_PCIE_LINK1_IRQ:
110 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
111 break;
112 case PIC_PCIE_LINK2_IRQ:
113 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
114 break;
115 case PIC_PCIE_LINK3_IRQ:
116 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
117 break;
118 }
119}
120
121/* For XLS B silicon, the 3,4 PCI interrupts are different */
122static void xls_pcie_ack_b(struct irq_data *d)
123{
124 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
125
126 switch (d->irq) {
127 case PIC_PCIE_LINK0_IRQ:
128 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
129 break;
130 case PIC_PCIE_LINK1_IRQ:
131 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
132 break;
133 case PIC_PCIE_XLSB0_LINK2_IRQ:
134 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
135 break;
136 case PIC_PCIE_XLSB0_LINK3_IRQ:
137 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
138 break;
139 }
140}
141#endif
142
143static void xlr_pic_ack(struct irq_data *d)
144{
145 unsigned long flags;
146 nlm_reg_t *mmio;
147 int irq = d->irq;
148 void *hd = irq_data_get_irq_handler_data(d);
149
150 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
151
152 if (hd) {
153 void (*extra_ack)(void *) = hd;
154 extra_ack(d);
155 }
156 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
157 spin_lock_irqsave(&nlm_pic_lock, flags);
158 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
159 spin_unlock_irqrestore(&nlm_pic_lock, flags);
160}
161
162/*
163 * This chip definition handles interrupts routed thru the XLR
164 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
165 * 0-31 wired the XLR PIC
166 */
167static struct irq_chip xlr_pic = {
168 .name = "XLR-PIC",
169 .irq_enable = xlr_pic_enable,
170 .irq_mask = xlr_pic_mask,
171 .irq_ack = xlr_pic_ack,
172};
173
174static void rsvd_irq_handler(struct irq_data *d)
175{
176 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
177}
178
179/*
180 * Chip definition for CPU originated interrupts(timer, msg) and
181 * IPIs
182 */
183struct irq_chip nlm_cpu_intr = {
184 .name = "XLR-CPU-INTR",
185 .irq_enable = rsvd_irq_handler,
186 .irq_mask = rsvd_irq_handler,
187 .irq_ack = rsvd_irq_handler,
188};
189
190void __init init_xlr_irqs(void)
191{
192 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
193 uint32_t thread_mask = 1;
194 int level, i;
195
196 pr_info("Interrupt thread mask [%x]\n", thread_mask);
197 for (i = 0; i < PIC_NUM_IRTS; i++) {
198 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
199
200 /* Bind all PIC irqs to boot cpu */
201 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
202
203 /*
204 * Use local scheduling and high polarity for all IRTs
205 * Invalidate all IRTs, by default
206 */
207 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
208 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
209 }
210
211 /* Make all IRQs as level triggered by default */
212 for (i = 0; i < NR_IRQS; i++) {
213 if (PIC_IRQ_IS_IRT(i))
214 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
215 else
216 irq_set_chip_and_handler(i, &nlm_cpu_intr,
217 handle_percpu_irq);
218 }
219#ifdef CONFIG_SMP
220 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
221 nlm_smp_function_ipi_handler);
222 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
223 nlm_smp_resched_ipi_handler);
224 nlm_irq_mask |=
225 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
226#endif
227
228#ifdef CONFIG_PCI
229 /*
230 * For PCI interrupts, we need to ack the PIC controller too, overload
231 * irq handler data to do this
232 */
233 if (nlm_chip_is_xls()) {
234 if (nlm_chip_is_xls_b()) {
235 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
236 xls_pcie_ack_b);
237 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
238 xls_pcie_ack_b);
239 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
240 xls_pcie_ack_b);
241 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
242 xls_pcie_ack_b);
243 } else {
244 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
245 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
246 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
247 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
248 }
249 } else {
250 /* XLR PCI controller ACK */
251 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
252 }
253#endif
254 /* unmask all PIC related interrupts. If no handler is installed by the
255 * drivers, it'll just ack the interrupt and return
256 */
257 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
258 nlm_irq_mask |= (1ULL << i);
259
260 nlm_irq_mask |= (1ULL << IRQ_TIMER);
261}
262
263void __init arch_init_irq(void)
264{
265 /* Initialize the irq descriptors */
266 init_xlr_irqs();
267 write_c0_eimr(nlm_irq_mask);
268}
269
270void __cpuinit nlm_smp_irq_init(void)
271{
272 /* set interrupt mask for non-zero cpus */
273 write_c0_eimr(nlm_irq_mask);
274}
275
276asmlinkage void plat_irq_dispatch(void)
277{
278 uint64_t eirr;
279 int i;
280
281 eirr = read_c0_eirr() & read_c0_eimr();
282 if (!eirr)
283 return;
284
285 /* no need of EIRR here, writing compare clears interrupt */
286 if (eirr & (1 << IRQ_TIMER)) {
287 do_IRQ(IRQ_TIMER);
288 return;
289 }
290
291 /* use dcltz: optimize below code */
292 for (i = 63; i != -1; i--) {
293 if (eirr & (1ULL << i))
294 break;
295 }
296 if (i == -1) {
297 pr_err("no interrupt !!\n");
298 return;
299 }
300
301 /* Ack eirr */
302 write_c0_eirr(1ULL << i);
303
304 do_IRQ(i);
305}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 609ec2534642..eab64b45dffd 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -15,18 +15,19 @@
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17 17
18#include <asm/netlogic/haldefs.h>
18#include <asm/netlogic/xlr/iomap.h> 19#include <asm/netlogic/xlr/iomap.h>
19#include <asm/netlogic/xlr/pic.h> 20#include <asm/netlogic/xlr/pic.h>
20#include <asm/netlogic/xlr/xlr.h> 21#include <asm/netlogic/xlr/xlr.h>
21 22
22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 23unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
23{ 24{
24 nlm_reg_t *mmio; 25 uint64_t uartbase;
25 unsigned int value; 26 unsigned int value;
26 27
27 /* XLR uart does not need any mapping of regs */ 28 /* sign extend to 64 bits, if needed */
28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 29 uartbase = (uint64_t)(long)p->membase;
29 value = netlogic_read_reg(mmio, 0); 30 value = nlm_read_reg(uartbase, offset);
30 31
31 /* See XLR/XLS errata */ 32 /* See XLR/XLS errata */
32 if (offset == UART_MSR) 33 if (offset == UART_MSR)
@@ -39,10 +40,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
39 40
40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 41void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
41{ 42{
42 nlm_reg_t *mmio; 43 uint64_t uartbase;
43 44
44 /* XLR uart does not need any mapping of regs */ 45 /* sign extend to 64 bits, if needed */
45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 46 uartbase = (uint64_t)(long)p->membase;
46 47
47 /* See XLR/XLS errata */ 48 /* See XLR/XLS errata */
48 if (offset == UART_MSR) 49 if (offset == UART_MSR)
@@ -50,7 +51,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
50 else if (offset == UART_MCR) 51 else if (offset == UART_MCR)
51 value ^= 0x3; 52 value ^= 0x3;
52 53
53 netlogic_write_reg(mmio, 0, value); 54 nlm_write_reg(uartbase, offset, value);
54} 55}
55 56
56#define PORT(_irq) \ 57#define PORT(_irq) \
@@ -82,15 +83,15 @@ static struct platform_device uart_device = {
82 83
83static int __init nlm_uart_init(void) 84static int __init nlm_uart_init(void)
84{ 85{
85 nlm_reg_t *mmio; 86 unsigned long uartbase;
86 87
87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 88 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
88 xlr_uart_data[0].membase = (void __iomem *)mmio; 89 xlr_uart_data[0].membase = (void __iomem *)uartbase;
89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio); 90 xlr_uart_data[0].mapbase = CPHYSADDR(uartbase);
90 91
91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); 92 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET);
92 xlr_uart_data[1].membase = (void __iomem *)mmio; 93 xlr_uart_data[1].membase = (void __iomem *)uartbase;
93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio); 94 xlr_uart_data[1].mapbase = CPHYSADDR(uartbase);
94 95
95 return platform_device_register(&uart_device); 96 return platform_device_register(&uart_device);
96} 97}
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index cee25ddd0887..20c280ae7e99 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,26 +39,28 @@
39#include <asm/reboot.h> 39#include <asm/reboot.h>
40#include <asm/time.h> 40#include <asm/time.h>
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
43 42
44#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/psb-bootinfo.h> 44#include <asm/netlogic/psb-bootinfo.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
46 47
47#include <asm/netlogic/xlr/xlr.h> 48#include <asm/netlogic/xlr/xlr.h>
48#include <asm/netlogic/xlr/iomap.h> 49#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h> 50#include <asm/netlogic/xlr/pic.h>
50#include <asm/netlogic/xlr/gpio.h> 51#include <asm/netlogic/xlr/gpio.h>
51 52
52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); 53uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
54uint64_t nlm_pic_base;
53unsigned long nlm_common_ebase = 0x0; 55unsigned long nlm_common_ebase = 0x0;
54struct psb_info nlm_prom_info; 56struct psb_info nlm_prom_info;
55 57
56static void __init nlm_early_serial_setup(void) 58static void __init nlm_early_serial_setup(void)
57{ 59{
58 struct uart_port s; 60 struct uart_port s;
59 nlm_reg_t *uart_base; 61 unsigned long uart_base;
60 62
61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 63 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
62 memset(&s, 0, sizeof(s)); 64 memset(&s, 0, sizeof(s));
63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; 65 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
64 s.iotype = UPIO_MEM32; 66 s.iotype = UPIO_MEM32;
@@ -67,18 +69,18 @@ static void __init nlm_early_serial_setup(void)
67 s.uartclk = PIC_CLKS_PER_SEC; 69 s.uartclk = PIC_CLKS_PER_SEC;
68 s.serial_in = nlm_xlr_uart_in; 70 s.serial_in = nlm_xlr_uart_in;
69 s.serial_out = nlm_xlr_uart_out; 71 s.serial_out = nlm_xlr_uart_out;
70 s.mapbase = (unsigned long)uart_base; 72 s.mapbase = uart_base;
71 s.membase = (unsigned char __iomem *)uart_base; 73 s.membase = (unsigned char __iomem *)uart_base;
72 early_serial_setup(&s); 74 early_serial_setup(&s);
73} 75}
74 76
75static void nlm_linux_exit(void) 77static void nlm_linux_exit(void)
76{ 78{
77 nlm_reg_t *mmio; 79 uint64_t gpiobase;
78 80
79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); 81 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 82 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); 83 nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
82 for ( ; ; ) 84 for ( ; ; )
83 cpu_wait(); 85 cpu_wait();
84} 86}
@@ -96,6 +98,11 @@ const char *get_system_type(void)
96 return "Netlogic XLR/XLS Series"; 98 return "Netlogic XLR/XLS Series";
97} 99}
98 100
101unsigned int nlm_get_cpu_frequency(void)
102{
103 return (unsigned int)nlm_prom_info.cpu_frequency;
104}
105
99void __init prom_free_prom_memory(void) 106void __init prom_free_prom_memory(void)
100{ 107{
101 /* Nothing yet */ 108 /* Nothing yet */
@@ -175,6 +182,7 @@ void __init prom_init(void)
175 prom_infop = (struct psb_info *)(long)(int)fw_arg3; 182 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
176 183
177 nlm_prom_info = *prom_infop; 184 nlm_prom_info = *prom_infop;
185 nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
178 186
179 nlm_early_serial_setup(); 187 nlm_early_serial_setup();
180 build_arcs_cmdline(argv); 188 build_arcs_cmdline(argv);
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S
index 8cb7889ce0cc..7f1f6e6e295f 100644
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ b/arch/mips/netlogic/xlr/smpboot.S
@@ -75,12 +75,11 @@ NESTED(prom_pre_boot_secondary_cpus, 16, sp)
75 jr t0 75 jr t0
76 nop 76 nop
77END(prom_pre_boot_secondary_cpus) 77END(prom_pre_boot_secondary_cpus)
78 __FINIT
79 78
80/* 79/*
81 * NMI code, used for CPU wakeup, copied to reset entry 80 * NMI code, used for CPU wakeup, copied to reset entry
82 */ 81 */
83NESTED(nlm_boot_smp_nmi, 0, sp) 82EXPORT(nlm_reset_entry)
84 .set push 83 .set push
85 .set noat 84 .set noat
86 .set mips64 85 .set mips64
@@ -97,4 +96,5 @@ NESTED(nlm_boot_smp_nmi, 0, sp)
97 jr k0 96 jr k0
98 nop 97 nop
99 .set pop 98 .set pop
100END(nlm_boot_smp_nmi) 99EXPORT(nlm_reset_entry_end)
100 __FINIT
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
new file mode 100644
index 000000000000..69143bb7f688
--- /dev/null
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -0,0 +1,71 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36#include <linux/threads.h>
37
38#include <asm/asm.h>
39#include <asm/asm-offsets.h>
40#include <asm/mipsregs.h>
41#include <asm/addrspace.h>
42#include <asm/string.h>
43
44#include <asm/netlogic/haldefs.h>
45#include <asm/netlogic/common.h>
46#include <asm/netlogic/mips-extns.h>
47
48#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h>
50
51unsigned long secondary_entry_point;
52
53int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
54{
55 unsigned int i, boot_cpu;
56 void *reset_vec;
57
58 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
59 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
60 memcpy(reset_vec, (void *)nlm_reset_entry,
61 (nlm_reset_entry_end - nlm_reset_entry));
62 boot_cpu = hard_smp_processor_id();
63
64 for (i = 0; i < NR_CPUS; i++) {
65 if (i == boot_cpu || (wakeup_mask & (1u << i)) == 0)
66 continue;
67 nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
68 }
69
70 return 0;
71}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 15:20:57 -0400