MIPS: Fixup ordering of micro assembler instructions.

A number of new instructions have been added to the micro assembler causing
the list to no longer be in alphabetical order. This patch fixes up the name
ordering.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3789/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 30 insertions, 32 deletions

diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 5fa185151fc8..64a28e819064 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -58,18 +58,16 @@ enum fields {
 
 enum opcode {
         insn_invalid,
-        insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
-        insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
-        insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
-        insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
-        insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
-        insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
-        insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
-        insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
-        insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
+        insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
+        insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
+        insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
+        insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
+        insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
+        insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, insn_ll, insn_lld,
+        insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori,
+        insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,
+        insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp,
         insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
-        insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1,
-        insn_lwx, insn_ldx
 };
 
 struct insn {
@@ -90,65 +88,65 @@ struct insn {
 static struct insn insn_table[] __uasminitdata = {
         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
-        { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
         { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
-        { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
+        { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
-        { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
+        { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
-        { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
+        { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
         { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
+        { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
         { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
         { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
+        { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
+        { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
         { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
         { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
-        { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
+        { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
+        { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
-        { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
-        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
-        { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
-        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
+        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
-        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
         { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
         { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
         { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
         { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
-        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
         { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
         { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
-        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
         { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
-        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
         { insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
-        { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
-        { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
-        { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
-        { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
-        { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
-        { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
-        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
-        { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
+        { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
         { insn_invalid, 0, 0 }
 };