Merge tag 'v3.12-rc4' into sched/core

Merge Linux v3.12-rc4 to fix a conflict and also to refresh the tree
before applying more scheduler patches.

Conflicts:
	arch/avr32/include/asm/Kbuild

Signed-off-by: Ingo Molnar <mingo@kernel.org>

7 files changed, 48 insertions, 27 deletions

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 729e7702b1de..c8efdb5b6ee0 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -19,6 +19,7 @@
 #include <asm/bootinfo.h>
 #include <asm/cacheops.h>
 #include <asm/cpu-features.h>
+#include <asm/cpu-type.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/r4kcache.h>
@@ -186,9 +187,10 @@ static void probe_octeon(void)
         unsigned long dcache_size;
         unsigned int config1;
         struct cpuinfo_mips *c = &current_cpu_data;
+        int cputype = current_cpu_type();
 
         config1 = read_c0_config1();
-        switch (c->cputype) {
+        switch (cputype) {
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
                 c->icache.linesz = 2 << ((config1 >> 19) & 7);
@@ -199,7 +201,7 @@ static void probe_octeon(void)
                         c->icache.sets * c->icache.ways * c->icache.linesz;
                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
                 c->dcache.linesz = 128;
-                if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
+                if (cputype == CPU_CAVIUM_OCTEON_PLUS)
                         c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
                 else
                         c->dcache.sets = 1; /* CN3XXX has one Dcache set */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index f749f687ee87..bc6f96fcb529 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -12,6 +12,7 @@
 #include <linux/highmem.h>
 #include <linux/kernel.h>
 #include <linux/linkage.h>
+#include <linux/preempt.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/mm.h>
@@ -24,6 +25,7 @@
 #include <asm/cacheops.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
+#include <asm/cpu-type.h>
 #include <asm/io.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
@@ -601,11 +603,13 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
         /* Catch bad driver code */
         BUG_ON(size == 0);
 
+        preempt_disable();
         if (cpu_has_inclusive_pcaches) {
                 if (size >= scache_size)
                         r4k_blast_scache();
                 else
                         blast_scache_range(addr, addr + size);
+                preempt_enable();
                 __sync();
                 return;
         }
@@ -621,6 +625,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
                 R4600_HIT_CACHEOP_WAR_IMPL;
                 blast_dcache_range(addr, addr + size);
         }
+        preempt_enable();
 
         bc_wback_inv(addr, size);
         __sync();
@@ -631,6 +636,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
         /* Catch bad driver code */
         BUG_ON(size == 0);
 
+        preempt_disable();
         if (cpu_has_inclusive_pcaches) {
                 if (size >= scache_size)
                         r4k_blast_scache();
@@ -645,6 +651,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                          */
                         blast_inv_scache_range(addr, addr + size);
                 }
+                preempt_enable();
                 __sync();
                 return;
         }
@@ -655,6 +662,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                 R4600_HIT_CACHEOP_WAR_IMPL;
                 blast_inv_dcache_range(addr, addr + size);
         }
+        preempt_enable();
 
         bc_inv(addr, size);
         __sync();
@@ -780,20 +788,30 @@ static inline void rm7k_erratum31(void)
 
 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
 {
+        unsigned int imp = c->processor_id & PRID_IMP_MASK;
+        unsigned int rev = c->processor_id & PRID_REV_MASK;
+
         /*
          * Early versions of the 74K do not update the cache tags on a
          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
          * aliases. In this case it is better to treat the cache as always
          * having aliases.
          */
-        if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
-                c->dcache.flags |= MIPS_CACHE_VTAG;
-        if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
-                write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
-        if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
-            ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
-                c->dcache.flags |= MIPS_CACHE_VTAG;
-                write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+        switch (imp) {
+        case PRID_IMP_74K:
+                if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
+                        c->dcache.flags |= MIPS_CACHE_VTAG;
+                if (rev == PRID_REV_ENCODE_332(2, 4, 0))
+                        write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+                break;
+        case PRID_IMP_1074K:
+                if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
+                        c->dcache.flags |= MIPS_CACHE_VTAG;
+                        write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+                }
+                break;
+        default:
+                BUG();
         }
 }
 
@@ -809,7 +827,7 @@ static void probe_pcache(void)
         unsigned long config1;
         unsigned int lsize;
 
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
         case CPU_R4600:                 /* QED style two way caches? */
         case CPU_R4700:
         case CPU_R5000:
@@ -1025,7 +1043,8 @@ static void probe_pcache(void)
          * presumably no vendor is shipping his hardware in the "bad"
          * configuration.
          */
-        if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
+        if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
+            (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
             !(config & CONF_SC) && c->icache.linesz != 16 &&
             PAGE_SIZE <= 0x8000)
                 panic("Improper R4000SC processor configuration detected");
@@ -1045,7 +1064,7 @@ static void probe_pcache(void)
          * normally they'd suffer from aliases but magic in the hardware deals
          * with that for us so we don't need to take care ourselves.
          */
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
         case CPU_20KC:
         case CPU_25KF:
         case CPU_SB1:
@@ -1065,7 +1084,7 @@ static void probe_pcache(void)
         case CPU_34K:
         case CPU_74K:
         case CPU_1004K:
-                if (c->cputype == CPU_74K)
+                if (current_cpu_type() == CPU_74K)
                         alias_74k_erratum(c);
                 if ((read_c0_config7() & (1 << 16))) {
                         /* effectively physically indexed dcache,
@@ -1078,7 +1097,7 @@ static void probe_pcache(void)
                         c->dcache.flags |= MIPS_CACHE_ALIASES;
         }
 
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
         case CPU_20KC:
                 /*
                  * Some older 20Kc chips doesn't have the 'VI' bit in
@@ -1207,7 +1226,7 @@ static void setup_scache(void)
          * processors don't have a S-cache that would be relevant to the
          * Linux memory management.
          */
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
         case CPU_R4000SC:
         case CPU_R4000MC:
         case CPU_R4400SC:
@@ -1384,9 +1403,8 @@ static void r4k_cache_error_setup(void)
 {
         extern char __weak except_vec2_generic;
         extern char __weak except_vec2_sb1;
-        struct cpuinfo_mips *c = &current_cpu_data;
 
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
         case CPU_SB1:
         case CPU_SB1A:
                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 664e523653d0..5f8b95512580 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -18,6 +18,7 @@
 #include <linux/highmem.h>
 
 #include <asm/cache.h>
+#include <asm/cpu-type.h>
 #include <asm/io.h>
 
 #include <dma-coherence.h>
@@ -307,12 +308,10 @@ static void mips_dma_sync_sg_for_cpu(struct device *dev,
 {
         int i;
 
-        /* Make sure that gcc doesn't leave the empty loop body.  */
-        for (i = 0; i < nelems; i++, sg++) {
-                if (cpu_needs_post_dma_flush(dev))
+        if (cpu_needs_post_dma_flush(dev))
+                for (i = 0; i < nelems; i++, sg++)
                         __dma_sync(sg_page(sg), sg->offset, sg->length,
                                    direction);
-        }
 }
 
 static void mips_dma_sync_sg_for_device(struct device *dev,
@@ -320,12 +319,10 @@ static void mips_dma_sync_sg_for_device(struct device *dev,
 {
         int i;
 
-        /* Make sure that gcc doesn't leave the empty loop body.  */
-        for (i = 0; i < nelems; i++, sg++) {
-                if (!plat_device_is_coherent(dev))
+        if (!plat_device_is_coherent(dev))
+                for (i = 0; i < nelems; i++, sg++)
                         __dma_sync(sg_page(sg), sg->offset, sg->length,
                                    direction);
-        }
 }
 
 int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 218c2109a55d..cbd81d17793a 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -18,6 +18,7 @@
 
 #include <asm/bugs.h>
 #include <asm/cacheops.h>
+#include <asm/cpu-type.h>
 #include <asm/inst.h>
 #include <asm/io.h>
 #include <asm/page.h>
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5d01392e3518..08d05aee8788 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -6,6 +6,7 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 
+#include <asm/cpu-type.h>
 #include <asm/mipsregs.h>
 #include <asm/bcache.h>
 #include <asm/cacheops.h>
@@ -71,7 +72,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
         unsigned int tmp;
 
         /* Check the bypass bit (L2B) */
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
         case CPU_34K:
         case CPU_74K:
         case CPU_1004K:
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 00b26a67a06d..bb3a5f643e97 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 
 #include <asm/cpu.h>
+#include <asm/cpu-type.h>
 #include <asm/bootinfo.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 821b45175dc1..9bb3a9363b06 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -30,6 +30,7 @@
 #include <linux/cache.h>
 
 #include <asm/cacheflush.h>
+#include <asm/cpu-type.h>
 #include <asm/pgtable.h>
 #include <asm/war.h>
 #include <asm/uasm.h>