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authorRalf Baechle <ralf@linux-mips.org>2005-07-15 11:23:23 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:54 -0400
commit1d40cfcd3442a53e98468cdb3e6d4d9a568d76cf (patch)
tree76d3ba7ac251389194b74c4343d7c46231442044 /arch/mips/mm
parentbdf21b18b4abf983db38f04ef7fec88f47389867 (diff)
Avoid SMP cacheflushes. This is a minor optimization of startup but
will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/c-r4k.c5
-rw-r--r--arch/mips/mm/c-tx39.c1
-rw-r--r--arch/mips/mm/pg-r4k.c6
-rw-r--r--arch/mips/mm/tlbex.c30
4 files changed, 13 insertions, 29 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6a1267ad071f..637052b23042 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1270,9 +1270,8 @@ void __init ld_mmu_r4xx0(void)
1270 _dma_cache_inv = r4k_dma_cache_inv; 1270 _dma_cache_inv = r4k_dma_cache_inv;
1271#endif 1271#endif
1272 1272
1273 __flush_cache_all();
1274 coherency_setup();
1275
1276 build_clear_page(); 1273 build_clear_page();
1277 build_copy_page(); 1274 build_copy_page();
1275 local_r4k___flush_cache_all(NULL);
1276 coherency_setup();
1278} 1277}
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 5054a0ed2b6d..56c3fcdd2822 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -492,4 +492,5 @@ void __init ld_mmu_tx39(void)
492 492
493 build_clear_page(); 493 build_clear_page();
494 build_copy_page(); 494 build_copy_page();
495 tx39h_flush_icache_all();
495} 496}
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index 9f8b16541577..75d9ebfc5431 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -404,9 +404,6 @@ dest = label();
404 404
405 build_jr_ra(); 405 build_jr_ra();
406 406
407 flush_icache_range((unsigned long)&clear_page_array,
408 (unsigned long) epc);
409
410 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); 407 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
411} 408}
412 409
@@ -482,8 +479,5 @@ dest = label();
482 479
483 build_jr_ra(); 480 build_jr_ra();
484 481
485 flush_icache_range((unsigned long)&copy_page_array,
486 (unsigned long) epc);
487
488 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); 482 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
489} 483}
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a876ed6cde24..c3c75a234f50 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -743,7 +743,6 @@ static void __init build_r3000_tlb_refill_handler(void)
743#endif 743#endif
744 744
745 memcpy((void *)CAC_BASE, tlb_handler, 0x80); 745 memcpy((void *)CAC_BASE, tlb_handler, 0x80);
746 flush_icache_range(CAC_BASE, CAC_BASE + 0x80);
747} 746}
748 747
749/* 748/*
@@ -1258,7 +1257,6 @@ static void __init build_r4000_tlb_refill_handler(void)
1258#endif 1257#endif
1259 1258
1260 memcpy((void *)CAC_BASE, final_handler, 0x100); 1259 memcpy((void *)CAC_BASE, final_handler, 0x100);
1261 flush_icache_range(CAC_BASE, CAC_BASE + 0x100);
1262} 1260}
1263 1261
1264/* 1262/*
@@ -1519,9 +1517,6 @@ static void __init build_r3000_tlb_load_handler(void)
1519 printk("%08x\n", handle_tlbl[i]); 1517 printk("%08x\n", handle_tlbl[i]);
1520 } 1518 }
1521#endif 1519#endif
1522
1523 flush_icache_range((unsigned long)handle_tlbl,
1524 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1525} 1520}
1526 1521
1527static void __init build_r3000_tlb_store_handler(void) 1522static void __init build_r3000_tlb_store_handler(void)
@@ -1559,9 +1554,6 @@ static void __init build_r3000_tlb_store_handler(void)
1559 printk("%08x\n", handle_tlbs[i]); 1554 printk("%08x\n", handle_tlbs[i]);
1560 } 1555 }
1561#endif 1556#endif
1562
1563 flush_icache_range((unsigned long)handle_tlbs,
1564 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1565} 1557}
1566 1558
1567static void __init build_r3000_tlb_modify_handler(void) 1559static void __init build_r3000_tlb_modify_handler(void)
@@ -1599,9 +1591,6 @@ static void __init build_r3000_tlb_modify_handler(void)
1599 printk("%08x\n", handle_tlbm[i]); 1591 printk("%08x\n", handle_tlbm[i]);
1600 } 1592 }
1601#endif 1593#endif
1602
1603 flush_icache_range((unsigned long)handle_tlbm,
1604 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1605} 1594}
1606 1595
1607/* 1596/*
@@ -1691,9 +1680,6 @@ static void __init build_r4000_tlb_load_handler(void)
1691 printk("%08x\n", handle_tlbl[i]); 1680 printk("%08x\n", handle_tlbl[i]);
1692 } 1681 }
1693#endif 1682#endif
1694
1695 flush_icache_range((unsigned long)handle_tlbl,
1696 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1697} 1683}
1698 1684
1699static void __init build_r4000_tlb_store_handler(void) 1685static void __init build_r4000_tlb_store_handler(void)
@@ -1730,9 +1716,6 @@ static void __init build_r4000_tlb_store_handler(void)
1730 printk("%08x\n", handle_tlbs[i]); 1716 printk("%08x\n", handle_tlbs[i]);
1731 } 1717 }
1732#endif 1718#endif
1733
1734 flush_icache_range((unsigned long)handle_tlbs,
1735 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1736} 1719}
1737 1720
1738static void __init build_r4000_tlb_modify_handler(void) 1721static void __init build_r4000_tlb_modify_handler(void)
@@ -1770,9 +1753,6 @@ static void __init build_r4000_tlb_modify_handler(void)
1770 printk("%08x\n", handle_tlbm[i]); 1753 printk("%08x\n", handle_tlbm[i]);
1771 } 1754 }
1772#endif 1755#endif
1773
1774 flush_icache_range((unsigned long)handle_tlbm,
1775 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1776} 1756}
1777 1757
1778void __init build_tlb_refill_handler(void) 1758void __init build_tlb_refill_handler(void)
@@ -1820,3 +1800,13 @@ void __init build_tlb_refill_handler(void)
1820 } 1800 }
1821 } 1801 }
1822} 1802}
1803
1804void __init flush_tlb_handlers(void)
1805{
1806 flush_icache_range((unsigned long)handle_tlbl,
1807 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1808 flush_icache_range((unsigned long)handle_tlbs,
1809 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1810 flush_icache_range((unsigned long)handle_tlbm,
1811 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
1812}