diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2006-03-20 12:58:02 -0500 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2006-03-20 12:58:02 -0500 |
commit | 1a02e59a2970f9ed28ab51d3b08624b79e54d848 (patch) | |
tree | 470cce472be3b08c160e0c569648e7228651b12a /arch/mips/mm/c-r4k.c | |
parent | ebcff3c773b42bce6182ec16485abca4e53fba97 (diff) | |
parent | 2c276603c3e5ebf38155a9d1fbbda656d52d138e (diff) |
Merge branch 'master'
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r-- | arch/mips/mm/c-r4k.c | 120 |
1 files changed, 25 insertions, 95 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index e51c38cef88e..0668e9bfce41 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -235,7 +235,9 @@ static inline void r4k_blast_scache_page_setup(void) | |||
235 | { | 235 | { |
236 | unsigned long sc_lsize = cpu_scache_line_size(); | 236 | unsigned long sc_lsize = cpu_scache_line_size(); |
237 | 237 | ||
238 | if (sc_lsize == 16) | 238 | if (scache_size == 0) |
239 | r4k_blast_scache_page = (void *)no_sc_noop; | ||
240 | else if (sc_lsize == 16) | ||
239 | r4k_blast_scache_page = blast_scache16_page; | 241 | r4k_blast_scache_page = blast_scache16_page; |
240 | else if (sc_lsize == 32) | 242 | else if (sc_lsize == 32) |
241 | r4k_blast_scache_page = blast_scache32_page; | 243 | r4k_blast_scache_page = blast_scache32_page; |
@@ -251,7 +253,9 @@ static inline void r4k_blast_scache_page_indexed_setup(void) | |||
251 | { | 253 | { |
252 | unsigned long sc_lsize = cpu_scache_line_size(); | 254 | unsigned long sc_lsize = cpu_scache_line_size(); |
253 | 255 | ||
254 | if (sc_lsize == 16) | 256 | if (scache_size == 0) |
257 | r4k_blast_scache_page_indexed = (void *)no_sc_noop; | ||
258 | else if (sc_lsize == 16) | ||
255 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; | 259 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
256 | else if (sc_lsize == 32) | 260 | else if (sc_lsize == 32) |
257 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | 261 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; |
@@ -267,7 +271,9 @@ static inline void r4k_blast_scache_setup(void) | |||
267 | { | 271 | { |
268 | unsigned long sc_lsize = cpu_scache_line_size(); | 272 | unsigned long sc_lsize = cpu_scache_line_size(); |
269 | 273 | ||
270 | if (sc_lsize == 16) | 274 | if (scache_size == 0) |
275 | r4k_blast_scache = (void *)no_sc_noop; | ||
276 | else if (sc_lsize == 16) | ||
271 | r4k_blast_scache = blast_scache16; | 277 | r4k_blast_scache = blast_scache16; |
272 | else if (sc_lsize == 32) | 278 | else if (sc_lsize == 32) |
273 | r4k_blast_scache = blast_scache32; | 279 | r4k_blast_scache = blast_scache32; |
@@ -471,61 +477,29 @@ struct flush_icache_range_args { | |||
471 | static inline void local_r4k_flush_icache_range(void *args) | 477 | static inline void local_r4k_flush_icache_range(void *args) |
472 | { | 478 | { |
473 | struct flush_icache_range_args *fir_args = args; | 479 | struct flush_icache_range_args *fir_args = args; |
474 | unsigned long dc_lsize = cpu_dcache_line_size(); | ||
475 | unsigned long ic_lsize = cpu_icache_line_size(); | ||
476 | unsigned long sc_lsize = cpu_scache_line_size(); | ||
477 | unsigned long start = fir_args->start; | 480 | unsigned long start = fir_args->start; |
478 | unsigned long end = fir_args->end; | 481 | unsigned long end = fir_args->end; |
479 | unsigned long addr, aend; | ||
480 | 482 | ||
481 | if (!cpu_has_ic_fills_f_dc) { | 483 | if (!cpu_has_ic_fills_f_dc) { |
482 | if (end - start > dcache_size) { | 484 | if (end - start > dcache_size) { |
483 | r4k_blast_dcache(); | 485 | r4k_blast_dcache(); |
484 | } else { | 486 | } else { |
485 | R4600_HIT_CACHEOP_WAR_IMPL; | 487 | R4600_HIT_CACHEOP_WAR_IMPL; |
486 | addr = start & ~(dc_lsize - 1); | 488 | protected_blast_dcache_range(start, end); |
487 | aend = (end - 1) & ~(dc_lsize - 1); | ||
488 | |||
489 | while (1) { | ||
490 | /* Hit_Writeback_Inv_D */ | ||
491 | protected_writeback_dcache_line(addr); | ||
492 | if (addr == aend) | ||
493 | break; | ||
494 | addr += dc_lsize; | ||
495 | } | ||
496 | } | 489 | } |
497 | 490 | ||
498 | if (!cpu_icache_snoops_remote_store) { | 491 | if (!cpu_icache_snoops_remote_store && scache_size) { |
499 | if (end - start > scache_size) { | 492 | if (end - start > scache_size) |
500 | r4k_blast_scache(); | 493 | r4k_blast_scache(); |
501 | } else { | 494 | else |
502 | addr = start & ~(sc_lsize - 1); | 495 | protected_blast_scache_range(start, end); |
503 | aend = (end - 1) & ~(sc_lsize - 1); | ||
504 | |||
505 | while (1) { | ||
506 | /* Hit_Writeback_Inv_SD */ | ||
507 | protected_writeback_scache_line(addr); | ||
508 | if (addr == aend) | ||
509 | break; | ||
510 | addr += sc_lsize; | ||
511 | } | ||
512 | } | ||
513 | } | 496 | } |
514 | } | 497 | } |
515 | 498 | ||
516 | if (end - start > icache_size) | 499 | if (end - start > icache_size) |
517 | r4k_blast_icache(); | 500 | r4k_blast_icache(); |
518 | else { | 501 | else |
519 | addr = start & ~(ic_lsize - 1); | 502 | protected_blast_icache_range(start, end); |
520 | aend = (end - 1) & ~(ic_lsize - 1); | ||
521 | while (1) { | ||
522 | /* Hit_Invalidate_I */ | ||
523 | protected_flush_icache_line(addr); | ||
524 | if (addr == aend) | ||
525 | break; | ||
526 | addr += ic_lsize; | ||
527 | } | ||
528 | } | ||
529 | } | 503 | } |
530 | 504 | ||
531 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) | 505 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
@@ -619,27 +593,14 @@ static void r4k_flush_icache_page(struct vm_area_struct *vma, | |||
619 | 593 | ||
620 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | 594 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) |
621 | { | 595 | { |
622 | unsigned long end, a; | ||
623 | |||
624 | /* Catch bad driver code */ | 596 | /* Catch bad driver code */ |
625 | BUG_ON(size == 0); | 597 | BUG_ON(size == 0); |
626 | 598 | ||
627 | if (cpu_has_subset_pcaches) { | 599 | if (cpu_has_subset_pcaches) { |
628 | unsigned long sc_lsize = cpu_scache_line_size(); | 600 | if (size >= scache_size) |
629 | |||
630 | if (size >= scache_size) { | ||
631 | r4k_blast_scache(); | 601 | r4k_blast_scache(); |
632 | return; | 602 | else |
633 | } | 603 | blast_scache_range(addr, addr + size); |
634 | |||
635 | a = addr & ~(sc_lsize - 1); | ||
636 | end = (addr + size - 1) & ~(sc_lsize - 1); | ||
637 | while (1) { | ||
638 | flush_scache_line(a); /* Hit_Writeback_Inv_SD */ | ||
639 | if (a == end) | ||
640 | break; | ||
641 | a += sc_lsize; | ||
642 | } | ||
643 | return; | 604 | return; |
644 | } | 605 | } |
645 | 606 | ||
@@ -651,17 +612,8 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |||
651 | if (size >= dcache_size) { | 612 | if (size >= dcache_size) { |
652 | r4k_blast_dcache(); | 613 | r4k_blast_dcache(); |
653 | } else { | 614 | } else { |
654 | unsigned long dc_lsize = cpu_dcache_line_size(); | ||
655 | |||
656 | R4600_HIT_CACHEOP_WAR_IMPL; | 615 | R4600_HIT_CACHEOP_WAR_IMPL; |
657 | a = addr & ~(dc_lsize - 1); | 616 | blast_dcache_range(addr, addr + size); |
658 | end = (addr + size - 1) & ~(dc_lsize - 1); | ||
659 | while (1) { | ||
660 | flush_dcache_line(a); /* Hit_Writeback_Inv_D */ | ||
661 | if (a == end) | ||
662 | break; | ||
663 | a += dc_lsize; | ||
664 | } | ||
665 | } | 617 | } |
666 | 618 | ||
667 | bc_wback_inv(addr, size); | 619 | bc_wback_inv(addr, size); |
@@ -669,44 +621,22 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |||
669 | 621 | ||
670 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | 622 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) |
671 | { | 623 | { |
672 | unsigned long end, a; | ||
673 | |||
674 | /* Catch bad driver code */ | 624 | /* Catch bad driver code */ |
675 | BUG_ON(size == 0); | 625 | BUG_ON(size == 0); |
676 | 626 | ||
677 | if (cpu_has_subset_pcaches) { | 627 | if (cpu_has_subset_pcaches) { |
678 | unsigned long sc_lsize = cpu_scache_line_size(); | 628 | if (size >= scache_size) |
679 | |||
680 | if (size >= scache_size) { | ||
681 | r4k_blast_scache(); | 629 | r4k_blast_scache(); |
682 | return; | 630 | else |
683 | } | 631 | blast_scache_range(addr, addr + size); |
684 | |||
685 | a = addr & ~(sc_lsize - 1); | ||
686 | end = (addr + size - 1) & ~(sc_lsize - 1); | ||
687 | while (1) { | ||
688 | flush_scache_line(a); /* Hit_Writeback_Inv_SD */ | ||
689 | if (a == end) | ||
690 | break; | ||
691 | a += sc_lsize; | ||
692 | } | ||
693 | return; | 632 | return; |
694 | } | 633 | } |
695 | 634 | ||
696 | if (size >= dcache_size) { | 635 | if (size >= dcache_size) { |
697 | r4k_blast_dcache(); | 636 | r4k_blast_dcache(); |
698 | } else { | 637 | } else { |
699 | unsigned long dc_lsize = cpu_dcache_line_size(); | ||
700 | |||
701 | R4600_HIT_CACHEOP_WAR_IMPL; | 638 | R4600_HIT_CACHEOP_WAR_IMPL; |
702 | a = addr & ~(dc_lsize - 1); | 639 | blast_dcache_range(addr, addr + size); |
703 | end = (addr + size - 1) & ~(dc_lsize - 1); | ||
704 | while (1) { | ||
705 | flush_dcache_line(a); /* Hit_Writeback_Inv_D */ | ||
706 | if (a == end) | ||
707 | break; | ||
708 | a += dc_lsize; | ||
709 | } | ||
710 | } | 640 | } |
711 | 641 | ||
712 | bc_inv(addr, size); | 642 | bc_inv(addr, size); |
@@ -727,7 +657,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg) | |||
727 | 657 | ||
728 | R4600_HIT_CACHEOP_WAR_IMPL; | 658 | R4600_HIT_CACHEOP_WAR_IMPL; |
729 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | 659 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); |
730 | if (!cpu_icache_snoops_remote_store) | 660 | if (!cpu_icache_snoops_remote_store && scache_size) |
731 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); | 661 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
732 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | 662 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); |
733 | if (MIPS4K_ICACHE_REFILL_WAR) { | 663 | if (MIPS4K_ICACHE_REFILL_WAR) { |