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authorIngo Molnar <mingo@elte.hu>2009-08-24 06:25:44 -0400
committerIngo Molnar <mingo@elte.hu>2009-08-24 06:25:54 -0400
commit5f9ece02401116b29eb04396b99ea092acb75dd8 (patch)
treee10386e2dc63c275646b4eb0bed857da7bf86c6a /arch/mips/mipssim/sim_time.c
parent9f51e24ee8b5a1595b6a5ac0c2be278a16488e75 (diff)
parent422bef879e84104fee6dc68ded0e371dbeb5f88e (diff)
Merge commit 'v2.6.31-rc7' into x86/cleanups
Merge reason: we were on -rc1 before - go up to -rc7 Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/mips/mipssim/sim_time.c')
-rw-r--r--arch/mips/mipssim/sim_time.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index 0cea932f1241..5492c42f7650 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -89,13 +89,13 @@ unsigned __cpuinit get_c0_compare_int(void)
89 if (cpu_has_veic) { 89 if (cpu_has_veic) {
90 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 90 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
91 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 91 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
92 } else { 92
93#endif 93 return mips_cpu_timer_irq;
94 {
95 if (cpu_has_vint)
96 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
97 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
98 } 94 }
95#endif
96 if (cpu_has_vint)
97 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
98 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
99 99
100 return mips_cpu_timer_irq; 100 return mips_cpu_timer_irq;
101} 101}