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authorRalf Baechle <ralf@linux-mips.org>2006-04-03 12:56:36 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-04-18 22:14:21 -0400
commite4ac58afdfac792c0583af30dbd9eae53e24c78b (patch)
tree7517bef2c515fc630e4d3d238867b91cde96f558 /arch/mips/mips-boards
parentd35d473c25d43d7db3e5e18b66d558d2a631cca8 (diff)
[MIPS] Rewrite all the assembler interrupt handlers to C.
Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards')
-rw-r--r--arch/mips/mips-boards/atlas/Makefile2
-rw-r--r--arch/mips/mips-boards/atlas/atlas-irq.S120
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c92
-rw-r--r--arch/mips/mips-boards/malta/Makefile2
-rw-r--r--arch/mips/mips-boards/malta/malta-irq.S122
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c91
-rw-r--r--arch/mips/mips-boards/sead/Makefile2
-rw-r--r--arch/mips/mips-boards/sead/sead-irq.S111
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c86
-rw-r--r--arch/mips/mips-boards/sim/sim_int.c64
10 files changed, 317 insertions, 375 deletions
diff --git a/arch/mips/mips-boards/atlas/Makefile b/arch/mips/mips-boards/atlas/Makefile
index 50fec2a5aee6..d8dab75906bf 100644
--- a/arch/mips/mips-boards/atlas/Makefile
+++ b/arch/mips/mips-boards/atlas/Makefile
@@ -16,5 +16,5 @@
16# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17# 17#
18 18
19obj-y := atlas_int.o atlas-irq.o atlas_setup.o 19obj-y := atlas_int.o atlas_setup.o
20obj-$(CONFIG_KGDB) += atlas_gdb.o 20obj-$(CONFIG_KGDB) += atlas_gdb.o
diff --git a/arch/mips/mips-boards/atlas/atlas-irq.S b/arch/mips/mips-boards/atlas/atlas-irq.S
deleted file mode 100644
index 31bc99a52383..000000000000
--- a/arch/mips/mips-boards/atlas/atlas-irq.S
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Interrupt exception dispatch code.
19 */
20#include <linux/config.h>
21
22#include <asm/asm.h>
23#include <asm/mipsregs.h>
24#include <asm/regdef.h>
25#include <asm/stackframe.h>
26#include <asm/mips-boards/atlasint.h>
27
28/*
29 * Furthermore, the IRQs on the MIPS board look basically (barring software
30 * IRQs which we don't use at all and all external interrupt sources are
31 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
32 *
33 * MIPS IRQ Source
34 * -------- ------
35 * 0 Software (ignored)
36 * 1 Software (ignored)
37 * 2 Combined hardware interrupt (hw0)
38 * 3 Hardware (ignored)
39 * 4 Hardware (ignored)
40 * 5 Hardware (ignored)
41 * 6 Hardware (ignored)
42 * 7 R4k timer (what we use)
43 *
44 * Note: On the SEAD board thing are a little bit different.
45 * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
46 * wired to UART1.
47 *
48 * We handle the IRQ according to _our_ priority which is:
49 *
50 * Highest ---- R4k Timer
51 * Lowest ---- Combined hardware interrupt
52 *
53 * then we just return, if multiple IRQs are pending then we will just take
54 * another exception, big deal.
55 */
56
57 .text
58 .set noreorder
59 .set noat
60 .align 5
61 NESTED(mipsIRQ, PT_SIZE, sp)
62 SAVE_ALL
63 CLI
64 .set at
65
66 mfc0 s0, CP0_CAUSE # get irq bits
67 mfc0 s1, CP0_STATUS # get irq mask
68 andi s0, ST0_IM # CAUSE.CE may be non-zero!
69 and s0, s1
70
71#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
72 .set mips32
73 clz a0, s0
74 .set mips0
75 negu a0
76 addu a0, 31-CAUSEB_IP
77 bltz a0, spurious
78#else
79 beqz s0, spurious
80 li a0, 7
81
82 and t0, s0, 0xf000
83 sltiu t0, t0, 1
84 sll t0, 2
85 subu a0, t0
86 sll s0, t0
87
88 and t0, s0, 0xc000
89 sltiu t0, t0, 1
90 sll t0, 1
91 subu a0, t0
92 sll s0, t0
93
94 and t0, s0, 0x8000
95 sltiu t0, t0, 1
96 # sll t0, 0
97 subu a0, t0
98 # sll s0, t0
99#endif
100
101 li a1, MIPSCPU_INT_ATLAS
102 bne a0, a1, 1f
103 addu a0, MIPSCPU_INT_BASE
104
105 jal atlas_hw0_irqdispatch
106 move a0, sp
107
108 j ret_from_irq
109 nop
110
1111: jal do_IRQ
112 move a1, sp
113
114 j ret_from_irq
115 nop
116
117spurious:
118 j spurious_interrupt
119 nop
120 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index bc0ebc69bfb3..db53950b7cfb 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -39,8 +39,6 @@
39 39
40static struct atlas_ictrl_regs *atlas_hw0_icregs; 40static struct atlas_ictrl_regs *atlas_hw0_icregs;
41 41
42extern asmlinkage void mipsIRQ(void);
43
44#if 0 42#if 0
45#define DEBUG_INT(x...) printk(x) 43#define DEBUG_INT(x...) printk(x)
46#else 44#else
@@ -98,7 +96,7 @@ static inline int ls1bit32(unsigned int x)
98 return b; 96 return b;
99} 97}
100 98
101void atlas_hw0_irqdispatch(struct pt_regs *regs) 99static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
102{ 100{
103 unsigned long int_status; 101 unsigned long int_status;
104 int irq; 102 int irq;
@@ -116,6 +114,91 @@ void atlas_hw0_irqdispatch(struct pt_regs *regs)
116 do_IRQ(irq, regs); 114 do_IRQ(irq, regs);
117} 115}
118 116
117static inline int clz(unsigned long x)
118{
119 __asm__ (
120 " .set push \n"
121 " .set mips32 \n"
122 " clz %0, %1 \n"
123 " .set pop \n"
124 : "=r" (x)
125 : "r" (x));
126
127 return x;
128}
129
130/*
131 * Version of ffs that only looks at bits 12..15.
132 */
133static inline unsigned int irq_ffs(unsigned int pending)
134{
135#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
136 return -clz(pending) + 31 - CAUSEB_IP;
137#else
138 unsigned int a0 = 7;
139 unsigned int t0;
140
141 t0 = s0 & 0xf000;
142 t0 = t0 < 1;
143 t0 = t0 << 2;
144 a0 = a0 - t0;
145 s0 = s0 << t0;
146
147 t0 = s0 & 0xc000;
148 t0 = t0 < 1;
149 t0 = t0 << 1;
150 a0 = a0 - t0;
151 s0 = s0 << t0;
152
153 t0 = s0 & 0x8000;
154 t0 = t0 < 1;
155 //t0 = t0 << 2;
156 a0 = a0 - t0;
157 //s0 = s0 << t0;
158
159 return a0;
160#endif
161}
162
163/*
164 * IRQs on the Atlas board look basically (barring software IRQs which we
165 * don't use at all and all external interrupt sources are combined together
166 * on hardware interrupt 0 (MIPS IRQ 2)) like:
167 *
168 * MIPS IRQ Source
169 * -------- ------
170 * 0 Software (ignored)
171 * 1 Software (ignored)
172 * 2 Combined hardware interrupt (hw0)
173 * 3 Hardware (ignored)
174 * 4 Hardware (ignored)
175 * 5 Hardware (ignored)
176 * 6 Hardware (ignored)
177 * 7 R4k timer (what we use)
178 *
179 * We handle the IRQ according to _our_ priority which is:
180 *
181 * Highest ---- R4k Timer
182 * Lowest ---- Combined hardware interrupt
183 *
184 * then we just return, if multiple IRQs are pending then we will just take
185 * another exception, big deal.
186 */
187asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
188{
189 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
190 int irq;
191
192 irq = irq_ffs(pending);
193
194 if (irq == MIPSCPU_INT_ATLAS)
195 atlas_hw0_irqdispatch(regs);
196 else if (irq > 0)
197 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
198 else
199 spurious_interrupt(regs);
200}
201
119void __init arch_init_irq(void) 202void __init arch_init_irq(void)
120{ 203{
121 int i; 204 int i;
@@ -128,9 +211,6 @@ void __init arch_init_irq(void)
128 */ 211 */
129 atlas_hw0_icregs->intrsten = 0xffffffff; 212 atlas_hw0_icregs->intrsten = 0xffffffff;
130 213
131 /* Now safe to set the exception vector. */
132 set_except_vector(0, mipsIRQ);
133
134 for (i = ATLASINT_BASE; i <= ATLASINT_END; i++) { 214 for (i = ATLASINT_BASE; i <= ATLASINT_END; i++) {
135 irq_desc[i].status = IRQ_DISABLED; 215 irq_desc[i].status = IRQ_DISABLED;
136 irq_desc[i].action = 0; 216 irq_desc[i].action = 0;
diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile
index 3ae8fe6c0070..fd4c143c0e2f 100644
--- a/arch/mips/mips-boards/malta/Makefile
+++ b/arch/mips/mips-boards/malta/Makefile
@@ -19,4 +19,4 @@
19# under Linux. 19# under Linux.
20# 20#
21 21
22obj-y := malta_int.o malta-irq.o malta_setup.o 22obj-y := malta_int.o malta_setup.o
diff --git a/arch/mips/mips-boards/malta/malta-irq.S b/arch/mips/mips-boards/malta/malta-irq.S
deleted file mode 100644
index 6217aff3be03..000000000000
--- a/arch/mips/mips-boards/malta/malta-irq.S
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Interrupt exception dispatch code.
23 *
24 */
25#include <linux/config.h>
26
27#include <asm/asm.h>
28#include <asm/mipsregs.h>
29#include <asm/regdef.h>
30#include <asm/stackframe.h>
31#include <asm/mips-boards/maltaint.h>
32
33/*
34 * IRQs on the Malta board look basically (barring software IRQs which we
35 * don't use at all and all external interrupt sources are combined together
36 * on hardware interrupt 0 (MIPS IRQ 2)) like:
37 *
38 * MIPS IRQ Source
39 * -------- ------
40 * 0 Software (ignored)
41 * 1 Software (ignored)
42 * 2 Combined hardware interrupt (hw0)
43 * 3 Hardware (ignored)
44 * 4 Hardware (ignored)
45 * 5 Hardware (ignored)
46 * 6 Hardware (ignored)
47 * 7 R4k timer (what we use)
48 *
49 * We handle the IRQ according to _our_ priority which is:
50 *
51 * Highest ---- R4k Timer
52 * Lowest ---- Combined hardware interrupt
53 *
54 * then we just return, if multiple IRQs are pending then we will just take
55 * another exception, big deal.
56 */
57
58 .text
59 .set noreorder
60 .set noat
61 .align 5
62 NESTED(mipsIRQ, PT_SIZE, sp)
63 SAVE_ALL
64 CLI
65 .set at
66
67 mfc0 s0, CP0_CAUSE # get irq bits
68 mfc0 s1, CP0_STATUS # get irq mask
69 andi s0, ST0_IM # CAUSE.CE may be non-zero!
70 and s0, s1
71
72#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
73 .set mips32
74 clz a0, s0
75 .set mips0
76 negu a0
77 addu a0, 31-CAUSEB_IP
78 bltz a0, spurious
79#else
80 beqz s0, spurious
81 li a0, 7
82
83 and t0, s0, 0xf000
84 sltiu t0, t0, 1
85 sll t0, 2
86 subu a0, t0
87 sll s0, t0
88
89 and t0, s0, 0xc000
90 sltiu t0, t0, 1
91 sll t0, 1
92 subu a0, t0
93 sll s0, t0
94
95 and t0, s0, 0x8000
96 sltiu t0, t0, 1
97 # sll t0, 0
98 subu a0, t0
99 # sll s0, t0
100#endif
101
102 li a1, MIPSCPU_INT_I8259A
103 bne a0, a1, 1f
104 addu a0, MIPSCPU_INT_BASE
105
106 jal malta_hw0_irqdispatch
107 move a0, sp
108
109 j ret_from_irq
110 nop
1111:
112
113 jal do_IRQ
114 move a1, sp
115
116 j ret_from_irq
117 nop
118
119spurious:
120 j spurious_interrupt
121 nop
122 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index d06dc5ad6c9e..1da8c18b9c8e 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -40,7 +40,6 @@
40#include <asm/mips-boards/msc01_pci.h> 40#include <asm/mips-boards/msc01_pci.h>
41#include <asm/msc01_ic.h> 41#include <asm/msc01_ic.h>
42 42
43extern asmlinkage void mipsIRQ(void);
44extern void mips_timer_interrupt(void); 43extern void mips_timer_interrupt(void);
45 44
46static DEFINE_SPINLOCK(mips_irq_lock); 45static DEFINE_SPINLOCK(mips_irq_lock);
@@ -114,7 +113,7 @@ static inline int get_int(void)
114 return irq; 113 return irq;
115} 114}
116 115
117void malta_hw0_irqdispatch(struct pt_regs *regs) 116static void malta_hw0_irqdispatch(struct pt_regs *regs)
118{ 117{
119 int irq; 118 int irq;
120 119
@@ -182,6 +181,92 @@ void corehi_irqdispatch(struct pt_regs *regs)
182 die("CoreHi interrupt", regs); 181 die("CoreHi interrupt", regs);
183} 182}
184 183
184static inline int clz(unsigned long x)
185{
186 __asm__ (
187 " .set push \n"
188 " .set mips32 \n"
189 " clz %0, %1 \n"
190 " .set pop \n"
191 : "=r" (x)
192 : "r" (x));
193
194 return x;
195}
196
197/*
198 * Version of ffs that only looks at bits 12..15.
199 */
200static inline unsigned int irq_ffs(unsigned int pending)
201{
202#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
203 return -clz(pending) + 31 - CAUSEB_IP;
204#else
205 unsigned int a0 = 7;
206 unsigned int t0;
207
208 t0 = s0 & 0xf000;
209 t0 = t0 < 1;
210 t0 = t0 << 2;
211 a0 = a0 - t0;
212 s0 = s0 << t0;
213
214 t0 = s0 & 0xc000;
215 t0 = t0 < 1;
216 t0 = t0 << 1;
217 a0 = a0 - t0;
218 s0 = s0 << t0;
219
220 t0 = s0 & 0x8000;
221 t0 = t0 < 1;
222 //t0 = t0 << 2;
223 a0 = a0 - t0;
224 //s0 = s0 << t0;
225
226 return a0;
227#endif
228}
229
230/*
231 * IRQs on the Malta board look basically (barring software IRQs which we
232 * don't use at all and all external interrupt sources are combined together
233 * on hardware interrupt 0 (MIPS IRQ 2)) like:
234 *
235 * MIPS IRQ Source
236 * -------- ------
237 * 0 Software (ignored)
238 * 1 Software (ignored)
239 * 2 Combined hardware interrupt (hw0)
240 * 3 Hardware (ignored)
241 * 4 Hardware (ignored)
242 * 5 Hardware (ignored)
243 * 6 Hardware (ignored)
244 * 7 R4k timer (what we use)
245 *
246 * We handle the IRQ according to _our_ priority which is:
247 *
248 * Highest ---- R4k Timer
249 * Lowest ---- Combined hardware interrupt
250 *
251 * then we just return, if multiple IRQs are pending then we will just take
252 * another exception, big deal.
253 */
254
255asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
256{
257 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
258 int irq;
259
260 irq = irq_ffs(pending);
261
262 if (irq == MIPSCPU_INT_I8259A)
263 malta_hw0_irqdispatch(regs);
264 else if (irq > 0)
265 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
266 else
267 spurious_interrupt(regs);
268}
269
185static struct irqaction i8259irq = { 270static struct irqaction i8259irq = {
186 .handler = no_action, 271 .handler = no_action,
187 .name = "XT-PIC cascade" 272 .name = "XT-PIC cascade"
@@ -214,7 +299,6 @@ int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
214 299
215void __init arch_init_irq(void) 300void __init arch_init_irq(void)
216{ 301{
217 set_except_vector(0, mipsIRQ);
218 init_i8259_irqs(); 302 init_i8259_irqs();
219 303
220 if (!cpu_has_veic) 304 if (!cpu_has_veic)
@@ -245,7 +329,6 @@ void __init arch_init_irq(void)
245 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 329 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
246 } 330 }
247 else { 331 else {
248 set_except_vector(0, mipsIRQ);
249 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); 332 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
250 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 333 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
251 } 334 }
diff --git a/arch/mips/mips-boards/sead/Makefile b/arch/mips/mips-boards/sead/Makefile
index 01780b605346..224bb848f16b 100644
--- a/arch/mips/mips-boards/sead/Makefile
+++ b/arch/mips/mips-boards/sead/Makefile
@@ -23,4 +23,4 @@
23# under Linux. 23# under Linux.
24# 24#
25 25
26obj-y := sead_int.o sead-irq.o sead_setup.o 26obj-y := sead_int.o sead_setup.o
diff --git a/arch/mips/mips-boards/sead/sead-irq.S b/arch/mips/mips-boards/sead/sead-irq.S
deleted file mode 100644
index d5dea1d2e220..000000000000
--- a/arch/mips/mips-boards/sead/sead-irq.S
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Interrupt exception dispatch code.
23 *
24 */
25#include <linux/config.h>
26
27#include <asm/asm.h>
28#include <asm/mipsregs.h>
29#include <asm/regdef.h>
30#include <asm/stackframe.h>
31#include <asm/mips-boards/seadint.h>
32
33/*
34 * IRQs on the SEAD board look basically are combined together on hardware
35 * interrupt 0 (MIPS IRQ 2)) like:
36 *
37 * MIPS IRQ Source
38 * -------- ------
39 * 0 Software (ignored)
40 * 1 Software (ignored)
41 * 2 UART0 (hw0)
42 * 3 UART1 (hw1)
43 * 4 Hardware (ignored)
44 * 5 Hardware (ignored)
45 * 6 Hardware (ignored)
46 * 7 R4k timer (what we use)
47 *
48 * We handle the IRQ according to _our_ priority which is:
49 *
50 * Highest ---- R4k Timer
51 * Lowest ---- Combined hardware interrupt
52 *
53 * then we just return, if multiple IRQs are pending then we will just take
54 * another exception, big deal.
55 */
56
57 .text
58 .set noreorder
59 .set noat
60 .align 5
61 NESTED(mipsIRQ, PT_SIZE, sp)
62 SAVE_ALL
63 CLI
64 .set at
65
66 mfc0 s0, CP0_CAUSE # get irq bits
67 mfc0 s1, CP0_STATUS # get irq mask
68 andi s0, ST0_IM # CAUSE.CE may be non-zero!
69 and s0, s1
70
71#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
72 .set mips32
73 clz a0, s0
74 .set mips0
75 negu a0
76 addu a0, 31-CAUSEB_IP
77 bltz a0, spurious
78#else
79 beqz s0, spurious
80 li a0, 7
81
82 and t0, s0, 0xf000
83 sltiu t0, t0, 1
84 sll t0, 2
85 subu a0, t0
86 sll s0, t0
87
88 and t0, s0, 0xc000
89 sltiu t0, t0, 1
90 sll t0, 1
91 subu a0, t0
92 sll s0, t0
93
94 and t0, s0, 0x8000
95 sltiu t0, t0, 1
96 # sll t0, 0
97 subu a0, t0
98 # sll s0, t0
99#endif
100
101 addu a0, MIPSCPU_INT_BASE
102 jal do_IRQ
103 move a1, sp
104
105 j ret_from_irq
106 nop
107
108spurious:
109 j spurious_interrupt
110 nop
111 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 90fda0d9915f..9168d934c661 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -24,16 +24,94 @@
24#include <linux/irq.h> 24#include <linux/irq.h>
25 25
26#include <asm/irq_cpu.h> 26#include <asm/irq_cpu.h>
27#include <asm/mipsregs.h>
27#include <asm/system.h> 28#include <asm/system.h>
28 29
29#include <asm/mips-boards/seadint.h> 30#include <asm/mips-boards/seadint.h>
30 31
31extern asmlinkage void mipsIRQ(void); 32static inline int clz(unsigned long x)
33{
34 __asm__ (
35 " .set push \n"
36 " .set mips32 \n"
37 " clz %0, %1 \n"
38 " .set pop \n"
39 : "=r" (x)
40 : "r" (x));
41
42 return x;
43}
44
45/*
46 * Version of ffs that only looks at bits 12..15.
47 */
48static inline unsigned int irq_ffs(unsigned int pending)
49{
50#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
51 return -clz(pending) + 31 - CAUSEB_IP;
52#else
53 unsigned int a0 = 7;
54 unsigned int t0;
55
56 t0 = s0 & 0xf000;
57 t0 = t0 < 1;
58 t0 = t0 << 2;
59 a0 = a0 - t0;
60 s0 = s0 << t0;
61
62 t0 = s0 & 0xc000;
63 t0 = t0 < 1;
64 t0 = t0 << 1;
65 a0 = a0 - t0;
66 s0 = s0 << t0;
67
68 t0 = s0 & 0x8000;
69 t0 = t0 < 1;
70 //t0 = t0 << 2;
71 a0 = a0 - t0;
72 //s0 = s0 << t0;
73
74 return a0;
75#endif
76}
77
78/*
79 * IRQs on the SEAD board look basically are combined together on hardware
80 * interrupt 0 (MIPS IRQ 2)) like:
81 *
82 * MIPS IRQ Source
83 * -------- ------
84 * 0 Software (ignored)
85 * 1 Software (ignored)
86 * 2 UART0 (hw0)
87 * 3 UART1 (hw1)
88 * 4 Hardware (ignored)
89 * 5 Hardware (ignored)
90 * 6 Hardware (ignored)
91 * 7 R4k timer (what we use)
92 *
93 * We handle the IRQ according to _our_ priority which is:
94 *
95 * Highest ---- R4k Timer
96 * Lowest ---- Combined hardware interrupt
97 *
98 * then we just return, if multiple IRQs are pending then we will just take
99 * another exception, big deal.
100 */
101asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
102{
103 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
104 int irq;
105
106 irq = irq_ffs(pending);
107
108 if (irq >= 0)
109 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
110 else
111 spurious_interrupt(regs);
112}
32 113
33void __init arch_init_irq(void) 114void __init arch_init_irq(void)
34{ 115{
35 mips_cpu_irq_init(MIPSCPU_INT_BASE); 116 mips_cpu_irq_init(MIPSCPU_INT_BASE);
36
37 /* Now safe to set the exception vector. */
38 set_except_vector(0, mipsIRQ);
39} 117}
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c
index a4d0a2c05031..2c15c8efec4e 100644
--- a/arch/mips/mips-boards/sim/sim_int.c
+++ b/arch/mips/mips-boards/sim/sim_int.c
@@ -25,17 +25,71 @@
25 25
26extern void mips_cpu_irq_init(int); 26extern void mips_cpu_irq_init(int);
27 27
28extern asmlinkage void simIRQ(void); 28static inline int clz(unsigned long x)
29{
30 __asm__ (
31 " .set push \n"
32 " .set mips32 \n"
33 " clz %0, %1 \n"
34 " .set pop \n"
35 : "=r" (x)
36 : "r" (x));
37
38 return x;
39}
40
41/*
42 * Version of ffs that only looks at bits 12..15.
43 */
44static inline unsigned int irq_ffs(unsigned int pending)
45{
46#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
47 return -clz(pending) + 31 - CAUSEB_IP;
48#else
49 unsigned int a0 = 7;
50 unsigned int t0;
51
52 t0 = s0 & 0xf000;
53 t0 = t0 < 1;
54 t0 = t0 << 2;
55 a0 = a0 - t0;
56 s0 = s0 << t0;
57
58 t0 = s0 & 0xc000;
59 t0 = t0 < 1;
60 t0 = t0 << 1;
61 a0 = a0 - t0;
62 s0 = s0 << t0;
29 63
30asmlinkage void sim_hw0_irqdispatch(struct pt_regs *regs) 64 t0 = s0 & 0x8000;
65 t0 = t0 < 1;
66 //t0 = t0 << 2;
67 a0 = a0 - t0;
68 //s0 = s0 << t0;
69
70 return a0;
71#endif
72}
73
74static inline void sim_hw0_irqdispatch(struct pt_regs *regs)
31{ 75{
32 do_IRQ(2, regs); 76 do_IRQ(2, regs);
33} 77}
34 78
35void __init arch_init_irq(void) 79asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
36{ 80{
37 /* Now safe to set the exception vector. */ 81 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
38 set_except_vector(0, simIRQ); 82 int irq;
83
84 irq = irq_ffs(pending);
39 85
86 if (irq > 0)
87 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
88 else
89 spurious_interrupt(regs);
90}
91
92void __init arch_init_irq(void)
93{
40 mips_cpu_irq_init(MIPSCPU_INT_BASE); 94 mips_cpu_irq_init(MIPSCPU_INT_BASE);
41} 95}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 20:47:26 -0500