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authorWill Deacon <will.deacon@arm.com>2012-07-19 06:51:05 -0400
committerWill Deacon <will.deacon@arm.com>2012-11-09 09:13:19 -0500
commitdbf62d50067e55a782583fe53c3d2a3d98b1f6f3 (patch)
tree1bca43e9824e79d97bc32445182fe91a6600e035 /arch/mips/math-emu/sp_tlong.c
parent0cbbbad63179652272cc5e18a68d69bfc8dd25ce (diff)
ARM: mm: introduce L_PTE_VALID for page table entries
For long-descriptor translation table formats, the ARMv7 architecture defines the last two bits of the second- and third-level descriptors to be: x0b - Invalid 01b - Block (second-level), Reserved (third-level) 11b - Table (second-level), Page (third-level) This allows us to define L_PTE_PRESENT as (3 << 0) and use this value to create ptes directly. However, when determining whether a given pte value is present in the low-level page table accessors, we only need to check the least significant bit of the descriptor, allowing us to write faulting, present entries which are required for PROT_NONE mappings. This patch introduces L_PTE_VALID, which can be used to test whether a pte should fault, and updates the low-level page table accessors accordingly. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/mips/math-emu/sp_tlong.c')
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