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authorRob Kendrick <rob.kendrick@codethink.co.uk>2014-07-23 05:03:58 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-07-30 13:13:35 -0400
commitc3b9b945e02e011c63522761e91133ea43eb6939 (patch)
tree016753aecbdfb9764f940cfb3bcf2186bfe56b39 /arch/mips/math-emu/cp1emu.c
parent8393c524a25609a30129e4a8975cf3b91f6c16a5 (diff)
MIPS: math-emu: Fix instruction decoding.
Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu/cp1emu.c')
-rw-r--r--arch/mips/math-emu/cp1emu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 736c17a226e9..bf0fc6b16ad9 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1827,7 +1827,7 @@ dcopuop:
1827 case -1: 1827 case -1:
1828 1828
1829 if (cpu_has_mips_4_5_r) 1829 if (cpu_has_mips_4_5_r)
1830 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1830 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1831 else 1831 else
1832 cbit = FPU_CSR_COND; 1832 cbit = FPU_CSR_COND;
1833 if (rv.w) 1833 if (rv.w)