MIPS: math-emu: Remove `modeindex' macro

Commit 56a64733 [MIPS: math-emu: Switch to using the MIPS rounding
modes.] removed the distinction between hardware and emulator rounding
mode encodings, the hardware encoding is now used in emulation as well.
Complement the change and remove the `modeindex' macro previously used
for indexing into encoding translation tables, it now does nothing and
only obfuscates code by reinserting the value extracted from FCSR.
Adjust comments accordingly.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9680/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 8 insertions, 18 deletions

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 3c5b1c8d73ee..fc6ce90d21f8 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -65,9 +65,6 @@ static int fpux_emu(struct pt_regs *,
 #define FPCREG_RID      0       /* $0  = revision id */
 #define FPCREG_CSR      31      /* $31 = csr */
 
-/* Determine rounding mode from the RM bits of the FCSR */
-#define modeindex(v) ((v) & FPU_CSR_RM)
-
 /* convert condition code register number to csr bit */
 const unsigned int fpucondbit[8] = {
         FPU_CSR_COND0,
@@ -1051,7 +1048,6 @@ emul:
                         /* cop control register rd -> gpr[rt] */
                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
                                 value = ctx->fcr31;
-                                value = (value & ~FPU_CSR_RM) | modeindex(value);
                                 pr_debug("%p gpr[%d]<-csr=%08x\n",
                                          (void *) (xcp->cp0_epc),
                                          MIPSInst_RT(ir), value);
@@ -1078,12 +1074,8 @@ emul:
                                          (void *) (xcp->cp0_epc),
                                          MIPSInst_RT(ir), value);
 
-                                /*
-                                 * Don't write reserved bits,
-                                 * and convert to ieee library modes
-                                 */
-                                ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
-                                             modeindex(value);
+                                /* Don't write reserved bits.  */
+                                ctx->fcr31 = value & ~FPU_CSR_RSVD;
                         }
                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
                                 return SIGFPE;
@@ -1675,7 +1667,7 @@ copcsr:
 
                         oldrm = ieee754_csr.rm;
                         SPFROMREG(fs, MIPSInst_FS(ir));
-                        ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
+                        ieee754_csr.rm = MIPSInst_FUNC(ir);
                         rv.w = ieee754sp_tint(fs);
                         ieee754_csr.rm = oldrm;
                         rfmt = w_fmt;
@@ -1699,7 +1691,7 @@ copcsr:
 
                         oldrm = ieee754_csr.rm;
                         SPFROMREG(fs, MIPSInst_FS(ir));
-                        ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
+                        ieee754_csr.rm = MIPSInst_FUNC(ir);
                         rv.l = ieee754sp_tlong(fs);
                         ieee754_csr.rm = oldrm;
                         rfmt = l_fmt;
@@ -1852,7 +1844,7 @@ dcopuop:
 
                         oldrm = ieee754_csr.rm;
                         DPFROMREG(fs, MIPSInst_FS(ir));
-                        ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
+                        ieee754_csr.rm = MIPSInst_FUNC(ir);
                         rv.w = ieee754dp_tint(fs);
                         ieee754_csr.rm = oldrm;
                         rfmt = w_fmt;
@@ -1876,7 +1868,7 @@ dcopuop:
 
                         oldrm = ieee754_csr.rm;
                         DPFROMREG(fs, MIPSInst_FS(ir));
-                        ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
+                        ieee754_csr.rm = MIPSInst_FUNC(ir);
                         rv.l = ieee754dp_tlong(fs);
                         ieee754_csr.rm = oldrm;
                         rfmt = l_fmt;
@@ -2081,10 +2073,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
                 else {
                         /*
-                         * The 'ieee754_csr' is an alias of
-                         * ctx->fcr31.  No need to copy ctx->fcr31 to
-                         * ieee754_csr.  But ieee754_csr.rm is ieee
-                         * library modes. (not mips rounding mode)
+                         * The 'ieee754_csr' is an alias of ctx->fcr31.
+                         * No need to copy ctx->fcr31 to ieee754_csr.
                          */
                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
                 }