diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2014-05-23 10:29:44 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-23 18:07:01 -0400 |
| commit | b633648c5ad3cfbda0b3daea50d2135d44899259 (patch) | |
| tree | 6100185cae10f36a55e71c3b220fc79cfa14b7c0 /arch/mips/lib/mips-atomic.c | |
| parent | 8b2e62cc34feaaf1cac9440a93fb18ac0b1e81bc (diff) | |
MIPS: MT: Remove SMTC support
Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.
Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lib/mips-atomic.c')
| -rw-r--r-- | arch/mips/lib/mips-atomic.c | 46 |
1 files changed, 6 insertions, 40 deletions
diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c index 6807f7172eaf..57bcdaf1f1c8 100644 --- a/arch/mips/lib/mips-atomic.c +++ b/arch/mips/lib/mips-atomic.c | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | #include <linux/export.h> | 15 | #include <linux/export.h> |
| 16 | #include <linux/stringify.h> | 16 | #include <linux/stringify.h> |
| 17 | 17 | ||
| 18 | #if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) | 18 | #ifndef CONFIG_CPU_MIPSR2 |
| 19 | 19 | ||
| 20 | /* | 20 | /* |
| 21 | * For cli() we have to insert nops to make sure that the new value | 21 | * For cli() we have to insert nops to make sure that the new value |
| @@ -42,12 +42,7 @@ notrace void arch_local_irq_disable(void) | |||
| 42 | __asm__ __volatile__( | 42 | __asm__ __volatile__( |
| 43 | " .set push \n" | 43 | " .set push \n" |
| 44 | " .set noat \n" | 44 | " .set noat \n" |
| 45 | #ifdef CONFIG_MIPS_MT_SMTC | 45 | #if defined(CONFIG_CPU_MIPSR2) |
| 46 | " mfc0 $1, $2, 1 \n" | ||
| 47 | " ori $1, 0x400 \n" | ||
| 48 | " .set noreorder \n" | ||
| 49 | " mtc0 $1, $2, 1 \n" | ||
| 50 | #elif defined(CONFIG_CPU_MIPSR2) | ||
| 51 | /* see irqflags.h for inline function */ | 46 | /* see irqflags.h for inline function */ |
| 52 | #else | 47 | #else |
| 53 | " mfc0 $1,$12 \n" | 48 | " mfc0 $1,$12 \n" |
| @@ -77,13 +72,7 @@ notrace unsigned long arch_local_irq_save(void) | |||
| 77 | " .set push \n" | 72 | " .set push \n" |
| 78 | " .set reorder \n" | 73 | " .set reorder \n" |
| 79 | " .set noat \n" | 74 | " .set noat \n" |
| 80 | #ifdef CONFIG_MIPS_MT_SMTC | 75 | #if defined(CONFIG_CPU_MIPSR2) |
| 81 | " mfc0 %[flags], $2, 1 \n" | ||
| 82 | " ori $1, %[flags], 0x400 \n" | ||
| 83 | " .set noreorder \n" | ||
| 84 | " mtc0 $1, $2, 1 \n" | ||
| 85 | " andi %[flags], %[flags], 0x400 \n" | ||
| 86 | #elif defined(CONFIG_CPU_MIPSR2) | ||
| 87 | /* see irqflags.h for inline function */ | 76 | /* see irqflags.h for inline function */ |
| 88 | #else | 77 | #else |
| 89 | " mfc0 %[flags], $12 \n" | 78 | " mfc0 %[flags], $12 \n" |
| @@ -108,29 +97,13 @@ notrace void arch_local_irq_restore(unsigned long flags) | |||
| 108 | { | 97 | { |
| 109 | unsigned long __tmp1; | 98 | unsigned long __tmp1; |
| 110 | 99 | ||
| 111 | #ifdef CONFIG_MIPS_MT_SMTC | ||
| 112 | /* | ||
| 113 | * SMTC kernel needs to do a software replay of queued | ||
| 114 | * IPIs, at the cost of branch and call overhead on each | ||
| 115 | * local_irq_restore() | ||
| 116 | */ | ||
| 117 | if (unlikely(!(flags & 0x0400))) | ||
| 118 | smtc_ipi_replay(); | ||
| 119 | #endif | ||
| 120 | preempt_disable(); | 100 | preempt_disable(); |
| 121 | 101 | ||
| 122 | __asm__ __volatile__( | 102 | __asm__ __volatile__( |
| 123 | " .set push \n" | 103 | " .set push \n" |
| 124 | " .set noreorder \n" | 104 | " .set noreorder \n" |
| 125 | " .set noat \n" | 105 | " .set noat \n" |
| 126 | #ifdef CONFIG_MIPS_MT_SMTC | 106 | #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) |
| 127 | " mfc0 $1, $2, 1 \n" | ||
| 128 | " andi %[flags], 0x400 \n" | ||
| 129 | " ori $1, 0x400 \n" | ||
| 130 | " xori $1, 0x400 \n" | ||
| 131 | " or %[flags], $1 \n" | ||
| 132 | " mtc0 %[flags], $2, 1 \n" | ||
| 133 | #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) | ||
| 134 | /* see irqflags.h for inline function */ | 107 | /* see irqflags.h for inline function */ |
| 135 | #elif defined(CONFIG_CPU_MIPSR2) | 108 | #elif defined(CONFIG_CPU_MIPSR2) |
| 136 | /* see irqflags.h for inline function */ | 109 | /* see irqflags.h for inline function */ |
| @@ -163,14 +136,7 @@ notrace void __arch_local_irq_restore(unsigned long flags) | |||
| 163 | " .set push \n" | 136 | " .set push \n" |
| 164 | " .set noreorder \n" | 137 | " .set noreorder \n" |
| 165 | " .set noat \n" | 138 | " .set noat \n" |
| 166 | #ifdef CONFIG_MIPS_MT_SMTC | 139 | #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) |
| 167 | " mfc0 $1, $2, 1 \n" | ||
| 168 | " andi %[flags], 0x400 \n" | ||
| 169 | " ori $1, 0x400 \n" | ||
| 170 | " xori $1, 0x400 \n" | ||
| 171 | " or %[flags], $1 \n" | ||
| 172 | " mtc0 %[flags], $2, 1 \n" | ||
| 173 | #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) | ||
| 174 | /* see irqflags.h for inline function */ | 140 | /* see irqflags.h for inline function */ |
| 175 | #elif defined(CONFIG_CPU_MIPSR2) | 141 | #elif defined(CONFIG_CPU_MIPSR2) |
| 176 | /* see irqflags.h for inline function */ | 142 | /* see irqflags.h for inline function */ |
| @@ -192,4 +158,4 @@ notrace void __arch_local_irq_restore(unsigned long flags) | |||
| 192 | } | 158 | } |
| 193 | EXPORT_SYMBOL(__arch_local_irq_restore); | 159 | EXPORT_SYMBOL(__arch_local_irq_restore); |
| 194 | 160 | ||
| 195 | #endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */ | 161 | #endif /* !CONFIG_CPU_MIPSR2 */ |