Merge branch 'clocksource/cleanup' into next/cleanup

Clockevent cleanup series from Shawn Guo.

Resolved move/change conflict in mach-pxa/time.c due to the sys_timer
cleanup.

* clocksource/cleanup:
  clocksource: use clockevents_config_and_register() where possible
  ARM: use clockevents_config_and_register() where possible
  clockevents: export clockevents_config_and_register for module use
  + sync to Linux 3.8-rc3

Signed-off-by: Olof Johansson <olof@lixom.net>

Conflicts:
	arch/arm/mach-pxa/time.c

14 files changed, 13 insertions, 49 deletions

diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 9690998d4ef3..50285b2c7ffe 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -200,6 +200,9 @@ void output_mm_defines(void)
         DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
         DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
         BLANK();
+        DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
+        DEFINE(_PAGE_SIZE, PAGE_SIZE);
+        BLANK();
 }
 
 #ifdef CONFIG_32BIT
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 8882e5766f27..8a0096d62812 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -19,7 +19,6 @@
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
 #include <asm/war.h>
-#include <asm/page.h>
 #include <asm/thread_info.h>
 
 #define PANIC_PIC(msg)                                  \
@@ -483,8 +482,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
         MFC0    k1, CP0_ENTRYHI
         andi    k1, 0xff        /* ASID_MASK */
         MFC0    k0, CP0_EPC
-        PTR_SRL k0, PAGE_SHIFT + 1
-        PTR_SLL k0, PAGE_SHIFT + 1
+        PTR_SRL k0, _PAGE_SHIFT + 1
+        PTR_SLL k0, _PAGE_SHIFT + 1
         or      k1, k0
         MTC0    k1, CP0_ENTRYHI
         mtc0_tlbw_hazard
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index ea695d9605e9..fcf97312f328 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -21,7 +21,6 @@
 #include <asm/asmmacro.h>
 #include <asm/irqflags.h>
 #include <asm/regdef.h>
-#include <asm/page.h>
 #include <asm/pgtable-bits.h>
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 0441f54b2a6a..207f1341578b 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -15,7 +15,6 @@
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
-#include <asm/page.h>
 #include <asm/pgtable-bits.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index b14c14d90fc2..d9c81c5a6c90 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -847,7 +847,6 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
         [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
-        [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
 };
 
 /* 24K/34K/1004K cores can share the same cache event map. */
@@ -1115,24 +1114,12 @@ static const struct mips_perf_event xlp_cache_map
                 [C(RESULT_ACCESS)]      = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
                 [C(RESULT_MISS)]        = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
         },
-        [C(OP_PREFETCH)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
 },
 [C(L1I)] = {
         [C(OP_READ)] = {
                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
                 [C(RESULT_MISS)]        = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
         },
-        [C(OP_WRITE)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
-        [C(OP_PREFETCH)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
 },
 [C(LL)] = {
         [C(OP_READ)] = {
@@ -1143,10 +1130,6 @@ static const struct mips_perf_event xlp_cache_map
                 [C(RESULT_ACCESS)]      = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
                 [C(RESULT_MISS)]        = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
         },
-        [C(OP_PREFETCH)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
 },
 [C(DTLB)] = {
         /*
@@ -1154,45 +1137,24 @@ static const struct mips_perf_event xlp_cache_map
          * read and write.
          */
         [C(OP_READ)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
                 [C(RESULT_MISS)]        = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
         },
         [C(OP_WRITE)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
                 [C(RESULT_MISS)]        = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
         },
-        [C(OP_PREFETCH)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
 },
 [C(ITLB)] = {
         [C(OP_READ)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
                 [C(RESULT_MISS)]        = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
         },
         [C(OP_WRITE)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
                 [C(RESULT_MISS)]        = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
         },
-        [C(OP_PREFETCH)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
 },
 [C(BPU)] = {
         [C(OP_READ)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
                 [C(RESULT_MISS)]        = { 0x25, CNTR_ALL },
         },
-        [C(OP_WRITE)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
-        [C(OP_PREFETCH)] = {
-                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
-                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
-        },
 },
 };
 
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 9c51be5a163a..8d32d5a6b460 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -15,7 +15,6 @@
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
-#include <asm/page.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
 #include <asm/thread_info.h>
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 42d2a3938420..8decdfacb448 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -15,7 +15,6 @@
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
-#include <asm/page.h>
 #include <asm/pgtable-bits.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index e4142c5f7c2b..804ebb2c34a6 100644
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -9,7 +9,6 @@
 #include <asm/asm.h>
 #include <asm/asmmacro.h>
 #include <asm/regdef.h>
-#include <asm/page.h>
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
 #include <asm/addrspace.h>
@@ -50,7 +49,7 @@ process_entry:
         and             s3, s2, 0x8
         beq             s3, zero, process_entry
         and             s2, s2, ~0x8
-        li              s6, (1 << PAGE_SHIFT) / SZREG
+        li              s6, (1 << _PAGE_SHIFT) / SZREG
 
 copy_word:
         /* copy page word by word */
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 374f66e05f3d..d20a4bc9ed05 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -583,6 +583,7 @@ einval:	li	v0, -ENOSYS
         sys     sys_process_vm_readv    6       /* 4345 */
         sys     sys_process_vm_writev   6
         sys     sys_kcmp                5
+        sys     sys_finit_module        3
         .endm
 
         /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 169de6a6d916..b64f642da073 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -422,4 +422,5 @@ sys_call_table:
         PTR     sys_process_vm_readv
         PTR     sys_process_vm_writev           /* 5305 */
         PTR     sys_kcmp
+        PTR     sys_finit_module
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index ad3de9668da9..c29ac197f446 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -416,4 +416,5 @@ EXPORT(sysn32_call_table)
         PTR     compat_sys_process_vm_readv
         PTR     compat_sys_process_vm_writev    /* 6310 */
         PTR     sys_kcmp
+        PTR     sys_finit_module
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9601be6afa3d..cf3e75e46650 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -540,4 +540,5 @@ sys_call_table:
         PTR     compat_sys_process_vm_readv     /* 4345 */
         PTR     compat_sys_process_vm_writev
         PTR     sys_kcmp
+        PTR     sys_finit_module
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 2e6374a589ec..66bf4e22d9b9 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -188,7 +188,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 }
 
 /* preload SMP state for boot cpu */
-void __devinit smp_prepare_boot_cpu(void)
+void smp_prepare_boot_cpu(void)
 {
         set_cpu_possible(0, true);
         set_cpu_online(0, true);
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 007ccbe1e264..0a4336b803e9 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -1,7 +1,8 @@
 #include <asm/asm-offsets.h>
-#include <asm/page.h>
 #include <asm/thread_info.h>
 
+#define PAGE_SIZE _PAGE_SIZE
+
 /*
  * Put .bss..swapper_pg_dir as the first thing in .bss. This will
  * ensure that it has .bss alignment (64K).