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authorManuel Lauss <mano@roarinelk.homelinux.net>2008-12-21 03:26:22 -0500
committerRalf Baechle <ralf@linux-mips.org>2009-01-11 04:57:26 -0500
commit779e7d41ad004946603da139da99ba775f74cb1c (patch)
treebefca6de7d38cfb689150e722164e3d2dad7aca7 /arch/mips/kernel
parent074cf656700ddd1d2bd7f815f78e785418beb898 (diff)
MIPS: make cp0 counter clocksource/event usable as fallback.
The current mips clock build infrastructure lets a system only use either the MIPS cp0 counter or a SoC specific timer as a clocksource / clockevent device. This patch renames the core cp0 counter clocksource / clockevent functions from mips_* to r4k_* and updates the wrappers in asm-mips/time.h to call these renamed functions instead. Chips which can detect whether it is safe to use a chip-specific timer can now fall back on the cp0 counter if necessary and possible (e.g. Alchemy with a follow-on patch). Existing behaviour is not changed in any way. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/Makefile4
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/csrc-r4k.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 3ab4ac971fc4..e96122159928 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
9 time.o topology.o traps.o unaligned.o watch.o 9 time.o topology.o traps.o unaligned.o watch.o
10 10
11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
12obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 12obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o 13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o 14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
@@ -17,7 +17,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
20obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 20obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
23 23
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index e1ec83b68031..0015e442572b 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -160,7 +160,7 @@ int c0_compare_int_usable(void)
160 160
161#ifndef CONFIG_MIPS_MT_SMTC 161#ifndef CONFIG_MIPS_MT_SMTC
162 162
163int __cpuinit mips_clockevent_init(void) 163int __cpuinit r4k_clockevent_init(void)
164{ 164{
165 uint64_t mips_freq = mips_hpt_frequency; 165 uint64_t mips_freq = mips_hpt_frequency;
166 unsigned int cpu = smp_processor_id(); 166 unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 74fb74583b4e..f1a2893931ed 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = {
22 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 22 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
23}; 23};
24 24
25int __init init_mips_clocksource(void) 25int __init init_r4k_clocksource(void)
26{ 26{
27 if (!cpu_has_counter || !mips_hpt_frequency) 27 if (!cpu_has_counter || !mips_hpt_frequency)
28 return -ENXIO; 28 return -ENXIO;