MIPS: Correct MIPS16 BREAK code interpretation

Correct the interpretation of the immediate MIPS16 BREAK instruction
code embedded in the instruction word across bits 10:5 rather than 11:6
as current code implies, fixing the interpretation of integer overflow
and divide by zero traps.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9695/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 5e1f28779340..b6f23343a8db 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -925,7 +925,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
                         if (__get_user(instr[0],
                                        (u16 __user *)msk_isa16_mode(epc)))
                                 goto out_sigsegv;
-                        bcode = (instr[0] >> 6) & 0x3f;
+                        bcode = (instr[0] >> 5) & 0x3f;
                         do_trap_or_bp(regs, bcode, "Break");
                         goto out;
                 }