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authorRalf Baechle <ralf@linux-mips.org>2015-02-19 10:00:34 -0500
committerRalf Baechle <ralf@linux-mips.org>2015-02-19 10:00:34 -0500
commit661af35e5fd878f915ed05dbbfe383f64133f98c (patch)
tree956b7efd662b682224e61060552fdcf4201101bf /arch/mips/kernel
parentca5d25642e212f73492d332d95dc90ef46a0e8dc (diff)
parentf296e7c48d3155991b99f41372e1786c5be03457 (diff)
Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/linux into mips-for-linux-next
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/Makefile3
-rw-r--r--arch/mips/kernel/asm-offsets.c1
-rw-r--r--arch/mips/kernel/branch.c288
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cps-vec.S16
-rw-r--r--arch/mips/kernel/cpu-bugs64.c11
-rw-r--r--arch/mips/kernel/cpu-probe.c27
-rw-r--r--arch/mips/kernel/elf.c303
-rw-r--r--arch/mips/kernel/entry.S23
-rw-r--r--arch/mips/kernel/genex.S2
-rw-r--r--arch/mips/kernel/idle.c1
-rw-r--r--arch/mips/kernel/mips-r2-to-r6-emul.c2378
-rw-r--r--arch/mips/kernel/mips_ksyms.c2
-rw-r--r--arch/mips/kernel/proc.c8
-rw-r--r--arch/mips/kernel/process.c4
-rw-r--r--arch/mips/kernel/r4k_fpu.S12
-rw-r--r--arch/mips/kernel/r4k_switch.S14
-rw-r--r--arch/mips/kernel/spram.c1
-rw-r--r--arch/mips/kernel/syscall.c2
-rw-r--r--arch/mips/kernel/traps.c41
-rw-r--r--arch/mips/kernel/unaligned.c390
21 files changed, 3334 insertions, 195 deletions
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 92987d1bbe5f..d3d2ff2d76dc 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -52,7 +52,7 @@ obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
52obj-$(CONFIG_MIPS_CMP) += smp-cmp.o 52obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
53obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o 53obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o
54obj-$(CONFIG_MIPS_GIC_IPI) += smp-gic.o 54obj-$(CONFIG_MIPS_GIC_IPI) += smp-gic.o
55obj-$(CONFIG_CPU_MIPSR2) += spram.o 55obj-$(CONFIG_MIPS_SPRAM) += spram.o
56 56
57obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 57obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
58obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o 58obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o
@@ -90,6 +90,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
90obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o 90obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o
91obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o 91obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o
92obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o 92obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o
93obj-$(CONFIG_MIPSR2_TO_R6_EMULATOR) += mips-r2-to-r6-emul.o
93 94
94CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) 95CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
95 96
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index b1d84bd4efb3..7b6c11aa1cae 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -97,6 +97,7 @@ void output_thread_info_defines(void)
97 OFFSET(TI_TP_VALUE, thread_info, tp_value); 97 OFFSET(TI_TP_VALUE, thread_info, tp_value);
98 OFFSET(TI_CPU, thread_info, cpu); 98 OFFSET(TI_CPU, thread_info, cpu);
99 OFFSET(TI_PRE_COUNT, thread_info, preempt_count); 99 OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
100 OFFSET(TI_R2_EMUL_RET, thread_info, r2_emul_return);
100 OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit); 101 OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
101 OFFSET(TI_RESTART_BLOCK, thread_info, restart_block); 102 OFFSET(TI_RESTART_BLOCK, thread_info, restart_block);
102 OFFSET(TI_REGS, thread_info, regs); 103 OFFSET(TI_REGS, thread_info, regs);
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d7d99d601cc..c2e0f45ddf6c 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -16,6 +16,7 @@
16#include <asm/fpu.h> 16#include <asm/fpu.h>
17#include <asm/fpu_emulator.h> 17#include <asm/fpu_emulator.h>
18#include <asm/inst.h> 18#include <asm/inst.h>
19#include <asm/mips-r2-to-r6-emul.h>
19#include <asm/ptrace.h> 20#include <asm/ptrace.h>
20#include <asm/uaccess.h> 21#include <asm/uaccess.h>
21 22
@@ -399,11 +400,21 @@ int __MIPS16e_compute_return_epc(struct pt_regs *regs)
399 * @returns: -EFAULT on error and forces SIGBUS, and on success 400 * @returns: -EFAULT on error and forces SIGBUS, and on success
400 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after 401 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
401 * evaluating the branch. 402 * evaluating the branch.
403 *
404 * MIPS R6 Compact branches and forbidden slots:
405 * Compact branches do not throw exceptions because they do
406 * not have delay slots. The forbidden slot instruction ($PC+4)
407 * is only executed if the branch was not taken. Otherwise the
408 * forbidden slot is skipped entirely. This means that the
409 * only possible reason to be here because of a MIPS R6 compact
410 * branch instruction is that the forbidden slot has thrown one.
411 * In that case the branch was not taken, so the EPC can be safely
412 * set to EPC + 8.
402 */ 413 */
403int __compute_return_epc_for_insn(struct pt_regs *regs, 414int __compute_return_epc_for_insn(struct pt_regs *regs,
404 union mips_instruction insn) 415 union mips_instruction insn)
405{ 416{
406 unsigned int bit, fcr31, dspcontrol; 417 unsigned int bit, fcr31, dspcontrol, reg;
407 long epc = regs->cp0_epc; 418 long epc = regs->cp0_epc;
408 int ret = 0; 419 int ret = 0;
409 420
@@ -417,6 +428,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
417 regs->regs[insn.r_format.rd] = epc + 8; 428 regs->regs[insn.r_format.rd] = epc + 8;
418 /* Fall through */ 429 /* Fall through */
419 case jr_op: 430 case jr_op:
431 if (NO_R6EMU && insn.r_format.func == jr_op)
432 goto sigill_r6;
420 regs->cp0_epc = regs->regs[insn.r_format.rs]; 433 regs->cp0_epc = regs->regs[insn.r_format.rs];
421 break; 434 break;
422 } 435 }
@@ -429,8 +442,10 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
429 */ 442 */
430 case bcond_op: 443 case bcond_op:
431 switch (insn.i_format.rt) { 444 switch (insn.i_format.rt) {
432 case bltz_op:
433 case bltzl_op: 445 case bltzl_op:
446 if (NO_R6EMU)
447 goto sigill_r6;
448 case bltz_op:
434 if ((long)regs->regs[insn.i_format.rs] < 0) { 449 if ((long)regs->regs[insn.i_format.rs] < 0) {
435 epc = epc + 4 + (insn.i_format.simmediate << 2); 450 epc = epc + 4 + (insn.i_format.simmediate << 2);
436 if (insn.i_format.rt == bltzl_op) 451 if (insn.i_format.rt == bltzl_op)
@@ -440,8 +455,10 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
440 regs->cp0_epc = epc; 455 regs->cp0_epc = epc;
441 break; 456 break;
442 457
443 case bgez_op:
444 case bgezl_op: 458 case bgezl_op:
459 if (NO_R6EMU)
460 goto sigill_r6;
461 case bgez_op:
445 if ((long)regs->regs[insn.i_format.rs] >= 0) { 462 if ((long)regs->regs[insn.i_format.rs] >= 0) {
446 epc = epc + 4 + (insn.i_format.simmediate << 2); 463 epc = epc + 4 + (insn.i_format.simmediate << 2);
447 if (insn.i_format.rt == bgezl_op) 464 if (insn.i_format.rt == bgezl_op)
@@ -453,7 +470,29 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
453 470
454 case bltzal_op: 471 case bltzal_op:
455 case bltzall_op: 472 case bltzall_op:
473 if (NO_R6EMU && (insn.i_format.rs ||
474 insn.i_format.rt == bltzall_op)) {
475 ret = -SIGILL;
476 break;
477 }
456 regs->regs[31] = epc + 8; 478 regs->regs[31] = epc + 8;
479 /*
480 * OK we are here either because we hit a NAL
481 * instruction or because we are emulating an
482 * old bltzal{,l} one. Lets figure out what the
483 * case really is.
484 */
485 if (!insn.i_format.rs) {
486 /*
487 * NAL or BLTZAL with rs == 0
488 * Doesn't matter if we are R6 or not. The
489 * result is the same
490 */
491 regs->cp0_epc += 4 +
492 (insn.i_format.simmediate << 2);
493 break;
494 }
495 /* Now do the real thing for non-R6 BLTZAL{,L} */
457 if ((long)regs->regs[insn.i_format.rs] < 0) { 496 if ((long)regs->regs[insn.i_format.rs] < 0) {
458 epc = epc + 4 + (insn.i_format.simmediate << 2); 497 epc = epc + 4 + (insn.i_format.simmediate << 2);
459 if (insn.i_format.rt == bltzall_op) 498 if (insn.i_format.rt == bltzall_op)
@@ -465,7 +504,29 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
465 504
466 case bgezal_op: 505 case bgezal_op:
467 case bgezall_op: 506 case bgezall_op:
507 if (NO_R6EMU && (insn.i_format.rs ||
508 insn.i_format.rt == bgezall_op)) {
509 ret = -SIGILL;
510 break;
511 }
468 regs->regs[31] = epc + 8; 512 regs->regs[31] = epc + 8;
513 /*
514 * OK we are here either because we hit a BAL
515 * instruction or because we are emulating an
516 * old bgezal{,l} one. Lets figure out what the
517 * case really is.
518 */
519 if (!insn.i_format.rs) {
520 /*
521 * BAL or BGEZAL with rs == 0
522 * Doesn't matter if we are R6 or not. The
523 * result is the same
524 */
525 regs->cp0_epc += 4 +
526 (insn.i_format.simmediate << 2);
527 break;
528 }
529 /* Now do the real thing for non-R6 BGEZAL{,L} */
469 if ((long)regs->regs[insn.i_format.rs] >= 0) { 530 if ((long)regs->regs[insn.i_format.rs] >= 0) {
470 epc = epc + 4 + (insn.i_format.simmediate << 2); 531 epc = epc + 4 + (insn.i_format.simmediate << 2);
471 if (insn.i_format.rt == bgezall_op) 532 if (insn.i_format.rt == bgezall_op)
@@ -477,7 +538,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
477 538
478 case bposge32_op: 539 case bposge32_op:
479 if (!cpu_has_dsp) 540 if (!cpu_has_dsp)
480 goto sigill; 541 goto sigill_dsp;
481 542
482 dspcontrol = rddsp(0x01); 543 dspcontrol = rddsp(0x01);
483 544
@@ -508,8 +569,10 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
508 /* 569 /*
509 * These are conditional and in i_format. 570 * These are conditional and in i_format.
510 */ 571 */
511 case beq_op:
512 case beql_op: 572 case beql_op:
573 if (NO_R6EMU)
574 goto sigill_r6;
575 case beq_op:
513 if (regs->regs[insn.i_format.rs] == 576 if (regs->regs[insn.i_format.rs] ==
514 regs->regs[insn.i_format.rt]) { 577 regs->regs[insn.i_format.rt]) {
515 epc = epc + 4 + (insn.i_format.simmediate << 2); 578 epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -520,8 +583,10 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
520 regs->cp0_epc = epc; 583 regs->cp0_epc = epc;
521 break; 584 break;
522 585
523 case bne_op:
524 case bnel_op: 586 case bnel_op:
587 if (NO_R6EMU)
588 goto sigill_r6;
589 case bne_op:
525 if (regs->regs[insn.i_format.rs] != 590 if (regs->regs[insn.i_format.rs] !=
526 regs->regs[insn.i_format.rt]) { 591 regs->regs[insn.i_format.rt]) {
527 epc = epc + 4 + (insn.i_format.simmediate << 2); 592 epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -532,8 +597,31 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
532 regs->cp0_epc = epc; 597 regs->cp0_epc = epc;
533 break; 598 break;
534 599
535 case blez_op: /* not really i_format */ 600 case blezl_op: /* not really i_format */
536 case blezl_op: 601 if (NO_R6EMU)
602 goto sigill_r6;
603 case blez_op:
604 /*
605 * Compact branches for R6 for the
606 * blez and blezl opcodes.
607 * BLEZ | rs = 0 | rt != 0 == BLEZALC
608 * BLEZ | rs = rt != 0 == BGEZALC
609 * BLEZ | rs != 0 | rt != 0 == BGEUC
610 * BLEZL | rs = 0 | rt != 0 == BLEZC
611 * BLEZL | rs = rt != 0 == BGEZC
612 * BLEZL | rs != 0 | rt != 0 == BGEC
613 *
614 * For real BLEZ{,L}, rt is always 0.
615 */
616
617 if (cpu_has_mips_r6 && insn.i_format.rt) {
618 if ((insn.i_format.opcode == blez_op) &&
619 ((!insn.i_format.rs && insn.i_format.rt) ||
620 (insn.i_format.rs == insn.i_format.rt)))
621 regs->regs[31] = epc + 4;
622 regs->cp0_epc += 8;
623 break;
624 }
537 /* rt field assumed to be zero */ 625 /* rt field assumed to be zero */
538 if ((long)regs->regs[insn.i_format.rs] <= 0) { 626 if ((long)regs->regs[insn.i_format.rs] <= 0) {
539 epc = epc + 4 + (insn.i_format.simmediate << 2); 627 epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -544,8 +632,32 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
544 regs->cp0_epc = epc; 632 regs->cp0_epc = epc;
545 break; 633 break;
546 634
547 case bgtz_op:
548 case bgtzl_op: 635 case bgtzl_op:
636 if (NO_R6EMU)
637 goto sigill_r6;
638 case bgtz_op:
639 /*
640 * Compact branches for R6 for the
641 * bgtz and bgtzl opcodes.
642 * BGTZ | rs = 0 | rt != 0 == BGTZALC
643 * BGTZ | rs = rt != 0 == BLTZALC
644 * BGTZ | rs != 0 | rt != 0 == BLTUC
645 * BGTZL | rs = 0 | rt != 0 == BGTZC
646 * BGTZL | rs = rt != 0 == BLTZC
647 * BGTZL | rs != 0 | rt != 0 == BLTC
648 *
649 * *ZALC varint for BGTZ &&& rt != 0
650 * For real GTZ{,L}, rt is always 0.
651 */
652 if (cpu_has_mips_r6 && insn.i_format.rt) {
653 if ((insn.i_format.opcode == blez_op) &&
654 ((!insn.i_format.rs && insn.i_format.rt) ||
655 (insn.i_format.rs == insn.i_format.rt)))
656 regs->regs[31] = epc + 4;
657 regs->cp0_epc += 8;
658 break;
659 }
660
549 /* rt field assumed to be zero */ 661 /* rt field assumed to be zero */
550 if ((long)regs->regs[insn.i_format.rs] > 0) { 662 if ((long)regs->regs[insn.i_format.rs] > 0) {
551 epc = epc + 4 + (insn.i_format.simmediate << 2); 663 epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -560,40 +672,83 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
560 * And now the FPA/cp1 branch instructions. 672 * And now the FPA/cp1 branch instructions.
561 */ 673 */
562 case cop1_op: 674 case cop1_op:
563 preempt_disable(); 675 if (cpu_has_mips_r6 &&
564 if (is_fpu_owner()) 676 ((insn.i_format.rs == bc1eqz_op) ||
565 fcr31 = read_32bit_cp1_register(CP1_STATUS); 677 (insn.i_format.rs == bc1nez_op))) {
566 else 678 if (!used_math()) { /* First time FPU user */
567 fcr31 = current->thread.fpu.fcr31; 679 ret = init_fpu();
568 preempt_enable(); 680 if (ret && NO_R6EMU) {
569 681 ret = -ret;
570 bit = (insn.i_format.rt >> 2); 682 break;
571 bit += (bit != 0); 683 }
572 bit += 23; 684 ret = 0;
573 switch (insn.i_format.rt & 3) { 685 set_used_math();
574 case 0: /* bc1f */ 686 }
575 case 2: /* bc1fl */ 687 lose_fpu(1); /* Save FPU state for the emulator. */
576 if (~fcr31 & (1 << bit)) { 688 reg = insn.i_format.rt;
577 epc = epc + 4 + (insn.i_format.simmediate << 2); 689 bit = 0;
578 if (insn.i_format.rt == 2) 690 switch (insn.i_format.rs) {
579 ret = BRANCH_LIKELY_TAKEN; 691 case bc1eqz_op:
580 } else 692 /* Test bit 0 */
693 if (get_fpr32(&current->thread.fpu.fpr[reg], 0)
694 & 0x1)
695 bit = 1;
696 break;
697 case bc1nez_op:
698 /* Test bit 0 */
699 if (!(get_fpr32(&current->thread.fpu.fpr[reg], 0)
700 & 0x1))
701 bit = 1;
702 break;
703 }
704 own_fpu(1);
705 if (bit)
706 epc = epc + 4 +
707 (insn.i_format.simmediate << 2);
708 else
581 epc += 8; 709 epc += 8;
582 regs->cp0_epc = epc; 710 regs->cp0_epc = epc;
711
583 break; 712 break;
713 } else {
584 714
585 case 1: /* bc1t */ 715 preempt_disable();
586 case 3: /* bc1tl */ 716 if (is_fpu_owner())
587 if (fcr31 & (1 << bit)) { 717 fcr31 = read_32bit_cp1_register(CP1_STATUS);
588 epc = epc + 4 + (insn.i_format.simmediate << 2); 718 else
589 if (insn.i_format.rt == 3) 719 fcr31 = current->thread.fpu.fcr31;
590 ret = BRANCH_LIKELY_TAKEN; 720 preempt_enable();
591 } else 721
592 epc += 8; 722 bit = (insn.i_format.rt >> 2);
593 regs->cp0_epc = epc; 723 bit += (bit != 0);
724 bit += 23;
725 switch (insn.i_format.rt & 3) {
726 case 0: /* bc1f */
727 case 2: /* bc1fl */
728 if (~fcr31 & (1 << bit)) {
729 epc = epc + 4 +
730 (insn.i_format.simmediate << 2);
731 if (insn.i_format.rt == 2)
732 ret = BRANCH_LIKELY_TAKEN;
733 } else
734 epc += 8;
735 regs->cp0_epc = epc;
736 break;
737
738 case 1: /* bc1t */
739 case 3: /* bc1tl */
740 if (fcr31 & (1 << bit)) {
741 epc = epc + 4 +
742 (insn.i_format.simmediate << 2);
743 if (insn.i_format.rt == 3)
744 ret = BRANCH_LIKELY_TAKEN;
745 } else
746 epc += 8;
747 regs->cp0_epc = epc;
748 break;
749 }
594 break; 750 break;
595 } 751 }
596 break;
597#ifdef CONFIG_CPU_CAVIUM_OCTEON 752#ifdef CONFIG_CPU_CAVIUM_OCTEON
598 case lwc2_op: /* This is bbit0 on Octeon */ 753 case lwc2_op: /* This is bbit0 on Octeon */
599 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 754 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
@@ -626,15 +781,72 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
626 epc += 8; 781 epc += 8;
627 regs->cp0_epc = epc; 782 regs->cp0_epc = epc;
628 break; 783 break;
784#else
785 case bc6_op:
786 /* Only valid for MIPS R6 */
787 if (!cpu_has_mips_r6) {
788 ret = -SIGILL;
789 break;
790 }
791 regs->cp0_epc += 8;
792 break;
793 case balc6_op:
794 if (!cpu_has_mips_r6) {
795 ret = -SIGILL;
796 break;
797 }
798 /* Compact branch: BALC */
799 regs->regs[31] = epc + 4;
800 epc += 4 + (insn.i_format.simmediate << 2);
801 regs->cp0_epc = epc;
802 break;
803 case beqzcjic_op:
804 if (!cpu_has_mips_r6) {
805 ret = -SIGILL;
806 break;
807 }
808 /* Compact branch: BEQZC || JIC */
809 regs->cp0_epc += 8;
810 break;
811 case bnezcjialc_op:
812 if (!cpu_has_mips_r6) {
813 ret = -SIGILL;
814 break;
815 }
816 /* Compact branch: BNEZC || JIALC */
817 if (insn.i_format.rs)
818 regs->regs[31] = epc + 4;
819 regs->cp0_epc += 8;
820 break;
629#endif 821#endif
822 case cbcond0_op:
823 case cbcond1_op:
824 /* Only valid for MIPS R6 */
825 if (!cpu_has_mips_r6) {
826 ret = -SIGILL;
827 break;
828 }
829 /*
830 * Compact branches:
831 * bovc, beqc, beqzalc, bnvc, bnec, bnezlac
832 */
833 if (insn.i_format.rt && !insn.i_format.rs)
834 regs->regs[31] = epc + 4;
835 regs->cp0_epc += 8;
836 break;
630 } 837 }
631 838
632 return ret; 839 return ret;
633 840
634sigill: 841sigill_dsp:
635 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); 842 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
636 force_sig(SIGBUS, current); 843 force_sig(SIGBUS, current);
637 return -EFAULT; 844 return -EFAULT;
845sigill_r6:
846 pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n",
847 current->comm);
848 force_sig(SIGILL, current);
849 return -EFAULT;
638} 850}
639EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn); 851EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
640 852
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 28bfdf2c59a5..82bd2b278a24 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -39,7 +39,7 @@ int cp0_timer_irq_installed;
39 39
40irqreturn_t c0_compare_interrupt(int irq, void *dev_id) 40irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
41{ 41{
42 const int r2 = cpu_has_mips_r2; 42 const int r2 = cpu_has_mips_r2_r6;
43 struct clock_event_device *cd; 43 struct clock_event_device *cd;
44 int cpu = smp_processor_id(); 44 int cpu = smp_processor_id();
45 45
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 0384b05ab5a0..55b759a0019e 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -99,11 +99,11 @@ not_nmi:
99 xori t2, t1, 0x7 99 xori t2, t1, 0x7
100 beqz t2, 1f 100 beqz t2, 1f
101 li t3, 32 101 li t3, 32
102 addi t1, t1, 1 102 addiu t1, t1, 1
103 sllv t1, t3, t1 103 sllv t1, t3, t1
1041: /* At this point t1 == I-cache sets per way */ 1041: /* At this point t1 == I-cache sets per way */
105 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ 105 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
106 addi t2, t2, 1 106 addiu t2, t2, 1
107 mul t1, t1, t0 107 mul t1, t1, t0
108 mul t1, t1, t2 108 mul t1, t1, t2
109 109
@@ -126,11 +126,11 @@ icache_done:
126 xori t2, t1, 0x7 126 xori t2, t1, 0x7
127 beqz t2, 1f 127 beqz t2, 1f
128 li t3, 32 128 li t3, 32
129 addi t1, t1, 1 129 addiu t1, t1, 1
130 sllv t1, t3, t1 130 sllv t1, t3, t1
1311: /* At this point t1 == D-cache sets per way */ 1311: /* At this point t1 == D-cache sets per way */
132 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ 132 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
133 addi t2, t2, 1 133 addiu t2, t2, 1
134 mul t1, t1, t0 134 mul t1, t1, t0
135 mul t1, t1, t2 135 mul t1, t1, t2
136 136
@@ -250,7 +250,7 @@ LEAF(mips_cps_core_init)
250 mfc0 t0, CP0_MVPCONF0 250 mfc0 t0, CP0_MVPCONF0
251 srl t0, t0, MVPCONF0_PVPE_SHIFT 251 srl t0, t0, MVPCONF0_PVPE_SHIFT
252 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT) 252 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
253 addi t7, t0, 1 253 addiu t7, t0, 1
254 254
255 /* If there's only 1, we're done */ 255 /* If there's only 1, we're done */
256 beqz t0, 2f 256 beqz t0, 2f
@@ -280,7 +280,7 @@ LEAF(mips_cps_core_init)
280 mttc0 t0, CP0_TCHALT 280 mttc0 t0, CP0_TCHALT
281 281
282 /* Next VPE */ 282 /* Next VPE */
283 addi t5, t5, 1 283 addiu t5, t5, 1
284 slt t0, t5, t7 284 slt t0, t5, t7
285 bnez t0, 1b 285 bnez t0, 1b
286 nop 286 nop
@@ -317,7 +317,7 @@ LEAF(mips_cps_boot_vpes)
317 mfc0 t1, CP0_MVPCONF0 317 mfc0 t1, CP0_MVPCONF0
318 srl t1, t1, MVPCONF0_PVPE_SHIFT 318 srl t1, t1, MVPCONF0_PVPE_SHIFT
319 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT 319 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
320 addi t1, t1, 1 320 addiu t1, t1, 1
321 321
322 /* Calculate a mask for the VPE ID from EBase.CPUNum */ 322 /* Calculate a mask for the VPE ID from EBase.CPUNum */
323 clz t1, t1 323 clz t1, t1
@@ -424,7 +424,7 @@ LEAF(mips_cps_boot_vpes)
424 424
425 /* Next VPE */ 425 /* Next VPE */
4262: srl t6, t6, 1 4262: srl t6, t6, 1
427 addi t5, t5, 1 427 addiu t5, t5, 1
428 bnez t6, 1b 428 bnez t6, 1b
429 nop 429 nop
430 430
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 2d80b5f1aeae..09f4034f239f 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -244,7 +244,7 @@ static inline void check_daddi(void)
244 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); 244 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
245} 245}
246 246
247int daddiu_bug = -1; 247int daddiu_bug = config_enabled(CONFIG_CPU_MIPSR6) ? 0 : -1;
248 248
249static inline void check_daddiu(void) 249static inline void check_daddiu(void)
250{ 250{
@@ -314,11 +314,14 @@ static inline void check_daddiu(void)
314 314
315void __init check_bugs64_early(void) 315void __init check_bugs64_early(void)
316{ 316{
317 check_mult_sh(); 317 if (!config_enabled(CONFIG_CPU_MIPSR6)) {
318 check_daddiu(); 318 check_mult_sh();
319 check_daddiu();
320 }
319} 321}
320 322
321void __init check_bugs64(void) 323void __init check_bugs64(void)
322{ 324{
323 check_daddi(); 325 if (!config_enabled(CONFIG_CPU_MIPSR6))
326 check_daddi();
324} 327}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 228ae864c92e..81f0aedbba0f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -237,6 +237,13 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
238 break; 238 break;
239 239
240 /* R6 incompatible with everything else */
241 case MIPS_CPU_ISA_M64R6:
242 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
243 case MIPS_CPU_ISA_M32R6:
244 c->isa_level |= MIPS_CPU_ISA_M32R6;
245 /* Break here so we don't add incompatible ISAs */
246 break;
240 case MIPS_CPU_ISA_M32R2: 247 case MIPS_CPU_ISA_M32R2:
241 c->isa_level |= MIPS_CPU_ISA_M32R2; 248 c->isa_level |= MIPS_CPU_ISA_M32R2;
242 case MIPS_CPU_ISA_M32R1: 249 case MIPS_CPU_ISA_M32R1:
@@ -326,6 +333,9 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
326 case 1: 333 case 1:
327 set_isa(c, MIPS_CPU_ISA_M32R2); 334 set_isa(c, MIPS_CPU_ISA_M32R2);
328 break; 335 break;
336 case 2:
337 set_isa(c, MIPS_CPU_ISA_M32R6);
338 break;
329 default: 339 default:
330 goto unknown; 340 goto unknown;
331 } 341 }
@@ -338,6 +348,9 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
338 case 1: 348 case 1:
339 set_isa(c, MIPS_CPU_ISA_M64R2); 349 set_isa(c, MIPS_CPU_ISA_M64R2);
340 break; 350 break;
351 case 2:
352 set_isa(c, MIPS_CPU_ISA_M64R6);
353 break;
341 default: 354 default:
342 goto unknown; 355 goto unknown;
343 } 356 }
@@ -501,6 +514,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
501 c->options |= MIPS_CPU_EVA; 514 c->options |= MIPS_CPU_EVA;
502 if (config5 & MIPS_CONF5_MRP) 515 if (config5 & MIPS_CONF5_MRP)
503 c->options |= MIPS_CPU_MAAR; 516 c->options |= MIPS_CPU_MAAR;
517 if (config5 & MIPS_CONF5_LLB)
518 c->options |= MIPS_CPU_RW_LLB;
504 519
505 return config5 & MIPS_CONF_M; 520 return config5 & MIPS_CONF_M;
506} 521}
@@ -543,7 +558,7 @@ static void decode_configs(struct cpuinfo_mips *c)
543 } 558 }
544 559
545#ifndef CONFIG_MIPS_CPS 560#ifndef CONFIG_MIPS_CPS
546 if (cpu_has_mips_r2) { 561 if (cpu_has_mips_r2_r6) {
547 c->core = get_ebase_cpunum(); 562 c->core = get_ebase_cpunum();
548 if (cpu_has_mipsmt) 563 if (cpu_has_mipsmt)
549 c->core >>= fls(core_nvpes()) - 1; 564 c->core >>= fls(core_nvpes()) - 1;
@@ -898,6 +913,11 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
898{ 913{
899 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 914 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
900 switch (c->processor_id & PRID_IMP_MASK) { 915 switch (c->processor_id & PRID_IMP_MASK) {
916 case PRID_IMP_QEMU_GENERIC:
917 c->writecombine = _CACHE_UNCACHED;
918 c->cputype = CPU_QEMU_GENERIC;
919 __cpu_name[cpu] = "MIPS GENERIC QEMU";
920 break;
901 case PRID_IMP_4KC: 921 case PRID_IMP_4KC:
902 c->cputype = CPU_4KC; 922 c->cputype = CPU_4KC;
903 c->writecombine = _CACHE_UNCACHED; 923 c->writecombine = _CACHE_UNCACHED;
@@ -1347,8 +1367,7 @@ void cpu_probe(void)
1347 if (c->options & MIPS_CPU_FPU) { 1367 if (c->options & MIPS_CPU_FPU) {
1348 c->fpu_id = cpu_get_fpu_id(); 1368 c->fpu_id = cpu_get_fpu_id();
1349 1369
1350 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1370 if (c->isa_level & cpu_has_mips_r) {
1351 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1352 if (c->fpu_id & MIPS_FPIR_3D) 1371 if (c->fpu_id & MIPS_FPIR_3D)
1353 c->ases |= MIPS_ASE_MIPS3D; 1372 c->ases |= MIPS_ASE_MIPS3D;
1354 if (c->fpu_id & MIPS_FPIR_FREP) 1373 if (c->fpu_id & MIPS_FPIR_FREP)
@@ -1356,7 +1375,7 @@ void cpu_probe(void)
1356 } 1375 }
1357 } 1376 }
1358 1377
1359 if (cpu_has_mips_r2) { 1378 if (cpu_has_mips_r2_r6) {
1360 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1379 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1361 /* R2 has Performance Counter Interrupt indicator */ 1380 /* R2 has Performance Counter Interrupt indicator */
1362 c->options |= MIPS_CPU_PCI; 1381 c->options |= MIPS_CPU_PCI;
diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c
index c92b15df6893..d2c09f6475c5 100644
--- a/arch/mips/kernel/elf.c
+++ b/arch/mips/kernel/elf.c
@@ -11,29 +11,112 @@
11#include <linux/elf.h> 11#include <linux/elf.h>
12#include <linux/sched.h> 12#include <linux/sched.h>
13 13
14/* FPU modes */
14enum { 15enum {
15 FP_ERROR = -1, 16 FP_FRE,
16 FP_DOUBLE_64A = -2, 17 FP_FR0,
18 FP_FR1,
17}; 19};
18 20
21/**
22 * struct mode_req - ABI FPU mode requirements
23 * @single: The program being loaded needs an FPU but it will only issue
24 * single precision instructions meaning that it can execute in
25 * either FR0 or FR1.
26 * @soft: The soft(-float) requirement means that the program being
27 * loaded needs has no FPU dependency at all (i.e. it has no
28 * FPU instructions).
29 * @fr1: The program being loaded depends on FPU being in FR=1 mode.
30 * @frdefault: The program being loaded depends on the default FPU mode.
31 * That is FR0 for O32 and FR1 for N32/N64.
32 * @fre: The program being loaded depends on FPU with FRE=1. This mode is
33 * a bridge which uses FR=1 whilst still being able to maintain
34 * full compatibility with pre-existing code using the O32 FP32
35 * ABI.
36 *
37 * More information about the FP ABIs can be found here:
38 *
39 * https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#10.4.1._Basic_mode_set-up
40 *
41 */
42
43struct mode_req {
44 bool single;
45 bool soft;
46 bool fr1;
47 bool frdefault;
48 bool fre;
49};
50
51static const struct mode_req fpu_reqs[] = {
52 [MIPS_ABI_FP_ANY] = { true, true, true, true, true },
53 [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
54 [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
55 [MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
56 [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
57 [MIPS_ABI_FP_XX] = { false, false, true, true, true },
58 [MIPS_ABI_FP_64] = { false, false, true, false, false },
59 [MIPS_ABI_FP_64A] = { false, false, true, false, true }
60};
61
62/*
63 * Mode requirements when .MIPS.abiflags is not present in the ELF.
64 * Not present means that everything is acceptable except FR1.
65 */
66static struct mode_req none_req = { true, true, false, true, true };
67
19int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf, 68int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
20 bool is_interp, struct arch_elf_state *state) 69 bool is_interp, struct arch_elf_state *state)
21{ 70{
22 struct elfhdr *ehdr = _ehdr; 71 struct elf32_hdr *ehdr32 = _ehdr;
23 struct elf_phdr *phdr = _phdr; 72 struct elf32_phdr *phdr32 = _phdr;
73 struct elf64_phdr *phdr64 = _phdr;
24 struct mips_elf_abiflags_v0 abiflags; 74 struct mips_elf_abiflags_v0 abiflags;
25 int ret; 75 int ret;
26 76
27 if (config_enabled(CONFIG_64BIT) && 77 /* Lets see if this is an O32 ELF */
28 (ehdr->e_ident[EI_CLASS] != ELFCLASS32)) 78 if (ehdr32->e_ident[EI_CLASS] == ELFCLASS32) {
29 return 0; 79 /* FR = 1 for N32 */
30 if (phdr->p_type != PT_MIPS_ABIFLAGS) 80 if (ehdr32->e_flags & EF_MIPS_ABI2)
31 return 0; 81 state->overall_fp_mode = FP_FR1;
32 if (phdr->p_filesz < sizeof(abiflags)) 82 else
33 return -EINVAL; 83 /* Set a good default FPU mode for O32 */
84 state->overall_fp_mode = cpu_has_mips_r6 ?
85 FP_FRE : FP_FR0;
86
87 if (ehdr32->e_flags & EF_MIPS_FP64) {
88 /*
89 * Set MIPS_ABI_FP_OLD_64 for EF_MIPS_FP64. We will override it
90 * later if needed
91 */
92 if (is_interp)
93 state->interp_fp_abi = MIPS_ABI_FP_OLD_64;
94 else
95 state->fp_abi = MIPS_ABI_FP_OLD_64;
96 }
97 if (phdr32->p_type != PT_MIPS_ABIFLAGS)
98 return 0;
99
100 if (phdr32->p_filesz < sizeof(abiflags))
101 return -EINVAL;
102
103 ret = kernel_read(elf, phdr32->p_offset,
104 (char *)&abiflags,
105 sizeof(abiflags));
106 } else {
107 /* FR=1 is really the only option for 64-bit */
108 state->overall_fp_mode = FP_FR1;
109
110 if (phdr64->p_type != PT_MIPS_ABIFLAGS)
111 return 0;
112 if (phdr64->p_filesz < sizeof(abiflags))
113 return -EINVAL;
114
115 ret = kernel_read(elf, phdr64->p_offset,
116 (char *)&abiflags,
117 sizeof(abiflags));
118 }
34 119
35 ret = kernel_read(elf, phdr->p_offset, (char *)&abiflags,
36 sizeof(abiflags));
37 if (ret < 0) 120 if (ret < 0)
38 return ret; 121 return ret;
39 if (ret != sizeof(abiflags)) 122 if (ret != sizeof(abiflags))
@@ -48,35 +131,30 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
48 return 0; 131 return 0;
49} 132}
50 133
51static inline unsigned get_fp_abi(struct elfhdr *ehdr, int in_abi) 134static inline unsigned get_fp_abi(int in_abi)
52{ 135{
53 /* If the ABI requirement is provided, simply return that */ 136 /* If the ABI requirement is provided, simply return that */
54 if (in_abi != -1) 137 if (in_abi != MIPS_ABI_FP_UNKNOWN)
55 return in_abi; 138 return in_abi;
56 139
57 /* If the EF_MIPS_FP64 flag was set, return MIPS_ABI_FP_64 */ 140 /* Unknown ABI */
58 if (ehdr->e_flags & EF_MIPS_FP64) 141 return MIPS_ABI_FP_UNKNOWN;
59 return MIPS_ABI_FP_64;
60
61 /* Default to MIPS_ABI_FP_DOUBLE */
62 return MIPS_ABI_FP_DOUBLE;
63} 142}
64 143
65int arch_check_elf(void *_ehdr, bool has_interpreter, 144int arch_check_elf(void *_ehdr, bool has_interpreter,
66 struct arch_elf_state *state) 145 struct arch_elf_state *state)
67{ 146{
68 struct elfhdr *ehdr = _ehdr; 147 struct elf32_hdr *ehdr = _ehdr;
69 unsigned fp_abi, interp_fp_abi, abi0, abi1; 148 struct mode_req prog_req, interp_req;
149 int fp_abi, interp_fp_abi, abi0, abi1, max_abi;
70 150
71 /* Ignore non-O32 binaries */ 151 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
72 if (config_enabled(CONFIG_64BIT) &&
73 (ehdr->e_ident[EI_CLASS] != ELFCLASS32))
74 return 0; 152 return 0;
75 153
76 fp_abi = get_fp_abi(ehdr, state->fp_abi); 154 fp_abi = get_fp_abi(state->fp_abi);
77 155
78 if (has_interpreter) { 156 if (has_interpreter) {
79 interp_fp_abi = get_fp_abi(ehdr, state->interp_fp_abi); 157 interp_fp_abi = get_fp_abi(state->interp_fp_abi);
80 158
81 abi0 = min(fp_abi, interp_fp_abi); 159 abi0 = min(fp_abi, interp_fp_abi);
82 abi1 = max(fp_abi, interp_fp_abi); 160 abi1 = max(fp_abi, interp_fp_abi);
@@ -84,108 +162,103 @@ int arch_check_elf(void *_ehdr, bool has_interpreter,
84 abi0 = abi1 = fp_abi; 162 abi0 = abi1 = fp_abi;
85 } 163 }
86 164
87 state->overall_abi = FP_ERROR; 165 /* ABI limits. O32 = FP_64A, N32/N64 = FP_SOFT */
88 166 max_abi = ((ehdr->e_ident[EI_CLASS] == ELFCLASS32) &&
89 if (abi0 == abi1) { 167 (!(ehdr->e_flags & EF_MIPS_ABI2))) ?
90 state->overall_abi = abi0; 168 MIPS_ABI_FP_64A : MIPS_ABI_FP_SOFT;
91 } else if (abi0 == MIPS_ABI_FP_ANY) {
92 state->overall_abi = abi1;
93 } else if (abi0 == MIPS_ABI_FP_DOUBLE) {
94 switch (abi1) {
95 case MIPS_ABI_FP_XX:
96 state->overall_abi = MIPS_ABI_FP_DOUBLE;
97 break;
98
99 case MIPS_ABI_FP_64A:
100 state->overall_abi = FP_DOUBLE_64A;
101 break;
102 }
103 } else if (abi0 == MIPS_ABI_FP_SINGLE ||
104 abi0 == MIPS_ABI_FP_SOFT) {
105 /* Cannot link with other ABIs */
106 } else if (abi0 == MIPS_ABI_FP_OLD_64) {
107 switch (abi1) {
108 case MIPS_ABI_FP_XX:
109 case MIPS_ABI_FP_64:
110 case MIPS_ABI_FP_64A:
111 state->overall_abi = MIPS_ABI_FP_64;
112 break;
113 }
114 } else if (abi0 == MIPS_ABI_FP_XX ||
115 abi0 == MIPS_ABI_FP_64 ||
116 abi0 == MIPS_ABI_FP_64A) {
117 state->overall_abi = MIPS_ABI_FP_64;
118 }
119 169
120 switch (state->overall_abi) { 170 if ((abi0 > max_abi && abi0 != MIPS_ABI_FP_UNKNOWN) ||
121 case MIPS_ABI_FP_64: 171 (abi1 > max_abi && abi1 != MIPS_ABI_FP_UNKNOWN))
122 case MIPS_ABI_FP_64A: 172 return -ELIBBAD;
123 case FP_DOUBLE_64A: 173
124 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 174 /* It's time to determine the FPU mode requirements */
125 return -ELIBBAD; 175 prog_req = (abi0 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi0];
126 break; 176 interp_req = (abi1 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi1];
127 177
128 case FP_ERROR: 178 /*
179 * Check whether the program's and interp's ABIs have a matching FPU
180 * mode requirement.
181 */
182 prog_req.single = interp_req.single && prog_req.single;
183 prog_req.soft = interp_req.soft && prog_req.soft;
184 prog_req.fr1 = interp_req.fr1 && prog_req.fr1;
185 prog_req.frdefault = interp_req.frdefault && prog_req.frdefault;
186 prog_req.fre = interp_req.fre && prog_req.fre;
187
188 /*
189 * Determine the desired FPU mode
190 *
191 * Decision making:
192 *
193 * - We want FR_FRE if FRE=1 and both FR=1 and FR=0 are false. This
194 * means that we have a combination of program and interpreter
195 * that inherently require the hybrid FP mode.
196 * - If FR1 and FRDEFAULT is true, that means we hit the any-abi or
197 * fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU
198 * instructions so we don't care about the mode. We will simply use
199 * the one preferred by the hardware. In fpxx case, that ABI can
200 * handle both FR=1 and FR=0, so, again, we simply choose the one
201 * preferred by the hardware. Next, if we only use single-precision
202 * FPU instructions, and the default ABI FPU mode is not good
203 * (ie single + any ABI combination), we set again the FPU mode to the
204 * one is preferred by the hardware. Next, if we know that the code
205 * will only use single-precision instructions, shown by single being
206 * true but frdefault being false, then we again set the FPU mode to
207 * the one that is preferred by the hardware.
208 * - We want FP_FR1 if that's the only matching mode and the default one
209 * is not good.
210 * - Return with -ELIBADD if we can't find a matching FPU mode.
211 */
212 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1)
213 state->overall_fp_mode = FP_FRE;
214 else if ((prog_req.fr1 && prog_req.frdefault) ||
215 (prog_req.single && !prog_req.frdefault))
216 /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */
217 state->overall_fp_mode = ((current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
218 cpu_has_mips_r2_r6) ?
219 FP_FR1 : FP_FR0;
220 else if (prog_req.fr1)
221 state->overall_fp_mode = FP_FR1;
222 else if (!prog_req.fre && !prog_req.frdefault &&
223 !prog_req.fr1 && !prog_req.single && !prog_req.soft)
129 return -ELIBBAD; 224 return -ELIBBAD;
130 }
131 225
132 return 0; 226 return 0;
133} 227}
134 228
135void mips_set_personality_fp(struct arch_elf_state *state) 229static inline void set_thread_fp_mode(int hybrid, int regs32)
136{ 230{
137 if (config_enabled(CONFIG_FP32XX_HYBRID_FPRS)) { 231 if (hybrid)
138 /* 232 set_thread_flag(TIF_HYBRID_FPREGS);
139 * Use hybrid FPRs for all code which can correctly execute 233 else
140 * with that mode.
141 */
142 switch (state->overall_abi) {
143 case MIPS_ABI_FP_DOUBLE:
144 case MIPS_ABI_FP_SINGLE:
145 case MIPS_ABI_FP_SOFT:
146 case MIPS_ABI_FP_XX:
147 case MIPS_ABI_FP_ANY:
148 /* FR=1, FRE=1 */
149 clear_thread_flag(TIF_32BIT_FPREGS);
150 set_thread_flag(TIF_HYBRID_FPREGS);
151 return;
152 }
153 }
154
155 switch (state->overall_abi) {
156 case MIPS_ABI_FP_DOUBLE:
157 case MIPS_ABI_FP_SINGLE:
158 case MIPS_ABI_FP_SOFT:
159 /* FR=0 */
160 set_thread_flag(TIF_32BIT_FPREGS);
161 clear_thread_flag(TIF_HYBRID_FPREGS); 234 clear_thread_flag(TIF_HYBRID_FPREGS);
162 break; 235 if (regs32)
163 236 set_thread_flag(TIF_32BIT_FPREGS);
164 case FP_DOUBLE_64A: 237 else
165 /* FR=1, FRE=1 */
166 clear_thread_flag(TIF_32BIT_FPREGS); 238 clear_thread_flag(TIF_32BIT_FPREGS);
167 set_thread_flag(TIF_HYBRID_FPREGS); 239}
168 break;
169 240
170 case MIPS_ABI_FP_64: 241void mips_set_personality_fp(struct arch_elf_state *state)
171 case MIPS_ABI_FP_64A: 242{
172 /* FR=1, FRE=0 */ 243 /*
173 clear_thread_flag(TIF_32BIT_FPREGS); 244 * This function is only ever called for O32 ELFs so we should
174 clear_thread_flag(TIF_HYBRID_FPREGS); 245 * not be worried about N32/N64 binaries.
175 break; 246 */
176 247
177 case MIPS_ABI_FP_XX: 248 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
178 case MIPS_ABI_FP_ANY: 249 return;
179 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
180 set_thread_flag(TIF_32BIT_FPREGS);
181 else
182 clear_thread_flag(TIF_32BIT_FPREGS);
183 250
184 clear_thread_flag(TIF_HYBRID_FPREGS); 251 switch (state->overall_fp_mode) {
252 case FP_FRE:
253 set_thread_fp_mode(1, 0);
254 break;
255 case FP_FR0:
256 set_thread_fp_mode(0, 1);
257 break;
258 case FP_FR1:
259 set_thread_fp_mode(0, 0);
185 break; 260 break;
186
187 default: 261 default:
188 case FP_ERROR:
189 BUG(); 262 BUG();
190 } 263 }
191} 264}
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 4353d323f017..af41ba6db960 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -46,6 +46,11 @@ resume_userspace:
46 local_irq_disable # make sure we dont miss an 46 local_irq_disable # make sure we dont miss an
47 # interrupt setting need_resched 47 # interrupt setting need_resched
48 # between sampling and return 48 # between sampling and return
49#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR
50 lw k0, TI_R2_EMUL_RET($28)
51 bnez k0, restore_all_from_r2_emul
52#endif
53
49 LONG_L a2, TI_FLAGS($28) # current->work 54 LONG_L a2, TI_FLAGS($28) # current->work
50 andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace) 55 andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace)
51 bnez t0, work_pending 56 bnez t0, work_pending
@@ -114,6 +119,19 @@ restore_partial: # restore partial frame
114 RESTORE_SP_AND_RET 119 RESTORE_SP_AND_RET
115 .set at 120 .set at
116 121
122#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR
123restore_all_from_r2_emul: # restore full frame
124 .set noat
125 sw zero, TI_R2_EMUL_RET($28) # reset it
126 RESTORE_TEMP
127 RESTORE_AT
128 RESTORE_STATIC
129 RESTORE_SOME
130 LONG_L sp, PT_R29(sp)
131 eretnc
132 .set at
133#endif
134
117work_pending: 135work_pending:
118 andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS 136 andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS
119 beqz t0, work_notifysig 137 beqz t0, work_notifysig
@@ -158,7 +176,8 @@ syscall_exit_work:
158 jal syscall_trace_leave 176 jal syscall_trace_leave
159 b resume_userspace 177 b resume_userspace
160 178
161#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT) 179#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) || \
180 defined(CONFIG_MIPS_MT)
162 181
163/* 182/*
164 * MIPS32R2 Instruction Hazard Barrier - must be called 183 * MIPS32R2 Instruction Hazard Barrier - must be called
@@ -171,4 +190,4 @@ LEAF(mips_ihb)
171 nop 190 nop
172 END(mips_ihb) 191 END(mips_ihb)
173 192
174#endif /* CONFIG_CPU_MIPSR2 or CONFIG_MIPS_MT */ 193#endif /* CONFIG_CPU_MIPSR2 or CONFIG_CPU_MIPSR6 or CONFIG_MIPS_MT */
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index a5e26dd90592..2ebaabe3af15 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -125,7 +125,7 @@ LEAF(__r4k_wait)
125 nop 125 nop
126 nop 126 nop
127#endif 127#endif
128 .set arch=r4000 128 .set MIPS_ISA_ARCH_LEVEL_RAW
129 wait 129 wait
130 /* end of rollback region (the region size must be power of two) */ 130 /* end of rollback region (the region size must be power of two) */
1311: 1311:
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 0b9082b6b683..368c88b7eb6c 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -186,6 +186,7 @@ void __init check_wait(void)
186 case CPU_PROAPTIV: 186 case CPU_PROAPTIV:
187 case CPU_P5600: 187 case CPU_P5600:
188 case CPU_M5150: 188 case CPU_M5150:
189 case CPU_QEMU_GENERIC:
189 cpu_wait = r4k_wait; 190 cpu_wait = r4k_wait;
190 if (read_c0_config7() & MIPS_CONF7_WII) 191 if (read_c0_config7() & MIPS_CONF7_WII)
191 cpu_wait = r4k_wait_irqoff; 192 cpu_wait = r4k_wait_irqoff;
diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c
new file mode 100644
index 000000000000..64d17e41093b
--- /dev/null
+++ b/arch/mips/kernel/mips-r2-to-r6-emul.c
@@ -0,0 +1,2378 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2014 Imagination Technologies Ltd.
7 * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
8 * Author: Markos Chandras <markos.chandras@imgtec.com>
9 *
10 * MIPS R2 user space instruction emulator for MIPS R6
11 *
12 */
13#include <linux/bug.h>
14#include <linux/compiler.h>
15#include <linux/debugfs.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/ptrace.h>
20#include <linux/seq_file.h>
21
22#include <asm/asm.h>
23#include <asm/branch.h>
24#include <asm/break.h>
25#include <asm/fpu.h>
26#include <asm/fpu_emulator.h>
27#include <asm/inst.h>
28#include <asm/mips-r2-to-r6-emul.h>
29#include <asm/local.h>
30#include <asm/ptrace.h>
31#include <asm/uaccess.h>
32
33#ifdef CONFIG_64BIT
34#define ADDIU "daddiu "
35#define INS "dins "
36#define EXT "dext "
37#else
38#define ADDIU "addiu "
39#define INS "ins "
40#define EXT "ext "
41#endif /* CONFIG_64BIT */
42
43#define SB "sb "
44#define LB "lb "
45#define LL "ll "
46#define SC "sc "
47
48DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats);
49DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats);
50DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats);
51
52extern const unsigned int fpucondbit[8];
53
54#define MIPS_R2_EMUL_TOTAL_PASS 10
55
56int mipsr2_emulation = 0;
57
58static int __init mipsr2emu_enable(char *s)
59{
60 mipsr2_emulation = 1;
61
62 pr_info("MIPS R2-to-R6 Emulator Enabled!");
63
64 return 1;
65}
66__setup("mipsr2emu", mipsr2emu_enable);
67
68/**
69 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
70 * for performance instead of the traditional way of using a stack trampoline
71 * which is rather slow.
72 * @regs: Process register set
73 * @ir: Instruction
74 */
75static inline int mipsr6_emul(struct pt_regs *regs, u32 ir)
76{
77 switch (MIPSInst_OPCODE(ir)) {
78 case addiu_op:
79 if (MIPSInst_RT(ir))
80 regs->regs[MIPSInst_RT(ir)] =
81 (s32)regs->regs[MIPSInst_RS(ir)] +
82 (s32)MIPSInst_SIMM(ir);
83 return 0;
84 case daddiu_op:
85 if (config_enabled(CONFIG_32BIT))
86 break;
87
88 if (MIPSInst_RT(ir))
89 regs->regs[MIPSInst_RT(ir)] =
90 (s64)regs->regs[MIPSInst_RS(ir)] +
91 (s64)MIPSInst_SIMM(ir);
92 return 0;
93 case lwc1_op:
94 case swc1_op:
95 case cop1_op:
96 case cop1x_op:
97 /* FPU instructions in delay slot */
98 return -SIGFPE;
99 case spec_op:
100 switch (MIPSInst_FUNC(ir)) {
101 case or_op:
102 if (MIPSInst_RD(ir))
103 regs->regs[MIPSInst_RD(ir)] =
104 regs->regs[MIPSInst_RS(ir)] |
105 regs->regs[MIPSInst_RT(ir)];
106 return 0;
107 case sll_op:
108 if (MIPSInst_RS(ir))
109 break;
110
111 if (MIPSInst_RD(ir))
112 regs->regs[MIPSInst_RD(ir)] =
113 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) <<
114 MIPSInst_FD(ir));
115 return 0;
116 case srl_op:
117 if (MIPSInst_RS(ir))
118 break;
119
120 if (MIPSInst_RD(ir))
121 regs->regs[MIPSInst_RD(ir)] =
122 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >>
123 MIPSInst_FD(ir));
124 return 0;
125 case addu_op:
126 if (MIPSInst_FD(ir))
127 break;
128
129 if (MIPSInst_RD(ir))
130 regs->regs[MIPSInst_RD(ir)] =
131 (s32)((u32)regs->regs[MIPSInst_RS(ir)] +
132 (u32)regs->regs[MIPSInst_RT(ir)]);
133 return 0;
134 case subu_op:
135 if (MIPSInst_FD(ir))
136 break;
137
138 if (MIPSInst_RD(ir))
139 regs->regs[MIPSInst_RD(ir)] =
140 (s32)((u32)regs->regs[MIPSInst_RS(ir)] -
141 (u32)regs->regs[MIPSInst_RT(ir)]);
142 return 0;
143 case dsll_op:
144 if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir))
145 break;
146
147 if (MIPSInst_RD(ir))
148 regs->regs[MIPSInst_RD(ir)] =
149 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) <<
150 MIPSInst_FD(ir));
151 return 0;
152 case dsrl_op:
153 if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir))
154 break;
155
156 if (MIPSInst_RD(ir))
157 regs->regs[MIPSInst_RD(ir)] =
158 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >>
159 MIPSInst_FD(ir));
160 return 0;
161 case daddu_op:
162 if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir))
163 break;
164
165 if (MIPSInst_RD(ir))
166 regs->regs[MIPSInst_RD(ir)] =
167 (u64)regs->regs[MIPSInst_RS(ir)] +
168 (u64)regs->regs[MIPSInst_RT(ir)];
169 return 0;
170 case dsubu_op:
171 if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir))
172 break;
173
174 if (MIPSInst_RD(ir))
175 regs->regs[MIPSInst_RD(ir)] =
176 (s64)((u64)regs->regs[MIPSInst_RS(ir)] -
177 (u64)regs->regs[MIPSInst_RT(ir)]);
178 return 0;
179 }
180 break;
181 default:
182 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n",
183 ir, MIPSInst_OPCODE(ir));
184 }
185
186 return SIGILL;
187}
188
189/**
190 * movt_func - Emulate a MOVT instruction
191 * @regs: Process register set
192 * @ir: Instruction
193 *
194 * Returns 0 since it always succeeds.
195 */
196static int movf_func(struct pt_regs *regs, u32 ir)
197{
198 u32 csr;
199 u32 cond;
200
201 csr = current->thread.fpu.fcr31;
202 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
203 if (((csr & cond) == 0) && MIPSInst_RD(ir))
204 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
205 MIPS_R2_STATS(movs);
206 return 0;
207}
208
209/**
210 * movt_func - Emulate a MOVT instruction
211 * @regs: Process register set
212 * @ir: Instruction
213 *
214 * Returns 0 since it always succeeds.
215 */
216static int movt_func(struct pt_regs *regs, u32 ir)
217{
218 u32 csr;
219 u32 cond;
220
221 csr = current->thread.fpu.fcr31;
222 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
223
224 if (((csr & cond) != 0) && MIPSInst_RD(ir))
225 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
226
227 MIPS_R2_STATS(movs);
228
229 return 0;
230}
231
232/**
233 * jr_func - Emulate a JR instruction.
234 * @pt_regs: Process register set
235 * @ir: Instruction
236 *
237 * Returns SIGILL if JR was in delay slot, SIGEMT if we
238 * can't compute the EPC, SIGSEGV if we can't access the
239 * userland instruction or 0 on success.
240 */
241static int jr_func(struct pt_regs *regs, u32 ir)
242{
243 int err;
244 unsigned long cepc, epc, nepc;
245 u32 nir;
246
247 if (delay_slot(regs))
248 return SIGILL;
249
250 /* EPC after the RI/JR instruction */
251 nepc = regs->cp0_epc;
252 /* Roll back to the reserved R2 JR instruction */
253 regs->cp0_epc -= 4;
254 epc = regs->cp0_epc;
255 err = __compute_return_epc(regs);
256
257 if (err < 0)
258 return SIGEMT;
259
260
261 /* Computed EPC */
262 cepc = regs->cp0_epc;
263
264 /* Get DS instruction */
265 err = __get_user(nir, (u32 __user *)nepc);
266 if (err)
267 return SIGSEGV;
268
269 MIPS_R2BR_STATS(jrs);
270
271 /* If nir == 0(NOP), then nothing else to do */
272 if (nir) {
273 /*
274 * Negative err means FPU instruction in BD-slot,
275 * Zero err means 'BD-slot emulation done'
276 * For anything else we go back to trampoline emulation.
277 */
278 err = mipsr6_emul(regs, nir);
279 if (err > 0) {
280 regs->cp0_epc = nepc;
281 err = mips_dsemul(regs, nir, cepc);
282 if (err == SIGILL)
283 err = SIGEMT;
284 MIPS_R2_STATS(dsemul);
285 }
286 }
287
288 return err;
289}
290
291/**
292 * movz_func - Emulate a MOVZ instruction
293 * @regs: Process register set
294 * @ir: Instruction
295 *
296 * Returns 0 since it always succeeds.
297 */
298static int movz_func(struct pt_regs *regs, u32 ir)
299{
300 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
301 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
302 MIPS_R2_STATS(movs);
303
304 return 0;
305}
306
307/**
308 * movn_func - Emulate a MOVZ instruction
309 * @regs: Process register set
310 * @ir: Instruction
311 *
312 * Returns 0 since it always succeeds.
313 */
314static int movn_func(struct pt_regs *regs, u32 ir)
315{
316 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
317 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
318 MIPS_R2_STATS(movs);
319
320 return 0;
321}
322
323/**
324 * mfhi_func - Emulate a MFHI instruction
325 * @regs: Process register set
326 * @ir: Instruction
327 *
328 * Returns 0 since it always succeeds.
329 */
330static int mfhi_func(struct pt_regs *regs, u32 ir)
331{
332 if (MIPSInst_RD(ir))
333 regs->regs[MIPSInst_RD(ir)] = regs->hi;
334
335 MIPS_R2_STATS(hilo);
336
337 return 0;
338}
339
340/**
341 * mthi_func - Emulate a MTHI instruction
342 * @regs: Process register set
343 * @ir: Instruction
344 *
345 * Returns 0 since it always succeeds.
346 */
347static int mthi_func(struct pt_regs *regs, u32 ir)
348{
349 regs->hi = regs->regs[MIPSInst_RS(ir)];
350
351 MIPS_R2_STATS(hilo);
352
353 return 0;
354}
355
356/**
357 * mflo_func - Emulate a MFLO instruction
358 * @regs: Process register set
359 * @ir: Instruction
360 *
361 * Returns 0 since it always succeeds.
362 */
363static int mflo_func(struct pt_regs *regs, u32 ir)
364{
365 if (MIPSInst_RD(ir))
366 regs->regs[MIPSInst_RD(ir)] = regs->lo;
367
368 MIPS_R2_STATS(hilo);
369
370 return 0;
371}
372
373/**
374 * mtlo_func - Emulate a MTLO instruction
375 * @regs: Process register set
376 * @ir: Instruction
377 *
378 * Returns 0 since it always succeeds.
379 */
380static int mtlo_func(struct pt_regs *regs, u32 ir)
381{
382 regs->lo = regs->regs[MIPSInst_RS(ir)];
383
384 MIPS_R2_STATS(hilo);
385
386 return 0;
387}
388
389/**
390 * mult_func - Emulate a MULT instruction
391 * @regs: Process register set
392 * @ir: Instruction
393 *
394 * Returns 0 since it always succeeds.
395 */
396static int mult_func(struct pt_regs *regs, u32 ir)
397{
398 s64 res;
399 s32 rt, rs;
400
401 rt = regs->regs[MIPSInst_RT(ir)];
402 rs = regs->regs[MIPSInst_RS(ir)];
403 res = (s64)rt * (s64)rs;
404
405 rs = res;
406 regs->lo = (s64)rs;
407 rt = res >> 32;
408 res = (s64)rt;
409 regs->hi = res;
410
411 MIPS_R2_STATS(muls);
412
413 return 0;
414}
415
416/**
417 * multu_func - Emulate a MULTU instruction
418 * @regs: Process register set
419 * @ir: Instruction
420 *
421 * Returns 0 since it always succeeds.
422 */
423static int multu_func(struct pt_regs *regs, u32 ir)
424{
425 u64 res;
426 u32 rt, rs;
427
428 rt = regs->regs[MIPSInst_RT(ir)];
429 rs = regs->regs[MIPSInst_RS(ir)];
430 res = (u64)rt * (u64)rs;
431 rt = res;
432 regs->lo = (s64)rt;
433 regs->hi = (s64)(res >> 32);
434
435 MIPS_R2_STATS(muls);
436
437 return 0;
438}
439
440/**
441 * div_func - Emulate a DIV instruction
442 * @regs: Process register set
443 * @ir: Instruction
444 *
445 * Returns 0 since it always succeeds.
446 */
447static int div_func(struct pt_regs *regs, u32 ir)
448{
449 s32 rt, rs;
450
451 rt = regs->regs[MIPSInst_RT(ir)];
452 rs = regs->regs[MIPSInst_RS(ir)];
453
454 regs->lo = (s64)(rs / rt);
455 regs->hi = (s64)(rs % rt);
456
457 MIPS_R2_STATS(divs);
458
459 return 0;
460}
461
462/**
463 * divu_func - Emulate a DIVU instruction
464 * @regs: Process register set
465 * @ir: Instruction
466 *
467 * Returns 0 since it always succeeds.
468 */
469static int divu_func(struct pt_regs *regs, u32 ir)
470{
471 u32 rt, rs;
472
473 rt = regs->regs[MIPSInst_RT(ir)];
474 rs = regs->regs[MIPSInst_RS(ir)];
475
476 regs->lo = (s64)(rs / rt);
477 regs->hi = (s64)(rs % rt);
478
479 MIPS_R2_STATS(divs);
480
481 return 0;
482}
483
484/**
485 * dmult_func - Emulate a DMULT instruction
486 * @regs: Process register set
487 * @ir: Instruction
488 *
489 * Returns 0 on success or SIGILL for 32-bit kernels.
490 */
491static int dmult_func(struct pt_regs *regs, u32 ir)
492{
493 s64 res;
494 s64 rt, rs;
495
496 if (config_enabled(CONFIG_32BIT))
497 return SIGILL;
498
499 rt = regs->regs[MIPSInst_RT(ir)];
500 rs = regs->regs[MIPSInst_RS(ir)];
501 res = rt * rs;
502
503 regs->lo = res;
504 __asm__ __volatile__(
505 "dmuh %0, %1, %2\t\n"
506 : "=r"(res)
507 : "r"(rt), "r"(rs));
508
509 regs->hi = res;
510
511 MIPS_R2_STATS(muls);
512
513 return 0;
514}
515
516/**
517 * dmultu_func - Emulate a DMULTU instruction
518 * @regs: Process register set
519 * @ir: Instruction
520 *
521 * Returns 0 on success or SIGILL for 32-bit kernels.
522 */
523static int dmultu_func(struct pt_regs *regs, u32 ir)
524{
525 u64 res;
526 u64 rt, rs;
527
528 if (config_enabled(CONFIG_32BIT))
529 return SIGILL;
530
531 rt = regs->regs[MIPSInst_RT(ir)];
532 rs = regs->regs[MIPSInst_RS(ir)];
533 res = rt * rs;
534
535 regs->lo = res;
536 __asm__ __volatile__(
537 "dmuhu %0, %1, %2\t\n"
538 : "=r"(res)
539 : "r"(rt), "r"(rs));
540
541 regs->hi = res;
542
543 MIPS_R2_STATS(muls);
544
545 return 0;
546}
547
548/**
549 * ddiv_func - Emulate a DDIV instruction
550 * @regs: Process register set
551 * @ir: Instruction
552 *
553 * Returns 0 on success or SIGILL for 32-bit kernels.
554 */
555static int ddiv_func(struct pt_regs *regs, u32 ir)
556{
557 s64 rt, rs;
558
559 if (config_enabled(CONFIG_32BIT))
560 return SIGILL;
561
562 rt = regs->regs[MIPSInst_RT(ir)];
563 rs = regs->regs[MIPSInst_RS(ir)];
564
565 regs->lo = rs / rt;
566 regs->hi = rs % rt;
567
568 MIPS_R2_STATS(divs);
569
570 return 0;
571}
572
573/**
574 * ddivu_func - Emulate a DDIVU instruction
575 * @regs: Process register set
576 * @ir: Instruction
577 *
578 * Returns 0 on success or SIGILL for 32-bit kernels.
579 */
580static int ddivu_func(struct pt_regs *regs, u32 ir)
581{
582 u64 rt, rs;
583
584 if (config_enabled(CONFIG_32BIT))
585 return SIGILL;
586
587 rt = regs->regs[MIPSInst_RT(ir)];
588 rs = regs->regs[MIPSInst_RS(ir)];
589
590 regs->lo = rs / rt;
591 regs->hi = rs % rt;
592
593 MIPS_R2_STATS(divs);
594
595 return 0;
596}
597
598/* R6 removed instructions for the SPECIAL opcode */
599static struct r2_decoder_table spec_op_table[] = {
600 { 0xfc1ff83f, 0x00000008, jr_func },
601 { 0xfc00ffff, 0x00000018, mult_func },
602 { 0xfc00ffff, 0x00000019, multu_func },
603 { 0xfc00ffff, 0x0000001c, dmult_func },
604 { 0xfc00ffff, 0x0000001d, dmultu_func },
605 { 0xffff07ff, 0x00000010, mfhi_func },
606 { 0xfc1fffff, 0x00000011, mthi_func },
607 { 0xffff07ff, 0x00000012, mflo_func },
608 { 0xfc1fffff, 0x00000013, mtlo_func },
609 { 0xfc0307ff, 0x00000001, movf_func },
610 { 0xfc0307ff, 0x00010001, movt_func },
611 { 0xfc0007ff, 0x0000000a, movz_func },
612 { 0xfc0007ff, 0x0000000b, movn_func },
613 { 0xfc00ffff, 0x0000001a, div_func },
614 { 0xfc00ffff, 0x0000001b, divu_func },
615 { 0xfc00ffff, 0x0000001e, ddiv_func },
616 { 0xfc00ffff, 0x0000001f, ddivu_func },
617 {}
618};
619
620/**
621 * madd_func - Emulate a MADD instruction
622 * @regs: Process register set
623 * @ir: Instruction
624 *
625 * Returns 0 since it always succeeds.
626 */
627static int madd_func(struct pt_regs *regs, u32 ir)
628{
629 s64 res;
630 s32 rt, rs;
631
632 rt = regs->regs[MIPSInst_RT(ir)];
633 rs = regs->regs[MIPSInst_RS(ir)];
634 res = (s64)rt * (s64)rs;
635 rt = regs->hi;
636 rs = regs->lo;
637 res += ((((s64)rt) << 32) | (u32)rs);
638
639 rt = res;
640 regs->lo = (s64)rt;
641 rs = res >> 32;
642 regs->hi = (s64)rs;
643
644 MIPS_R2_STATS(dsps);
645
646 return 0;
647}
648
649/**
650 * maddu_func - Emulate a MADDU instruction
651 * @regs: Process register set
652 * @ir: Instruction
653 *
654 * Returns 0 since it always succeeds.
655 */
656static int maddu_func(struct pt_regs *regs, u32 ir)
657{
658 u64 res;
659 u32 rt, rs;
660
661 rt = regs->regs[MIPSInst_RT(ir)];
662 rs = regs->regs[MIPSInst_RS(ir)];
663 res = (u64)rt * (u64)rs;
664 rt = regs->hi;
665 rs = regs->lo;
666 res += ((((s64)rt) << 32) | (u32)rs);
667
668 rt = res;
669 regs->lo = (s64)rt;
670 rs = res >> 32;
671 regs->hi = (s64)rs;
672
673 MIPS_R2_STATS(dsps);
674
675 return 0;
676}
677
678/**
679 * msub_func - Emulate a MSUB instruction
680 * @regs: Process register set
681 * @ir: Instruction
682 *
683 * Returns 0 since it always succeeds.
684 */
685static int msub_func(struct pt_regs *regs, u32 ir)
686{
687 s64 res;
688 s32 rt, rs;
689
690 rt = regs->regs[MIPSInst_RT(ir)];
691 rs = regs->regs[MIPSInst_RS(ir)];
692 res = (s64)rt * (s64)rs;
693 rt = regs->hi;
694 rs = regs->lo;
695 res = ((((s64)rt) << 32) | (u32)rs) - res;
696
697 rt = res;
698 regs->lo = (s64)rt;
699 rs = res >> 32;
700 regs->hi = (s64)rs;
701
702 MIPS_R2_STATS(dsps);
703
704 return 0;
705}
706
707/**
708 * msubu_func - Emulate a MSUBU instruction
709 * @regs: Process register set
710 * @ir: Instruction
711 *
712 * Returns 0 since it always succeeds.
713 */
714static int msubu_func(struct pt_regs *regs, u32 ir)
715{
716 u64 res;
717 u32 rt, rs;
718
719 rt = regs->regs[MIPSInst_RT(ir)];
720 rs = regs->regs[MIPSInst_RS(ir)];
721 res = (u64)rt * (u64)rs;
722 rt = regs->hi;
723 rs = regs->lo;
724 res = ((((s64)rt) << 32) | (u32)rs) - res;
725
726 rt = res;
727 regs->lo = (s64)rt;
728 rs = res >> 32;
729 regs->hi = (s64)rs;
730
731 MIPS_R2_STATS(dsps);
732
733 return 0;
734}
735
736/**
737 * mul_func - Emulate a MUL instruction
738 * @regs: Process register set
739 * @ir: Instruction
740 *
741 * Returns 0 since it always succeeds.
742 */
743static int mul_func(struct pt_regs *regs, u32 ir)
744{
745 s64 res;
746 s32 rt, rs;
747
748 if (!MIPSInst_RD(ir))
749 return 0;
750 rt = regs->regs[MIPSInst_RT(ir)];
751 rs = regs->regs[MIPSInst_RS(ir)];
752 res = (s64)rt * (s64)rs;
753
754 rs = res;
755 regs->regs[MIPSInst_RD(ir)] = (s64)rs;
756
757 MIPS_R2_STATS(muls);
758
759 return 0;
760}
761
762/**
763 * clz_func - Emulate a CLZ instruction
764 * @regs: Process register set
765 * @ir: Instruction
766 *
767 * Returns 0 since it always succeeds.
768 */
769static int clz_func(struct pt_regs *regs, u32 ir)
770{
771 u32 res;
772 u32 rs;
773
774 if (!MIPSInst_RD(ir))
775 return 0;
776
777 rs = regs->regs[MIPSInst_RS(ir)];
778 __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs));
779 regs->regs[MIPSInst_RD(ir)] = res;
780
781 MIPS_R2_STATS(bops);
782
783 return 0;
784}
785
786/**
787 * clo_func - Emulate a CLO instruction
788 * @regs: Process register set
789 * @ir: Instruction
790 *
791 * Returns 0 since it always succeeds.
792 */
793
794static int clo_func(struct pt_regs *regs, u32 ir)
795{
796 u32 res;
797 u32 rs;
798
799 if (!MIPSInst_RD(ir))
800 return 0;
801
802 rs = regs->regs[MIPSInst_RS(ir)];
803 __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs));
804 regs->regs[MIPSInst_RD(ir)] = res;
805
806 MIPS_R2_STATS(bops);
807
808 return 0;
809}
810
811/**
812 * dclz_func - Emulate a DCLZ instruction
813 * @regs: Process register set
814 * @ir: Instruction
815 *
816 * Returns 0 since it always succeeds.
817 */
818static int dclz_func(struct pt_regs *regs, u32 ir)
819{
820 u64 res;
821 u64 rs;
822
823 if (config_enabled(CONFIG_32BIT))
824 return SIGILL;
825
826 if (!MIPSInst_RD(ir))
827 return 0;
828
829 rs = regs->regs[MIPSInst_RS(ir)];
830 __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs));
831 regs->regs[MIPSInst_RD(ir)] = res;
832
833 MIPS_R2_STATS(bops);
834
835 return 0;
836}
837
838/**
839 * dclo_func - Emulate a DCLO instruction
840 * @regs: Process register set
841 * @ir: Instruction
842 *
843 * Returns 0 since it always succeeds.
844 */
845static int dclo_func(struct pt_regs *regs, u32 ir)
846{
847 u64 res;
848 u64 rs;
849
850 if (config_enabled(CONFIG_32BIT))
851 return SIGILL;
852
853 if (!MIPSInst_RD(ir))
854 return 0;
855
856 rs = regs->regs[MIPSInst_RS(ir)];
857 __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs));
858 regs->regs[MIPSInst_RD(ir)] = res;
859
860 MIPS_R2_STATS(bops);
861
862 return 0;
863}
864
865/* R6 removed instructions for the SPECIAL2 opcode */
866static struct r2_decoder_table spec2_op_table[] = {
867 { 0xfc00ffff, 0x70000000, madd_func },
868 { 0xfc00ffff, 0x70000001, maddu_func },
869 { 0xfc0007ff, 0x70000002, mul_func },
870 { 0xfc00ffff, 0x70000004, msub_func },
871 { 0xfc00ffff, 0x70000005, msubu_func },
872 { 0xfc0007ff, 0x70000020, clz_func },
873 { 0xfc0007ff, 0x70000021, clo_func },
874 { 0xfc0007ff, 0x70000024, dclz_func },
875 { 0xfc0007ff, 0x70000025, dclo_func },
876 { }
877};
878
879static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst,
880 struct r2_decoder_table *table)
881{
882 struct r2_decoder_table *p;
883 int err;
884
885 for (p = table; p->func; p++) {
886 if ((inst & p->mask) == p->code) {
887 err = (p->func)(regs, inst);
888 return err;
889 }
890 }
891 return SIGILL;
892}
893
894/**
895 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
896 * @regs: Process register set
897 * @inst: Instruction to decode and emulate
898 */
899int mipsr2_decoder(struct pt_regs *regs, u32 inst)
900{
901 int err = 0;
902 unsigned long vaddr;
903 u32 nir;
904 unsigned long cpc, epc, nepc, r31, res, rs, rt;
905
906 void __user *fault_addr = NULL;
907 int pass = 0;
908
909repeat:
910 r31 = regs->regs[31];
911 epc = regs->cp0_epc;
912 err = compute_return_epc(regs);
913 if (err < 0) {
914 BUG();
915 return SIGEMT;
916 }
917 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n",
918 inst, epc, pass);
919
920 switch (MIPSInst_OPCODE(inst)) {
921 case spec_op:
922 err = mipsr2_find_op_func(regs, inst, spec_op_table);
923 if (err < 0) {
924 /* FPU instruction under JR */
925 regs->cp0_cause |= CAUSEF_BD;
926 goto fpu_emul;
927 }
928 break;
929 case spec2_op:
930 err = mipsr2_find_op_func(regs, inst, spec2_op_table);
931 break;
932 case bcond_op:
933 rt = MIPSInst_RT(inst);
934 rs = MIPSInst_RS(inst);
935 switch (rt) {
936 case tgei_op:
937 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
938 do_trap_or_bp(regs, 0, "TGEI");
939
940 MIPS_R2_STATS(traps);
941
942 break;
943 case tgeiu_op:
944 if (regs->regs[rs] >= MIPSInst_UIMM(inst))
945 do_trap_or_bp(regs, 0, "TGEIU");
946
947 MIPS_R2_STATS(traps);
948
949 break;
950 case tlti_op:
951 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
952 do_trap_or_bp(regs, 0, "TLTI");
953
954 MIPS_R2_STATS(traps);
955
956 break;
957 case tltiu_op:
958 if (regs->regs[rs] < MIPSInst_UIMM(inst))
959 do_trap_or_bp(regs, 0, "TLTIU");
960
961 MIPS_R2_STATS(traps);
962
963 break;
964 case teqi_op:
965 if (regs->regs[rs] == MIPSInst_SIMM(inst))
966 do_trap_or_bp(regs, 0, "TEQI");
967
968 MIPS_R2_STATS(traps);
969
970 break;
971 case tnei_op:
972 if (regs->regs[rs] != MIPSInst_SIMM(inst))
973 do_trap_or_bp(regs, 0, "TNEI");
974
975 MIPS_R2_STATS(traps);
976
977 break;
978 case bltzl_op:
979 case bgezl_op:
980 case bltzall_op:
981 case bgezall_op:
982 if (delay_slot(regs)) {
983 err = SIGILL;
984 break;
985 }
986 regs->regs[31] = r31;
987 regs->cp0_epc = epc;
988 err = __compute_return_epc(regs);
989 if (err < 0)
990 return SIGEMT;
991 if (err != BRANCH_LIKELY_TAKEN)
992 break;
993 cpc = regs->cp0_epc;
994 nepc = epc + 4;
995 err = __get_user(nir, (u32 __user *)nepc);
996 if (err) {
997 err = SIGSEGV;
998 break;
999 }
1000 /*
1001 * This will probably be optimized away when
1002 * CONFIG_DEBUG_FS is not enabled
1003 */
1004 switch (rt) {
1005 case bltzl_op:
1006 MIPS_R2BR_STATS(bltzl);
1007 break;
1008 case bgezl_op:
1009 MIPS_R2BR_STATS(bgezl);
1010 break;
1011 case bltzall_op:
1012 MIPS_R2BR_STATS(bltzall);
1013 break;
1014 case bgezall_op:
1015 MIPS_R2BR_STATS(bgezall);
1016 break;
1017 }
1018
1019 switch (MIPSInst_OPCODE(nir)) {
1020 case cop1_op:
1021 case cop1x_op:
1022 case lwc1_op:
1023 case swc1_op:
1024 regs->cp0_cause |= CAUSEF_BD;
1025 goto fpu_emul;
1026 }
1027 if (nir) {
1028 err = mipsr6_emul(regs, nir);
1029 if (err > 0) {
1030 err = mips_dsemul(regs, nir, cpc);
1031 if (err == SIGILL)
1032 err = SIGEMT;
1033 MIPS_R2_STATS(dsemul);
1034 }
1035 }
1036 break;
1037 case bltzal_op:
1038 case bgezal_op:
1039 if (delay_slot(regs)) {
1040 err = SIGILL;
1041 break;
1042 }
1043 regs->regs[31] = r31;
1044 regs->cp0_epc = epc;
1045 err = __compute_return_epc(regs);
1046 if (err < 0)
1047 return SIGEMT;
1048 cpc = regs->cp0_epc;
1049 nepc = epc + 4;
1050 err = __get_user(nir, (u32 __user *)nepc);
1051 if (err) {
1052 err = SIGSEGV;
1053 break;
1054 }
1055 /*
1056 * This will probably be optimized away when
1057 * CONFIG_DEBUG_FS is not enabled
1058 */
1059 switch (rt) {
1060 case bltzal_op:
1061 MIPS_R2BR_STATS(bltzal);
1062 break;
1063 case bgezal_op:
1064 MIPS_R2BR_STATS(bgezal);
1065 break;
1066 }
1067
1068 switch (MIPSInst_OPCODE(nir)) {
1069 case cop1_op:
1070 case cop1x_op:
1071 case lwc1_op:
1072 case swc1_op:
1073 regs->cp0_cause |= CAUSEF_BD;
1074 goto fpu_emul;
1075 }
1076 if (nir) {
1077 err = mipsr6_emul(regs, nir);
1078 if (err > 0) {
1079 err = mips_dsemul(regs, nir, cpc);
1080 if (err == SIGILL)
1081 err = SIGEMT;
1082 MIPS_R2_STATS(dsemul);
1083 }
1084 }
1085 break;
1086 default:
1087 regs->regs[31] = r31;
1088 regs->cp0_epc = epc;
1089 err = SIGILL;
1090 break;
1091 }
1092 break;
1093
1094 case beql_op:
1095 case bnel_op:
1096 case blezl_op:
1097 case bgtzl_op:
1098 if (delay_slot(regs)) {
1099 err = SIGILL;
1100 break;
1101 }
1102 regs->regs[31] = r31;
1103 regs->cp0_epc = epc;
1104 err = __compute_return_epc(regs);
1105 if (err < 0)
1106 return SIGEMT;
1107 if (err != BRANCH_LIKELY_TAKEN)
1108 break;
1109 cpc = regs->cp0_epc;
1110 nepc = epc + 4;
1111 err = __get_user(nir, (u32 __user *)nepc);
1112 if (err) {
1113 err = SIGSEGV;
1114 break;
1115 }
1116 /*
1117 * This will probably be optimized away when
1118 * CONFIG_DEBUG_FS is not enabled
1119 */
1120 switch (MIPSInst_OPCODE(inst)) {
1121 case beql_op:
1122 MIPS_R2BR_STATS(beql);
1123 break;
1124 case bnel_op:
1125 MIPS_R2BR_STATS(bnel);
1126 break;
1127 case blezl_op:
1128 MIPS_R2BR_STATS(blezl);
1129 break;
1130 case bgtzl_op:
1131 MIPS_R2BR_STATS(bgtzl);
1132 break;
1133 }
1134
1135 switch (MIPSInst_OPCODE(nir)) {
1136 case cop1_op:
1137 case cop1x_op:
1138 case lwc1_op:
1139 case swc1_op:
1140 regs->cp0_cause |= CAUSEF_BD;
1141 goto fpu_emul;
1142 }
1143 if (nir) {
1144 err = mipsr6_emul(regs, nir);
1145 if (err > 0) {
1146 err = mips_dsemul(regs, nir, cpc);
1147 if (err == SIGILL)
1148 err = SIGEMT;
1149 MIPS_R2_STATS(dsemul);
1150 }
1151 }
1152 break;
1153 case lwc1_op:
1154 case swc1_op:
1155 case cop1_op:
1156 case cop1x_op:
1157fpu_emul:
1158 regs->regs[31] = r31;
1159 regs->cp0_epc = epc;
1160 if (!used_math()) { /* First time FPU user. */
1161 err = init_fpu();
1162 set_used_math();
1163 }
1164 lose_fpu(1); /* Save FPU state for the emulator. */
1165
1166 err = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1167 &fault_addr);
1168
1169 /*
1170 * this is a tricky issue - lose_fpu() uses LL/SC atomics
1171 * if FPU is owned and effectively cancels user level LL/SC.
1172 * So, it could be logical to don't restore FPU ownership here.
1173 * But the sequence of multiple FPU instructions is much much
1174 * more often than LL-FPU-SC and I prefer loop here until
1175 * next scheduler cycle cancels FPU ownership
1176 */
1177 own_fpu(1); /* Restore FPU state. */
1178
1179 if (err)
1180 current->thread.cp0_baduaddr = (unsigned long)fault_addr;
1181
1182 MIPS_R2_STATS(fpus);
1183
1184 break;
1185
1186 case lwl_op:
1187 rt = regs->regs[MIPSInst_RT(inst)];
1188 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1189 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1190 current->thread.cp0_baduaddr = vaddr;
1191 err = SIGSEGV;
1192 break;
1193 }
1194 __asm__ __volatile__(
1195 " .set push\n"
1196 " .set reorder\n"
1197#ifdef CONFIG_CPU_LITTLE_ENDIAN
1198 "1:" LB "%1, 0(%2)\n"
1199 INS "%0, %1, 24, 8\n"
1200 " andi %1, %2, 0x3\n"
1201 " beq $0, %1, 9f\n"
1202 ADDIU "%2, %2, -1\n"
1203 "2:" LB "%1, 0(%2)\n"
1204 INS "%0, %1, 16, 8\n"
1205 " andi %1, %2, 0x3\n"
1206 " beq $0, %1, 9f\n"
1207 ADDIU "%2, %2, -1\n"
1208 "3:" LB "%1, 0(%2)\n"
1209 INS "%0, %1, 8, 8\n"
1210 " andi %1, %2, 0x3\n"
1211 " beq $0, %1, 9f\n"
1212 ADDIU "%2, %2, -1\n"
1213 "4:" LB "%1, 0(%2)\n"
1214 INS "%0, %1, 0, 8\n"
1215#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1216 "1:" LB "%1, 0(%2)\n"
1217 INS "%0, %1, 24, 8\n"
1218 ADDIU "%2, %2, 1\n"
1219 " andi %1, %2, 0x3\n"
1220 " beq $0, %1, 9f\n"
1221 "2:" LB "%1, 0(%2)\n"
1222 INS "%0, %1, 16, 8\n"
1223 ADDIU "%2, %2, 1\n"
1224 " andi %1, %2, 0x3\n"
1225 " beq $0, %1, 9f\n"
1226 "3:" LB "%1, 0(%2)\n"
1227 INS "%0, %1, 8, 8\n"
1228 ADDIU "%2, %2, 1\n"
1229 " andi %1, %2, 0x3\n"
1230 " beq $0, %1, 9f\n"
1231 "4:" LB "%1, 0(%2)\n"
1232 INS "%0, %1, 0, 8\n"
1233#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1234 "9: sll %0, %0, 0\n"
1235 "10:\n"
1236 " .insn\n"
1237 " .section .fixup,\"ax\"\n"
1238 "8: li %3,%4\n"
1239 " j 10b\n"
1240 " .previous\n"
1241 " .section __ex_table,\"a\"\n"
1242 " .word 1b,8b\n"
1243 " .word 2b,8b\n"
1244 " .word 3b,8b\n"
1245 " .word 4b,8b\n"
1246 " .previous\n"
1247 " .set pop\n"
1248 : "+&r"(rt), "=&r"(rs),
1249 "+&r"(vaddr), "+&r"(err)
1250 : "i"(SIGSEGV));
1251
1252 if (MIPSInst_RT(inst) && !err)
1253 regs->regs[MIPSInst_RT(inst)] = rt;
1254
1255 MIPS_R2_STATS(loads);
1256
1257 break;
1258
1259 case lwr_op:
1260 rt = regs->regs[MIPSInst_RT(inst)];
1261 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1262 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1263 current->thread.cp0_baduaddr = vaddr;
1264 err = SIGSEGV;
1265 break;
1266 }
1267 __asm__ __volatile__(
1268 " .set push\n"
1269 " .set reorder\n"
1270#ifdef CONFIG_CPU_LITTLE_ENDIAN
1271 "1:" LB "%1, 0(%2)\n"
1272 INS "%0, %1, 0, 8\n"
1273 ADDIU "%2, %2, 1\n"
1274 " andi %1, %2, 0x3\n"
1275 " beq $0, %1, 9f\n"
1276 "2:" LB "%1, 0(%2)\n"
1277 INS "%0, %1, 8, 8\n"
1278 ADDIU "%2, %2, 1\n"
1279 " andi %1, %2, 0x3\n"
1280 " beq $0, %1, 9f\n"
1281 "3:" LB "%1, 0(%2)\n"
1282 INS "%0, %1, 16, 8\n"
1283 ADDIU "%2, %2, 1\n"
1284 " andi %1, %2, 0x3\n"
1285 " beq $0, %1, 9f\n"
1286 "4:" LB "%1, 0(%2)\n"
1287 INS "%0, %1, 24, 8\n"
1288 " sll %0, %0, 0\n"
1289#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1290 "1:" LB "%1, 0(%2)\n"
1291 INS "%0, %1, 0, 8\n"
1292 " andi %1, %2, 0x3\n"
1293 " beq $0, %1, 9f\n"
1294 ADDIU "%2, %2, -1\n"
1295 "2:" LB "%1, 0(%2)\n"
1296 INS "%0, %1, 8, 8\n"
1297 " andi %1, %2, 0x3\n"
1298 " beq $0, %1, 9f\n"
1299 ADDIU "%2, %2, -1\n"
1300 "3:" LB "%1, 0(%2)\n"
1301 INS "%0, %1, 16, 8\n"
1302 " andi %1, %2, 0x3\n"
1303 " beq $0, %1, 9f\n"
1304 ADDIU "%2, %2, -1\n"
1305 "4:" LB "%1, 0(%2)\n"
1306 INS "%0, %1, 24, 8\n"
1307 " sll %0, %0, 0\n"
1308#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1309 "9:\n"
1310 "10:\n"
1311 " .insn\n"
1312 " .section .fixup,\"ax\"\n"
1313 "8: li %3,%4\n"
1314 " j 10b\n"
1315 " .previous\n"
1316 " .section __ex_table,\"a\"\n"
1317 " .word 1b,8b\n"
1318 " .word 2b,8b\n"
1319 " .word 3b,8b\n"
1320 " .word 4b,8b\n"
1321 " .previous\n"
1322 " .set pop\n"
1323 : "+&r"(rt), "=&r"(rs),
1324 "+&r"(vaddr), "+&r"(err)
1325 : "i"(SIGSEGV));
1326 if (MIPSInst_RT(inst) && !err)
1327 regs->regs[MIPSInst_RT(inst)] = rt;
1328
1329 MIPS_R2_STATS(loads);
1330
1331 break;
1332
1333 case swl_op:
1334 rt = regs->regs[MIPSInst_RT(inst)];
1335 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1336 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
1337 current->thread.cp0_baduaddr = vaddr;
1338 err = SIGSEGV;
1339 break;
1340 }
1341 __asm__ __volatile__(
1342 " .set push\n"
1343 " .set reorder\n"
1344#ifdef CONFIG_CPU_LITTLE_ENDIAN
1345 EXT "%1, %0, 24, 8\n"
1346 "1:" SB "%1, 0(%2)\n"
1347 " andi %1, %2, 0x3\n"
1348 " beq $0, %1, 9f\n"
1349 ADDIU "%2, %2, -1\n"
1350 EXT "%1, %0, 16, 8\n"
1351 "2:" SB "%1, 0(%2)\n"
1352 " andi %1, %2, 0x3\n"
1353 " beq $0, %1, 9f\n"
1354 ADDIU "%2, %2, -1\n"
1355 EXT "%1, %0, 8, 8\n"
1356 "3:" SB "%1, 0(%2)\n"
1357 " andi %1, %2, 0x3\n"
1358 " beq $0, %1, 9f\n"
1359 ADDIU "%2, %2, -1\n"
1360 EXT "%1, %0, 0, 8\n"
1361 "4:" SB "%1, 0(%2)\n"
1362#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1363 EXT "%1, %0, 24, 8\n"
1364 "1:" SB "%1, 0(%2)\n"
1365 ADDIU "%2, %2, 1\n"
1366 " andi %1, %2, 0x3\n"
1367 " beq $0, %1, 9f\n"
1368 EXT "%1, %0, 16, 8\n"
1369 "2:" SB "%1, 0(%2)\n"
1370 ADDIU "%2, %2, 1\n"
1371 " andi %1, %2, 0x3\n"
1372 " beq $0, %1, 9f\n"
1373 EXT "%1, %0, 8, 8\n"
1374 "3:" SB "%1, 0(%2)\n"
1375 ADDIU "%2, %2, 1\n"
1376 " andi %1, %2, 0x3\n"
1377 " beq $0, %1, 9f\n"
1378 EXT "%1, %0, 0, 8\n"
1379 "4:" SB "%1, 0(%2)\n"
1380#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1381 "9:\n"
1382 " .insn\n"
1383 " .section .fixup,\"ax\"\n"
1384 "8: li %3,%4\n"
1385 " j 9b\n"
1386 " .previous\n"
1387 " .section __ex_table,\"a\"\n"
1388 " .word 1b,8b\n"
1389 " .word 2b,8b\n"
1390 " .word 3b,8b\n"
1391 " .word 4b,8b\n"
1392 " .previous\n"
1393 " .set pop\n"
1394 : "+&r"(rt), "=&r"(rs),
1395 "+&r"(vaddr), "+&r"(err)
1396 : "i"(SIGSEGV)
1397 : "memory");
1398
1399 MIPS_R2_STATS(stores);
1400
1401 break;
1402
1403 case swr_op:
1404 rt = regs->regs[MIPSInst_RT(inst)];
1405 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1406 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
1407 current->thread.cp0_baduaddr = vaddr;
1408 err = SIGSEGV;
1409 break;
1410 }
1411 __asm__ __volatile__(
1412 " .set push\n"
1413 " .set reorder\n"
1414#ifdef CONFIG_CPU_LITTLE_ENDIAN
1415 EXT "%1, %0, 0, 8\n"
1416 "1:" SB "%1, 0(%2)\n"
1417 ADDIU "%2, %2, 1\n"
1418 " andi %1, %2, 0x3\n"
1419 " beq $0, %1, 9f\n"
1420 EXT "%1, %0, 8, 8\n"
1421 "2:" SB "%1, 0(%2)\n"
1422 ADDIU "%2, %2, 1\n"
1423 " andi %1, %2, 0x3\n"
1424 " beq $0, %1, 9f\n"
1425 EXT "%1, %0, 16, 8\n"
1426 "3:" SB "%1, 0(%2)\n"
1427 ADDIU "%2, %2, 1\n"
1428 " andi %1, %2, 0x3\n"
1429 " beq $0, %1, 9f\n"
1430 EXT "%1, %0, 24, 8\n"
1431 "4:" SB "%1, 0(%2)\n"
1432#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1433 EXT "%1, %0, 0, 8\n"
1434 "1:" SB "%1, 0(%2)\n"
1435 " andi %1, %2, 0x3\n"
1436 " beq $0, %1, 9f\n"
1437 ADDIU "%2, %2, -1\n"
1438 EXT "%1, %0, 8, 8\n"
1439 "2:" SB "%1, 0(%2)\n"
1440 " andi %1, %2, 0x3\n"
1441 " beq $0, %1, 9f\n"
1442 ADDIU "%2, %2, -1\n"
1443 EXT "%1, %0, 16, 8\n"
1444 "3:" SB "%1, 0(%2)\n"
1445 " andi %1, %2, 0x3\n"
1446 " beq $0, %1, 9f\n"
1447 ADDIU "%2, %2, -1\n"
1448 EXT "%1, %0, 24, 8\n"
1449 "4:" SB "%1, 0(%2)\n"
1450#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1451 "9:\n"
1452 " .insn\n"
1453 " .section .fixup,\"ax\"\n"
1454 "8: li %3,%4\n"
1455 " j 9b\n"
1456 " .previous\n"
1457 " .section __ex_table,\"a\"\n"
1458 " .word 1b,8b\n"
1459 " .word 2b,8b\n"
1460 " .word 3b,8b\n"
1461 " .word 4b,8b\n"
1462 " .previous\n"
1463 " .set pop\n"
1464 : "+&r"(rt), "=&r"(rs),
1465 "+&r"(vaddr), "+&r"(err)
1466 : "i"(SIGSEGV)
1467 : "memory");
1468
1469 MIPS_R2_STATS(stores);
1470
1471 break;
1472
1473 case ldl_op:
1474 if (config_enabled(CONFIG_32BIT)) {
1475 err = SIGILL;
1476 break;
1477 }
1478
1479 rt = regs->regs[MIPSInst_RT(inst)];
1480 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1481 if (!access_ok(VERIFY_READ, vaddr, 8)) {
1482 current->thread.cp0_baduaddr = vaddr;
1483 err = SIGSEGV;
1484 break;
1485 }
1486 __asm__ __volatile__(
1487 " .set push\n"
1488 " .set reorder\n"
1489#ifdef CONFIG_CPU_LITTLE_ENDIAN
1490 "1: lb %1, 0(%2)\n"
1491 " dinsu %0, %1, 56, 8\n"
1492 " andi %1, %2, 0x7\n"
1493 " beq $0, %1, 9f\n"
1494 " daddiu %2, %2, -1\n"
1495 "2: lb %1, 0(%2)\n"
1496 " dinsu %0, %1, 48, 8\n"
1497 " andi %1, %2, 0x7\n"
1498 " beq $0, %1, 9f\n"
1499 " daddiu %2, %2, -1\n"
1500 "3: lb %1, 0(%2)\n"
1501 " dinsu %0, %1, 40, 8\n"
1502 " andi %1, %2, 0x7\n"
1503 " beq $0, %1, 9f\n"
1504 " daddiu %2, %2, -1\n"
1505 "4: lb %1, 0(%2)\n"
1506 " dinsu %0, %1, 32, 8\n"
1507 " andi %1, %2, 0x7\n"
1508 " beq $0, %1, 9f\n"
1509 " daddiu %2, %2, -1\n"
1510 "5: lb %1, 0(%2)\n"
1511 " dins %0, %1, 24, 8\n"
1512 " andi %1, %2, 0x7\n"
1513 " beq $0, %1, 9f\n"
1514 " daddiu %2, %2, -1\n"
1515 "6: lb %1, 0(%2)\n"
1516 " dins %0, %1, 16, 8\n"
1517 " andi %1, %2, 0x7\n"
1518 " beq $0, %1, 9f\n"
1519 " daddiu %2, %2, -1\n"
1520 "7: lb %1, 0(%2)\n"
1521 " dins %0, %1, 8, 8\n"
1522 " andi %1, %2, 0x7\n"
1523 " beq $0, %1, 9f\n"
1524 " daddiu %2, %2, -1\n"
1525 "0: lb %1, 0(%2)\n"
1526 " dins %0, %1, 0, 8\n"
1527#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1528 "1: lb %1, 0(%2)\n"
1529 " dinsu %0, %1, 56, 8\n"
1530 " daddiu %2, %2, 1\n"
1531 " andi %1, %2, 0x7\n"
1532 " beq $0, %1, 9f\n"
1533 "2: lb %1, 0(%2)\n"
1534 " dinsu %0, %1, 48, 8\n"
1535 " daddiu %2, %2, 1\n"
1536 " andi %1, %2, 0x7\n"
1537 " beq $0, %1, 9f\n"
1538 "3: lb %1, 0(%2)\n"
1539 " dinsu %0, %1, 40, 8\n"
1540 " daddiu %2, %2, 1\n"
1541 " andi %1, %2, 0x7\n"
1542 " beq $0, %1, 9f\n"
1543 "4: lb %1, 0(%2)\n"
1544 " dinsu %0, %1, 32, 8\n"
1545 " daddiu %2, %2, 1\n"
1546 " andi %1, %2, 0x7\n"
1547 " beq $0, %1, 9f\n"
1548 "5: lb %1, 0(%2)\n"
1549 " dins %0, %1, 24, 8\n"
1550 " daddiu %2, %2, 1\n"
1551 " andi %1, %2, 0x7\n"
1552 " beq $0, %1, 9f\n"
1553 "6: lb %1, 0(%2)\n"
1554 " dins %0, %1, 16, 8\n"
1555 " daddiu %2, %2, 1\n"
1556 " andi %1, %2, 0x7\n"
1557 " beq $0, %1, 9f\n"
1558 "7: lb %1, 0(%2)\n"
1559 " dins %0, %1, 8, 8\n"
1560 " daddiu %2, %2, 1\n"
1561 " andi %1, %2, 0x7\n"
1562 " beq $0, %1, 9f\n"
1563 "0: lb %1, 0(%2)\n"
1564 " dins %0, %1, 0, 8\n"
1565#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1566 "9:\n"
1567 " .insn\n"
1568 " .section .fixup,\"ax\"\n"
1569 "8: li %3,%4\n"
1570 " j 9b\n"
1571 " .previous\n"
1572 " .section __ex_table,\"a\"\n"
1573 " .word 1b,8b\n"
1574 " .word 2b,8b\n"
1575 " .word 3b,8b\n"
1576 " .word 4b,8b\n"
1577 " .word 5b,8b\n"
1578 " .word 6b,8b\n"
1579 " .word 7b,8b\n"
1580 " .word 0b,8b\n"
1581 " .previous\n"
1582 " .set pop\n"
1583 : "+&r"(rt), "=&r"(rs),
1584 "+&r"(vaddr), "+&r"(err)
1585 : "i"(SIGSEGV));
1586 if (MIPSInst_RT(inst) && !err)
1587 regs->regs[MIPSInst_RT(inst)] = rt;
1588
1589 MIPS_R2_STATS(loads);
1590 break;
1591
1592 case ldr_op:
1593 if (config_enabled(CONFIG_32BIT)) {
1594 err = SIGILL;
1595 break;
1596 }
1597
1598 rt = regs->regs[MIPSInst_RT(inst)];
1599 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1600 if (!access_ok(VERIFY_READ, vaddr, 8)) {
1601 current->thread.cp0_baduaddr = vaddr;
1602 err = SIGSEGV;
1603 break;
1604 }
1605 __asm__ __volatile__(
1606 " .set push\n"
1607 " .set reorder\n"
1608#ifdef CONFIG_CPU_LITTLE_ENDIAN
1609 "1: lb %1, 0(%2)\n"
1610 " dins %0, %1, 0, 8\n"
1611 " daddiu %2, %2, 1\n"
1612 " andi %1, %2, 0x7\n"
1613 " beq $0, %1, 9f\n"
1614 "2: lb %1, 0(%2)\n"
1615 " dins %0, %1, 8, 8\n"
1616 " daddiu %2, %2, 1\n"
1617 " andi %1, %2, 0x7\n"
1618 " beq $0, %1, 9f\n"
1619 "3: lb %1, 0(%2)\n"
1620 " dins %0, %1, 16, 8\n"
1621 " daddiu %2, %2, 1\n"
1622 " andi %1, %2, 0x7\n"
1623 " beq $0, %1, 9f\n"
1624 "4: lb %1, 0(%2)\n"
1625 " dins %0, %1, 24, 8\n"
1626 " daddiu %2, %2, 1\n"
1627 " andi %1, %2, 0x7\n"
1628 " beq $0, %1, 9f\n"
1629 "5: lb %1, 0(%2)\n"
1630 " dinsu %0, %1, 32, 8\n"
1631 " daddiu %2, %2, 1\n"
1632 " andi %1, %2, 0x7\n"
1633 " beq $0, %1, 9f\n"
1634 "6: lb %1, 0(%2)\n"
1635 " dinsu %0, %1, 40, 8\n"
1636 " daddiu %2, %2, 1\n"
1637 " andi %1, %2, 0x7\n"
1638 " beq $0, %1, 9f\n"
1639 "7: lb %1, 0(%2)\n"
1640 " dinsu %0, %1, 48, 8\n"
1641 " daddiu %2, %2, 1\n"
1642 " andi %1, %2, 0x7\n"
1643 " beq $0, %1, 9f\n"
1644 "0: lb %1, 0(%2)\n"
1645 " dinsu %0, %1, 56, 8\n"
1646#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1647 "1: lb %1, 0(%2)\n"
1648 " dins %0, %1, 0, 8\n"
1649 " andi %1, %2, 0x7\n"
1650 " beq $0, %1, 9f\n"
1651 " daddiu %2, %2, -1\n"
1652 "2: lb %1, 0(%2)\n"
1653 " dins %0, %1, 8, 8\n"
1654 " andi %1, %2, 0x7\n"
1655 " beq $0, %1, 9f\n"
1656 " daddiu %2, %2, -1\n"
1657 "3: lb %1, 0(%2)\n"
1658 " dins %0, %1, 16, 8\n"
1659 " andi %1, %2, 0x7\n"
1660 " beq $0, %1, 9f\n"
1661 " daddiu %2, %2, -1\n"
1662 "4: lb %1, 0(%2)\n"
1663 " dins %0, %1, 24, 8\n"
1664 " andi %1, %2, 0x7\n"
1665 " beq $0, %1, 9f\n"
1666 " daddiu %2, %2, -1\n"
1667 "5: lb %1, 0(%2)\n"
1668 " dinsu %0, %1, 32, 8\n"
1669 " andi %1, %2, 0x7\n"
1670 " beq $0, %1, 9f\n"
1671 " daddiu %2, %2, -1\n"
1672 "6: lb %1, 0(%2)\n"
1673 " dinsu %0, %1, 40, 8\n"
1674 " andi %1, %2, 0x7\n"
1675 " beq $0, %1, 9f\n"
1676 " daddiu %2, %2, -1\n"
1677 "7: lb %1, 0(%2)\n"
1678 " dinsu %0, %1, 48, 8\n"
1679 " andi %1, %2, 0x7\n"
1680 " beq $0, %1, 9f\n"
1681 " daddiu %2, %2, -1\n"
1682 "0: lb %1, 0(%2)\n"
1683 " dinsu %0, %1, 56, 8\n"
1684#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1685 "9:\n"
1686 " .insn\n"
1687 " .section .fixup,\"ax\"\n"
1688 "8: li %3,%4\n"
1689 " j 9b\n"
1690 " .previous\n"
1691 " .section __ex_table,\"a\"\n"
1692 " .word 1b,8b\n"
1693 " .word 2b,8b\n"
1694 " .word 3b,8b\n"
1695 " .word 4b,8b\n"
1696 " .word 5b,8b\n"
1697 " .word 6b,8b\n"
1698 " .word 7b,8b\n"
1699 " .word 0b,8b\n"
1700 " .previous\n"
1701 " .set pop\n"
1702 : "+&r"(rt), "=&r"(rs),
1703 "+&r"(vaddr), "+&r"(err)
1704 : "i"(SIGSEGV));
1705 if (MIPSInst_RT(inst) && !err)
1706 regs->regs[MIPSInst_RT(inst)] = rt;
1707
1708 MIPS_R2_STATS(loads);
1709 break;
1710
1711 case sdl_op:
1712 if (config_enabled(CONFIG_32BIT)) {
1713 err = SIGILL;
1714 break;
1715 }
1716
1717 rt = regs->regs[MIPSInst_RT(inst)];
1718 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1719 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
1720 current->thread.cp0_baduaddr = vaddr;
1721 err = SIGSEGV;
1722 break;
1723 }
1724 __asm__ __volatile__(
1725 " .set push\n"
1726 " .set reorder\n"
1727#ifdef CONFIG_CPU_LITTLE_ENDIAN
1728 " dextu %1, %0, 56, 8\n"
1729 "1: sb %1, 0(%2)\n"
1730 " andi %1, %2, 0x7\n"
1731 " beq $0, %1, 9f\n"
1732 " daddiu %2, %2, -1\n"
1733 " dextu %1, %0, 48, 8\n"
1734 "2: sb %1, 0(%2)\n"
1735 " andi %1, %2, 0x7\n"
1736 " beq $0, %1, 9f\n"
1737 " daddiu %2, %2, -1\n"
1738 " dextu %1, %0, 40, 8\n"
1739 "3: sb %1, 0(%2)\n"
1740 " andi %1, %2, 0x7\n"
1741 " beq $0, %1, 9f\n"
1742 " daddiu %2, %2, -1\n"
1743 " dextu %1, %0, 32, 8\n"
1744 "4: sb %1, 0(%2)\n"
1745 " andi %1, %2, 0x7\n"
1746 " beq $0, %1, 9f\n"
1747 " daddiu %2, %2, -1\n"
1748 " dext %1, %0, 24, 8\n"
1749 "5: sb %1, 0(%2)\n"
1750 " andi %1, %2, 0x7\n"
1751 " beq $0, %1, 9f\n"
1752 " daddiu %2, %2, -1\n"
1753 " dext %1, %0, 16, 8\n"
1754 "6: sb %1, 0(%2)\n"
1755 " andi %1, %2, 0x7\n"
1756 " beq $0, %1, 9f\n"
1757 " daddiu %2, %2, -1\n"
1758 " dext %1, %0, 8, 8\n"
1759 "7: sb %1, 0(%2)\n"
1760 " andi %1, %2, 0x7\n"
1761 " beq $0, %1, 9f\n"
1762 " daddiu %2, %2, -1\n"
1763 " dext %1, %0, 0, 8\n"
1764 "0: sb %1, 0(%2)\n"
1765#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1766 " dextu %1, %0, 56, 8\n"
1767 "1: sb %1, 0(%2)\n"
1768 " daddiu %2, %2, 1\n"
1769 " andi %1, %2, 0x7\n"
1770 " beq $0, %1, 9f\n"
1771 " dextu %1, %0, 48, 8\n"
1772 "2: sb %1, 0(%2)\n"
1773 " daddiu %2, %2, 1\n"
1774 " andi %1, %2, 0x7\n"
1775 " beq $0, %1, 9f\n"
1776 " dextu %1, %0, 40, 8\n"
1777 "3: sb %1, 0(%2)\n"
1778 " daddiu %2, %2, 1\n"
1779 " andi %1, %2, 0x7\n"
1780 " beq $0, %1, 9f\n"
1781 " dextu %1, %0, 32, 8\n"
1782 "4: sb %1, 0(%2)\n"
1783 " daddiu %2, %2, 1\n"
1784 " andi %1, %2, 0x7\n"
1785 " beq $0, %1, 9f\n"
1786 " dext %1, %0, 24, 8\n"
1787 "5: sb %1, 0(%2)\n"
1788 " daddiu %2, %2, 1\n"
1789 " andi %1, %2, 0x7\n"
1790 " beq $0, %1, 9f\n"
1791 " dext %1, %0, 16, 8\n"
1792 "6: sb %1, 0(%2)\n"
1793 " daddiu %2, %2, 1\n"
1794 " andi %1, %2, 0x7\n"
1795 " beq $0, %1, 9f\n"
1796 " dext %1, %0, 8, 8\n"
1797 "7: sb %1, 0(%2)\n"
1798 " daddiu %2, %2, 1\n"
1799 " andi %1, %2, 0x7\n"
1800 " beq $0, %1, 9f\n"
1801 " dext %1, %0, 0, 8\n"
1802 "0: sb %1, 0(%2)\n"
1803#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1804 "9:\n"
1805 " .insn\n"
1806 " .section .fixup,\"ax\"\n"
1807 "8: li %3,%4\n"
1808 " j 9b\n"
1809 " .previous\n"
1810 " .section __ex_table,\"a\"\n"
1811 " .word 1b,8b\n"
1812 " .word 2b,8b\n"
1813 " .word 3b,8b\n"
1814 " .word 4b,8b\n"
1815 " .word 5b,8b\n"
1816 " .word 6b,8b\n"
1817 " .word 7b,8b\n"
1818 " .word 0b,8b\n"
1819 " .previous\n"
1820 " .set pop\n"
1821 : "+&r"(rt), "=&r"(rs),
1822 "+&r"(vaddr), "+&r"(err)
1823 : "i"(SIGSEGV)
1824 : "memory");
1825
1826 MIPS_R2_STATS(stores);
1827 break;
1828
1829 case sdr_op:
1830 if (config_enabled(CONFIG_32BIT)) {
1831 err = SIGILL;
1832 break;
1833 }
1834
1835 rt = regs->regs[MIPSInst_RT(inst)];
1836 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1837 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
1838 current->thread.cp0_baduaddr = vaddr;
1839 err = SIGSEGV;
1840 break;
1841 }
1842 __asm__ __volatile__(
1843 " .set push\n"
1844 " .set reorder\n"
1845#ifdef CONFIG_CPU_LITTLE_ENDIAN
1846 " dext %1, %0, 0, 8\n"
1847 "1: sb %1, 0(%2)\n"
1848 " daddiu %2, %2, 1\n"
1849 " andi %1, %2, 0x7\n"
1850 " beq $0, %1, 9f\n"
1851 " dext %1, %0, 8, 8\n"
1852 "2: sb %1, 0(%2)\n"
1853 " daddiu %2, %2, 1\n"
1854 " andi %1, %2, 0x7\n"
1855 " beq $0, %1, 9f\n"
1856 " dext %1, %0, 16, 8\n"
1857 "3: sb %1, 0(%2)\n"
1858 " daddiu %2, %2, 1\n"
1859 " andi %1, %2, 0x7\n"
1860 " beq $0, %1, 9f\n"
1861 " dext %1, %0, 24, 8\n"
1862 "4: sb %1, 0(%2)\n"
1863 " daddiu %2, %2, 1\n"
1864 " andi %1, %2, 0x7\n"
1865 " beq $0, %1, 9f\n"
1866 " dextu %1, %0, 32, 8\n"
1867 "5: sb %1, 0(%2)\n"
1868 " daddiu %2, %2, 1\n"
1869 " andi %1, %2, 0x7\n"
1870 " beq $0, %1, 9f\n"
1871 " dextu %1, %0, 40, 8\n"
1872 "6: sb %1, 0(%2)\n"
1873 " daddiu %2, %2, 1\n"
1874 " andi %1, %2, 0x7\n"
1875 " beq $0, %1, 9f\n"
1876 " dextu %1, %0, 48, 8\n"
1877 "7: sb %1, 0(%2)\n"
1878 " daddiu %2, %2, 1\n"
1879 " andi %1, %2, 0x7\n"
1880 " beq $0, %1, 9f\n"
1881 " dextu %1, %0, 56, 8\n"
1882 "0: sb %1, 0(%2)\n"
1883#else /* !CONFIG_CPU_LITTLE_ENDIAN */
1884 " dext %1, %0, 0, 8\n"
1885 "1: sb %1, 0(%2)\n"
1886 " andi %1, %2, 0x7\n"
1887 " beq $0, %1, 9f\n"
1888 " daddiu %2, %2, -1\n"
1889 " dext %1, %0, 8, 8\n"
1890 "2: sb %1, 0(%2)\n"
1891 " andi %1, %2, 0x7\n"
1892 " beq $0, %1, 9f\n"
1893 " daddiu %2, %2, -1\n"
1894 " dext %1, %0, 16, 8\n"
1895 "3: sb %1, 0(%2)\n"
1896 " andi %1, %2, 0x7\n"
1897 " beq $0, %1, 9f\n"
1898 " daddiu %2, %2, -1\n"
1899 " dext %1, %0, 24, 8\n"
1900 "4: sb %1, 0(%2)\n"
1901 " andi %1, %2, 0x7\n"
1902 " beq $0, %1, 9f\n"
1903 " daddiu %2, %2, -1\n"
1904 " dextu %1, %0, 32, 8\n"
1905 "5: sb %1, 0(%2)\n"
1906 " andi %1, %2, 0x7\n"
1907 " beq $0, %1, 9f\n"
1908 " daddiu %2, %2, -1\n"
1909 " dextu %1, %0, 40, 8\n"
1910 "6: sb %1, 0(%2)\n"
1911 " andi %1, %2, 0x7\n"
1912 " beq $0, %1, 9f\n"
1913 " daddiu %2, %2, -1\n"
1914 " dextu %1, %0, 48, 8\n"
1915 "7: sb %1, 0(%2)\n"
1916 " andi %1, %2, 0x7\n"
1917 " beq $0, %1, 9f\n"
1918 " daddiu %2, %2, -1\n"
1919 " dextu %1, %0, 56, 8\n"
1920 "0: sb %1, 0(%2)\n"
1921#endif /* CONFIG_CPU_LITTLE_ENDIAN */
1922 "9:\n"
1923 " .insn\n"
1924 " .section .fixup,\"ax\"\n"
1925 "8: li %3,%4\n"
1926 " j 9b\n"
1927 " .previous\n"
1928 " .section __ex_table,\"a\"\n"
1929 " .word 1b,8b\n"
1930 " .word 2b,8b\n"
1931 " .word 3b,8b\n"
1932 " .word 4b,8b\n"
1933 " .word 5b,8b\n"
1934 " .word 6b,8b\n"
1935 " .word 7b,8b\n"
1936 " .word 0b,8b\n"
1937 " .previous\n"
1938 " .set pop\n"
1939 : "+&r"(rt), "=&r"(rs),
1940 "+&r"(vaddr), "+&r"(err)
1941 : "i"(SIGSEGV)
1942 : "memory");
1943
1944 MIPS_R2_STATS(stores);
1945
1946 break;
1947 case ll_op:
1948 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1949 if (vaddr & 0x3) {
1950 current->thread.cp0_baduaddr = vaddr;
1951 err = SIGBUS;
1952 break;
1953 }
1954 if (!access_ok(VERIFY_READ, vaddr, 4)) {
1955 current->thread.cp0_baduaddr = vaddr;
1956 err = SIGBUS;
1957 break;
1958 }
1959
1960 if (!cpu_has_rw_llb) {
1961 /*
1962 * An LL/SC block can't be safely emulated without
1963 * a Config5/LLB availability. So it's probably time to
1964 * kill our process before things get any worse. This is
1965 * because Config5/LLB allows us to use ERETNC so that
1966 * the LLAddr/LLB bit is not cleared when we return from
1967 * an exception. MIPS R2 LL/SC instructions trap with an
1968 * RI exception so once we emulate them here, we return
1969 * back to userland with ERETNC. That preserves the
1970 * LLAddr/LLB so the subsequent SC instruction will
1971 * succeed preserving the atomic semantics of the LL/SC
1972 * block. Without that, there is no safe way to emulate
1973 * an LL/SC block in MIPSR2 userland.
1974 */
1975 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
1976 err = SIGKILL;
1977 break;
1978 }
1979
1980 __asm__ __volatile__(
1981 "1:\n"
1982 "ll %0, 0(%2)\n"
1983 "2:\n"
1984 ".insn\n"
1985 ".section .fixup,\"ax\"\n"
1986 "3:\n"
1987 "li %1, %3\n"
1988 "j 2b\n"
1989 ".previous\n"
1990 ".section __ex_table,\"a\"\n"
1991 ".word 1b, 3b\n"
1992 ".previous\n"
1993 : "=&r"(res), "+&r"(err)
1994 : "r"(vaddr), "i"(SIGSEGV)
1995 : "memory");
1996
1997 if (MIPSInst_RT(inst) && !err)
1998 regs->regs[MIPSInst_RT(inst)] = res;
1999 MIPS_R2_STATS(llsc);
2000
2001 break;
2002
2003 case sc_op:
2004 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2005 if (vaddr & 0x3) {
2006 current->thread.cp0_baduaddr = vaddr;
2007 err = SIGBUS;
2008 break;
2009 }
2010 if (!access_ok(VERIFY_WRITE, vaddr, 4)) {
2011 current->thread.cp0_baduaddr = vaddr;
2012 err = SIGBUS;
2013 break;
2014 }
2015
2016 if (!cpu_has_rw_llb) {
2017 /*
2018 * An LL/SC block can't be safely emulated without
2019 * a Config5/LLB availability. So it's probably time to
2020 * kill our process before things get any worse. This is
2021 * because Config5/LLB allows us to use ERETNC so that
2022 * the LLAddr/LLB bit is not cleared when we return from
2023 * an exception. MIPS R2 LL/SC instructions trap with an
2024 * RI exception so once we emulate them here, we return
2025 * back to userland with ERETNC. That preserves the
2026 * LLAddr/LLB so the subsequent SC instruction will
2027 * succeed preserving the atomic semantics of the LL/SC
2028 * block. Without that, there is no safe way to emulate
2029 * an LL/SC block in MIPSR2 userland.
2030 */
2031 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2032 err = SIGKILL;
2033 break;
2034 }
2035
2036 res = regs->regs[MIPSInst_RT(inst)];
2037
2038 __asm__ __volatile__(
2039 "1:\n"
2040 "sc %0, 0(%2)\n"
2041 "2:\n"
2042 ".insn\n"
2043 ".section .fixup,\"ax\"\n"
2044 "3:\n"
2045 "li %1, %3\n"
2046 "j 2b\n"
2047 ".previous\n"
2048 ".section __ex_table,\"a\"\n"
2049 ".word 1b, 3b\n"
2050 ".previous\n"
2051 : "+&r"(res), "+&r"(err)
2052 : "r"(vaddr), "i"(SIGSEGV));
2053
2054 if (MIPSInst_RT(inst) && !err)
2055 regs->regs[MIPSInst_RT(inst)] = res;
2056
2057 MIPS_R2_STATS(llsc);
2058
2059 break;
2060
2061 case lld_op:
2062 if (config_enabled(CONFIG_32BIT)) {
2063 err = SIGILL;
2064 break;
2065 }
2066
2067 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2068 if (vaddr & 0x7) {
2069 current->thread.cp0_baduaddr = vaddr;
2070 err = SIGBUS;
2071 break;
2072 }
2073 if (!access_ok(VERIFY_READ, vaddr, 8)) {
2074 current->thread.cp0_baduaddr = vaddr;
2075 err = SIGBUS;
2076 break;
2077 }
2078
2079 if (!cpu_has_rw_llb) {
2080 /*
2081 * An LL/SC block can't be safely emulated without
2082 * a Config5/LLB availability. So it's probably time to
2083 * kill our process before things get any worse. This is
2084 * because Config5/LLB allows us to use ERETNC so that
2085 * the LLAddr/LLB bit is not cleared when we return from
2086 * an exception. MIPS R2 LL/SC instructions trap with an
2087 * RI exception so once we emulate them here, we return
2088 * back to userland with ERETNC. That preserves the
2089 * LLAddr/LLB so the subsequent SC instruction will
2090 * succeed preserving the atomic semantics of the LL/SC
2091 * block. Without that, there is no safe way to emulate
2092 * an LL/SC block in MIPSR2 userland.
2093 */
2094 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2095 err = SIGKILL;
2096 break;
2097 }
2098
2099 __asm__ __volatile__(
2100 "1:\n"
2101 "lld %0, 0(%2)\n"
2102 "2:\n"
2103 ".insn\n"
2104 ".section .fixup,\"ax\"\n"
2105 "3:\n"
2106 "li %1, %3\n"
2107 "j 2b\n"
2108 ".previous\n"
2109 ".section __ex_table,\"a\"\n"
2110 ".word 1b, 3b\n"
2111 ".previous\n"
2112 : "=&r"(res), "+&r"(err)
2113 : "r"(vaddr), "i"(SIGSEGV)
2114 : "memory");
2115 if (MIPSInst_RT(inst) && !err)
2116 regs->regs[MIPSInst_RT(inst)] = res;
2117
2118 MIPS_R2_STATS(llsc);
2119
2120 break;
2121
2122 case scd_op:
2123 if (config_enabled(CONFIG_32BIT)) {
2124 err = SIGILL;
2125 break;
2126 }
2127
2128 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
2129 if (vaddr & 0x7) {
2130 current->thread.cp0_baduaddr = vaddr;
2131 err = SIGBUS;
2132 break;
2133 }
2134 if (!access_ok(VERIFY_WRITE, vaddr, 8)) {
2135 current->thread.cp0_baduaddr = vaddr;
2136 err = SIGBUS;
2137 break;
2138 }
2139
2140 if (!cpu_has_rw_llb) {
2141 /*
2142 * An LL/SC block can't be safely emulated without
2143 * a Config5/LLB availability. So it's probably time to
2144 * kill our process before things get any worse. This is
2145 * because Config5/LLB allows us to use ERETNC so that
2146 * the LLAddr/LLB bit is not cleared when we return from
2147 * an exception. MIPS R2 LL/SC instructions trap with an
2148 * RI exception so once we emulate them here, we return
2149 * back to userland with ERETNC. That preserves the
2150 * LLAddr/LLB so the subsequent SC instruction will
2151 * succeed preserving the atomic semantics of the LL/SC
2152 * block. Without that, there is no safe way to emulate
2153 * an LL/SC block in MIPSR2 userland.
2154 */
2155 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n");
2156 err = SIGKILL;
2157 break;
2158 }
2159
2160 res = regs->regs[MIPSInst_RT(inst)];
2161
2162 __asm__ __volatile__(
2163 "1:\n"
2164 "scd %0, 0(%2)\n"
2165 "2:\n"
2166 ".insn\n"
2167 ".section .fixup,\"ax\"\n"
2168 "3:\n"
2169 "li %1, %3\n"
2170 "j 2b\n"
2171 ".previous\n"
2172 ".section __ex_table,\"a\"\n"
2173 ".word 1b, 3b\n"
2174 ".previous\n"
2175 : "+&r"(res), "+&r"(err)
2176 : "r"(vaddr), "i"(SIGSEGV));
2177
2178 if (MIPSInst_RT(inst) && !err)
2179 regs->regs[MIPSInst_RT(inst)] = res;
2180
2181 MIPS_R2_STATS(llsc);
2182
2183 break;
2184 case pref_op:
2185 /* skip it */
2186 break;
2187 default:
2188 err = SIGILL;
2189 }
2190
2191 /*
2192 * Lets not return to userland just yet. It's constly and
2193 * it's likely we have more R2 instructions to emulate
2194 */
2195 if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) {
2196 regs->cp0_cause &= ~CAUSEF_BD;
2197 err = get_user(inst, (u32 __user *)regs->cp0_epc);
2198 if (!err)
2199 goto repeat;
2200
2201 if (err < 0)
2202 err = SIGSEGV;
2203 }
2204
2205 if (err && (err != SIGEMT)) {
2206 regs->regs[31] = r31;
2207 regs->cp0_epc = epc;
2208 }
2209
2210 /* Likely a MIPS R6 compatible instruction */
2211 if (pass && (err == SIGILL))
2212 err = 0;
2213
2214 return err;
2215}
2216
2217#ifdef CONFIG_DEBUG_FS
2218
2219static int mipsr2_stats_show(struct seq_file *s, void *unused)
2220{
2221
2222 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n");
2223 seq_printf(s, "movs\t\t%ld\t%ld\n",
2224 (unsigned long)__this_cpu_read(mipsr2emustats.movs),
2225 (unsigned long)__this_cpu_read(mipsr2bdemustats.movs));
2226 seq_printf(s, "hilo\t\t%ld\t%ld\n",
2227 (unsigned long)__this_cpu_read(mipsr2emustats.hilo),
2228 (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo));
2229 seq_printf(s, "muls\t\t%ld\t%ld\n",
2230 (unsigned long)__this_cpu_read(mipsr2emustats.muls),
2231 (unsigned long)__this_cpu_read(mipsr2bdemustats.muls));
2232 seq_printf(s, "divs\t\t%ld\t%ld\n",
2233 (unsigned long)__this_cpu_read(mipsr2emustats.divs),
2234 (unsigned long)__this_cpu_read(mipsr2bdemustats.divs));
2235 seq_printf(s, "dsps\t\t%ld\t%ld\n",
2236 (unsigned long)__this_cpu_read(mipsr2emustats.dsps),
2237 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps));
2238 seq_printf(s, "bops\t\t%ld\t%ld\n",
2239 (unsigned long)__this_cpu_read(mipsr2emustats.bops),
2240 (unsigned long)__this_cpu_read(mipsr2bdemustats.bops));
2241 seq_printf(s, "traps\t\t%ld\t%ld\n",
2242 (unsigned long)__this_cpu_read(mipsr2emustats.traps),
2243 (unsigned long)__this_cpu_read(mipsr2bdemustats.traps));
2244 seq_printf(s, "fpus\t\t%ld\t%ld\n",
2245 (unsigned long)__this_cpu_read(mipsr2emustats.fpus),
2246 (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus));
2247 seq_printf(s, "loads\t\t%ld\t%ld\n",
2248 (unsigned long)__this_cpu_read(mipsr2emustats.loads),
2249 (unsigned long)__this_cpu_read(mipsr2bdemustats.loads));
2250 seq_printf(s, "stores\t\t%ld\t%ld\n",
2251 (unsigned long)__this_cpu_read(mipsr2emustats.stores),
2252 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores));
2253 seq_printf(s, "llsc\t\t%ld\t%ld\n",
2254 (unsigned long)__this_cpu_read(mipsr2emustats.llsc),
2255 (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc));
2256 seq_printf(s, "dsemul\t\t%ld\t%ld\n",
2257 (unsigned long)__this_cpu_read(mipsr2emustats.dsemul),
2258 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul));
2259 seq_printf(s, "jr\t\t%ld\n",
2260 (unsigned long)__this_cpu_read(mipsr2bremustats.jrs));
2261 seq_printf(s, "bltzl\t\t%ld\n",
2262 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl));
2263 seq_printf(s, "bgezl\t\t%ld\n",
2264 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl));
2265 seq_printf(s, "bltzll\t\t%ld\n",
2266 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll));
2267 seq_printf(s, "bgezll\t\t%ld\n",
2268 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll));
2269 seq_printf(s, "bltzal\t\t%ld\n",
2270 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal));
2271 seq_printf(s, "bgezal\t\t%ld\n",
2272 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal));
2273 seq_printf(s, "beql\t\t%ld\n",
2274 (unsigned long)__this_cpu_read(mipsr2bremustats.beql));
2275 seq_printf(s, "bnel\t\t%ld\n",
2276 (unsigned long)__this_cpu_read(mipsr2bremustats.bnel));
2277 seq_printf(s, "blezl\t\t%ld\n",
2278 (unsigned long)__this_cpu_read(mipsr2bremustats.blezl));
2279 seq_printf(s, "bgtzl\t\t%ld\n",
2280 (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl));
2281
2282 return 0;
2283}
2284
2285static int mipsr2_stats_clear_show(struct seq_file *s, void *unused)
2286{
2287 mipsr2_stats_show(s, unused);
2288
2289 __this_cpu_write((mipsr2emustats).movs, 0);
2290 __this_cpu_write((mipsr2bdemustats).movs, 0);
2291 __this_cpu_write((mipsr2emustats).hilo, 0);
2292 __this_cpu_write((mipsr2bdemustats).hilo, 0);
2293 __this_cpu_write((mipsr2emustats).muls, 0);
2294 __this_cpu_write((mipsr2bdemustats).muls, 0);
2295 __this_cpu_write((mipsr2emustats).divs, 0);
2296 __this_cpu_write((mipsr2bdemustats).divs, 0);
2297 __this_cpu_write((mipsr2emustats).dsps, 0);
2298 __this_cpu_write((mipsr2bdemustats).dsps, 0);
2299 __this_cpu_write((mipsr2emustats).bops, 0);
2300 __this_cpu_write((mipsr2bdemustats).bops, 0);
2301 __this_cpu_write((mipsr2emustats).traps, 0);
2302 __this_cpu_write((mipsr2bdemustats).traps, 0);
2303 __this_cpu_write((mipsr2emustats).fpus, 0);
2304 __this_cpu_write((mipsr2bdemustats).fpus, 0);
2305 __this_cpu_write((mipsr2emustats).loads, 0);
2306 __this_cpu_write((mipsr2bdemustats).loads, 0);
2307 __this_cpu_write((mipsr2emustats).stores, 0);
2308 __this_cpu_write((mipsr2bdemustats).stores, 0);
2309 __this_cpu_write((mipsr2emustats).llsc, 0);
2310 __this_cpu_write((mipsr2bdemustats).llsc, 0);
2311 __this_cpu_write((mipsr2emustats).dsemul, 0);
2312 __this_cpu_write((mipsr2bdemustats).dsemul, 0);
2313 __this_cpu_write((mipsr2bremustats).jrs, 0);
2314 __this_cpu_write((mipsr2bremustats).bltzl, 0);
2315 __this_cpu_write((mipsr2bremustats).bgezl, 0);
2316 __this_cpu_write((mipsr2bremustats).bltzll, 0);
2317 __this_cpu_write((mipsr2bremustats).bgezll, 0);
2318 __this_cpu_write((mipsr2bremustats).bltzal, 0);
2319 __this_cpu_write((mipsr2bremustats).bgezal, 0);
2320 __this_cpu_write((mipsr2bremustats).beql, 0);
2321 __this_cpu_write((mipsr2bremustats).bnel, 0);
2322 __this_cpu_write((mipsr2bremustats).blezl, 0);
2323 __this_cpu_write((mipsr2bremustats).bgtzl, 0);
2324
2325 return 0;
2326}
2327
2328static int mipsr2_stats_open(struct inode *inode, struct file *file)
2329{
2330 return single_open(file, mipsr2_stats_show, inode->i_private);
2331}
2332
2333static int mipsr2_stats_clear_open(struct inode *inode, struct file *file)
2334{
2335 return single_open(file, mipsr2_stats_clear_show, inode->i_private);
2336}
2337
2338static const struct file_operations mipsr2_emul_fops = {
2339 .open = mipsr2_stats_open,
2340 .read = seq_read,
2341 .llseek = seq_lseek,
2342 .release = single_release,
2343};
2344
2345static const struct file_operations mipsr2_clear_fops = {
2346 .open = mipsr2_stats_clear_open,
2347 .read = seq_read,
2348 .llseek = seq_lseek,
2349 .release = single_release,
2350};
2351
2352
2353static int __init mipsr2_init_debugfs(void)
2354{
2355 extern struct dentry *mips_debugfs_dir;
2356 struct dentry *mipsr2_emul;
2357
2358 if (!mips_debugfs_dir)
2359 return -ENODEV;
2360
2361 mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO,
2362 mips_debugfs_dir, NULL,
2363 &mipsr2_emul_fops);
2364 if (!mipsr2_emul)
2365 return -ENOMEM;
2366
2367 mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO,
2368 mips_debugfs_dir, NULL,
2369 &mipsr2_clear_fops);
2370 if (!mipsr2_emul)
2371 return -ENOMEM;
2372
2373 return 0;
2374}
2375
2376device_initcall(mipsr2_init_debugfs);
2377
2378#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 1a73c6c9e4b7..291af0b5c482 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -77,11 +77,13 @@ EXPORT_SYMBOL(__strnlen_kernel_asm);
77EXPORT_SYMBOL(__strnlen_user_nocheck_asm); 77EXPORT_SYMBOL(__strnlen_user_nocheck_asm);
78EXPORT_SYMBOL(__strnlen_user_asm); 78EXPORT_SYMBOL(__strnlen_user_asm);
79 79
80#ifndef CONFIG_CPU_MIPSR6
80EXPORT_SYMBOL(csum_partial); 81EXPORT_SYMBOL(csum_partial);
81EXPORT_SYMBOL(csum_partial_copy_nocheck); 82EXPORT_SYMBOL(csum_partial_copy_nocheck);
82EXPORT_SYMBOL(__csum_partial_copy_kernel); 83EXPORT_SYMBOL(__csum_partial_copy_kernel);
83EXPORT_SYMBOL(__csum_partial_copy_to_user); 84EXPORT_SYMBOL(__csum_partial_copy_to_user);
84EXPORT_SYMBOL(__csum_partial_copy_from_user); 85EXPORT_SYMBOL(__csum_partial_copy_from_user);
86#endif
85 87
86EXPORT_SYMBOL(invalid_pte_table); 88EXPORT_SYMBOL(invalid_pte_table);
87#ifdef CONFIG_FUNCTION_TRACER 89#ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 097fc8d14e42..130af7d26a9c 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -82,7 +82,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
82 seq_printf(m, "]\n"); 82 seq_printf(m, "]\n");
83 } 83 }
84 84
85 seq_printf(m, "isa\t\t\t: mips1"); 85 seq_printf(m, "isa\t\t\t:");
86 if (cpu_has_mips_r1)
87 seq_printf(m, " mips1");
86 if (cpu_has_mips_2) 88 if (cpu_has_mips_2)
87 seq_printf(m, "%s", " mips2"); 89 seq_printf(m, "%s", " mips2");
88 if (cpu_has_mips_3) 90 if (cpu_has_mips_3)
@@ -95,10 +97,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
95 seq_printf(m, "%s", " mips32r1"); 97 seq_printf(m, "%s", " mips32r1");
96 if (cpu_has_mips32r2) 98 if (cpu_has_mips32r2)
97 seq_printf(m, "%s", " mips32r2"); 99 seq_printf(m, "%s", " mips32r2");
100 if (cpu_has_mips32r6)
101 seq_printf(m, "%s", " mips32r6");
98 if (cpu_has_mips64r1) 102 if (cpu_has_mips64r1)
99 seq_printf(m, "%s", " mips64r1"); 103 seq_printf(m, "%s", " mips64r1");
100 if (cpu_has_mips64r2) 104 if (cpu_has_mips64r2)
101 seq_printf(m, "%s", " mips64r2"); 105 seq_printf(m, "%s", " mips64r2");
106 if (cpu_has_mips64r6)
107 seq_printf(m, "%s", " mips64r6");
102 seq_printf(m, "\n"); 108 seq_printf(m, "\n");
103 109
104 seq_printf(m, "ASEs implemented\t:"); 110 seq_printf(m, "ASEs implemented\t:");
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 4677b4c67da6..696d59e40fa4 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -581,6 +581,10 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
581 if ((value & PR_FP_MODE_FRE) && cpu_has_fpu && !cpu_has_fre) 581 if ((value & PR_FP_MODE_FRE) && cpu_has_fpu && !cpu_has_fre)
582 return -EOPNOTSUPP; 582 return -EOPNOTSUPP;
583 583
584 /* FR = 0 not supported in MIPS R6 */
585 if (!(value & PR_FP_MODE_FR) && cpu_has_fpu && cpu_has_mips_r6)
586 return -EOPNOTSUPP;
587
584 /* Save FP & vector context, then disable FPU & MSA */ 588 /* Save FP & vector context, then disable FPU & MSA */
585 if (task->signal == current->signal) 589 if (task->signal == current->signal)
586 lose_fpu(1); 590 lose_fpu(1);
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 6c160c67984c..676c5030a953 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -34,7 +34,7 @@
34 .endm 34 .endm
35 35
36 .set noreorder 36 .set noreorder
37 .set arch=r4000 37 .set MIPS_ISA_ARCH_LEVEL_RAW
38 38
39LEAF(_save_fp_context) 39LEAF(_save_fp_context)
40 .set push 40 .set push
@@ -42,7 +42,8 @@ LEAF(_save_fp_context)
42 cfc1 t1, fcr31 42 cfc1 t1, fcr31
43 .set pop 43 .set pop
44 44
45#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 45#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
46 defined(CONFIG_CPU_MIPS32_R6)
46 .set push 47 .set push
47 SET_HARDFLOAT 48 SET_HARDFLOAT
48#ifdef CONFIG_CPU_MIPS32_R2 49#ifdef CONFIG_CPU_MIPS32_R2
@@ -105,10 +106,12 @@ LEAF(_save_fp_context32)
105 SET_HARDFLOAT 106 SET_HARDFLOAT
106 cfc1 t1, fcr31 107 cfc1 t1, fcr31
107 108
109#ifndef CONFIG_CPU_MIPS64_R6
108 mfc0 t0, CP0_STATUS 110 mfc0 t0, CP0_STATUS
109 sll t0, t0, 5 111 sll t0, t0, 5
110 bgez t0, 1f # skip storing odd if FR=0 112 bgez t0, 1f # skip storing odd if FR=0
111 nop 113 nop
114#endif
112 115
113 /* Store the 16 odd double precision registers */ 116 /* Store the 16 odd double precision registers */
114 EX sdc1 $f1, SC32_FPREGS+8(a0) 117 EX sdc1 $f1, SC32_FPREGS+8(a0)
@@ -163,7 +166,8 @@ LEAF(_save_fp_context32)
163LEAF(_restore_fp_context) 166LEAF(_restore_fp_context)
164 EX lw t1, SC_FPC_CSR(a0) 167 EX lw t1, SC_FPC_CSR(a0)
165 168
166#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 169#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
170 defined(CONFIG_CPU_MIPS32_R6)
167 .set push 171 .set push
168 SET_HARDFLOAT 172 SET_HARDFLOAT
169#ifdef CONFIG_CPU_MIPS32_R2 173#ifdef CONFIG_CPU_MIPS32_R2
@@ -223,10 +227,12 @@ LEAF(_restore_fp_context32)
223 SET_HARDFLOAT 227 SET_HARDFLOAT
224 EX lw t1, SC32_FPC_CSR(a0) 228 EX lw t1, SC32_FPC_CSR(a0)
225 229
230#ifndef CONFIG_CPU_MIPS64_R6
226 mfc0 t0, CP0_STATUS 231 mfc0 t0, CP0_STATUS
227 sll t0, t0, 5 232 sll t0, t0, 5
228 bgez t0, 1f # skip loading odd if FR=0 233 bgez t0, 1f # skip loading odd if FR=0
229 nop 234 nop
235#endif
230 236
231 EX ldc1 $f1, SC32_FPREGS+8(a0) 237 EX ldc1 $f1, SC32_FPREGS+8(a0)
232 EX ldc1 $f3, SC32_FPREGS+24(a0) 238 EX ldc1 $f3, SC32_FPREGS+24(a0)
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 64591e671878..3b1a36f13a7d 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -115,7 +115,8 @@
115 * Save a thread's fp context. 115 * Save a thread's fp context.
116 */ 116 */
117LEAF(_save_fp) 117LEAF(_save_fp)
118#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 118#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
119 defined(CONFIG_CPU_MIPS32_R6)
119 mfc0 t0, CP0_STATUS 120 mfc0 t0, CP0_STATUS
120#endif 121#endif
121 fpu_save_double a0 t0 t1 # clobbers t1 122 fpu_save_double a0 t0 t1 # clobbers t1
@@ -126,7 +127,8 @@ LEAF(_save_fp)
126 * Restore a thread's fp context. 127 * Restore a thread's fp context.
127 */ 128 */
128LEAF(_restore_fp) 129LEAF(_restore_fp)
129#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 130#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
131 defined(CONFIG_CPU_MIPS32_R6)
130 mfc0 t0, CP0_STATUS 132 mfc0 t0, CP0_STATUS
131#endif 133#endif
132 fpu_restore_double a0 t0 t1 # clobbers t1 134 fpu_restore_double a0 t0 t1 # clobbers t1
@@ -240,9 +242,9 @@ LEAF(_init_fpu)
240 mtc1 t1, $f30 242 mtc1 t1, $f30
241 mtc1 t1, $f31 243 mtc1 t1, $f31
242 244
243#ifdef CONFIG_CPU_MIPS32_R2 245#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
244 .set push 246 .set push
245 .set mips32r2 247 .set MIPS_ISA_LEVEL_RAW
246 .set fp=64 248 .set fp=64
247 sll t0, t0, 5 # is Status.FR set? 249 sll t0, t0, 5 # is Status.FR set?
248 bgez t0, 1f # no: skip setting upper 32b 250 bgez t0, 1f # no: skip setting upper 32b
@@ -280,9 +282,9 @@ LEAF(_init_fpu)
280 mthc1 t1, $f30 282 mthc1 t1, $f30
281 mthc1 t1, $f31 283 mthc1 t1, $f31
2821: .set pop 2841: .set pop
283#endif /* CONFIG_CPU_MIPS32_R2 */ 285#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
284#else 286#else
285 .set arch=r4000 287 .set MIPS_ISA_ARCH_LEVEL_RAW
286 dmtc1 t1, $f0 288 dmtc1 t1, $f0
287 dmtc1 t1, $f2 289 dmtc1 t1, $f2
288 dmtc1 t1, $f4 290 dmtc1 t1, $f4
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 67f2495def1c..d1168d7c31e8 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -208,6 +208,7 @@ void spram_config(void)
208 case CPU_INTERAPTIV: 208 case CPU_INTERAPTIV:
209 case CPU_PROAPTIV: 209 case CPU_PROAPTIV:
210 case CPU_P5600: 210 case CPU_P5600:
211 case CPU_QEMU_GENERIC:
211 config0 = read_c0_config(); 212 config0 = read_c0_config();
212 /* FIXME: addresses are Malta specific */ 213 /* FIXME: addresses are Malta specific */
213 if (config0 & (1<<24)) { 214 if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 604b558809c4..53a7ef9a8f32 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -136,7 +136,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
136 : "memory"); 136 : "memory");
137 } else if (cpu_has_llsc) { 137 } else if (cpu_has_llsc) {
138 __asm__ __volatile__ ( 138 __asm__ __volatile__ (
139 " .set arch=r4000 \n" 139 " .set "MIPS_ISA_ARCH_LEVEL" \n"
140 " li %[err], 0 \n" 140 " li %[err], 0 \n"
141 "1: ll %[old], (%[addr]) \n" 141 "1: ll %[old], (%[addr]) \n"
142 " move %[tmp], %[new] \n" 142 " move %[tmp], %[new] \n"
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index d5fbfb51b9da..afa447e5e97f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -46,6 +46,7 @@
46#include <asm/fpu.h> 46#include <asm/fpu.h>
47#include <asm/fpu_emulator.h> 47#include <asm/fpu_emulator.h>
48#include <asm/idle.h> 48#include <asm/idle.h>
49#include <asm/mips-r2-to-r6-emul.h>
49#include <asm/mipsregs.h> 50#include <asm/mipsregs.h>
50#include <asm/mipsmtregs.h> 51#include <asm/mipsmtregs.h>
51#include <asm/module.h> 52#include <asm/module.h>
@@ -837,7 +838,7 @@ out:
837 exception_exit(prev_state); 838 exception_exit(prev_state);
838} 839}
839 840
840static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 841void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
841 const char *str) 842 const char *str)
842{ 843{
843 siginfo_t info; 844 siginfo_t info;
@@ -1027,7 +1028,34 @@ asmlinkage void do_ri(struct pt_regs *regs)
1027 unsigned int opcode = 0; 1028 unsigned int opcode = 0;
1028 int status = -1; 1029 int status = -1;
1029 1030
1031 /*
1032 * Avoid any kernel code. Just emulate the R2 instruction
1033 * as quickly as possible.
1034 */
1035 if (mipsr2_emulation && cpu_has_mips_r6 &&
1036 likely(user_mode(regs))) {
1037 if (likely(get_user(opcode, epc) >= 0)) {
1038 status = mipsr2_decoder(regs, opcode);
1039 switch (status) {
1040 case 0:
1041 case SIGEMT:
1042 task_thread_info(current)->r2_emul_return = 1;
1043 return;
1044 case SIGILL:
1045 goto no_r2_instr;
1046 default:
1047 process_fpemu_return(status,
1048 &current->thread.cp0_baduaddr);
1049 task_thread_info(current)->r2_emul_return = 1;
1050 return;
1051 }
1052 }
1053 }
1054
1055no_r2_instr:
1056
1030 prev_state = exception_enter(); 1057 prev_state = exception_enter();
1058
1031 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), 1059 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
1032 SIGILL) == NOTIFY_STOP) 1060 SIGILL) == NOTIFY_STOP)
1033 goto out; 1061 goto out;
@@ -1559,6 +1587,7 @@ static inline void parity_protection_init(void)
1559 case CPU_INTERAPTIV: 1587 case CPU_INTERAPTIV:
1560 case CPU_PROAPTIV: 1588 case CPU_PROAPTIV:
1561 case CPU_P5600: 1589 case CPU_P5600:
1590 case CPU_QEMU_GENERIC:
1562 { 1591 {
1563#define ERRCTL_PE 0x80000000 1592#define ERRCTL_PE 0x80000000
1564#define ERRCTL_L2P 0x00800000 1593#define ERRCTL_L2P 0x00800000
@@ -1648,7 +1677,7 @@ asmlinkage void cache_parity_error(void)
1648 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1677 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1649 reg_val & (1<<30) ? "secondary" : "primary", 1678 reg_val & (1<<30) ? "secondary" : "primary",
1650 reg_val & (1<<31) ? "data" : "insn"); 1679 reg_val & (1<<31) ? "data" : "insn");
1651 if (cpu_has_mips_r2 && 1680 if ((cpu_has_mips_r2_r6) &&
1652 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1681 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1653 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1682 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1654 reg_val & (1<<29) ? "ED " : "", 1683 reg_val & (1<<29) ? "ED " : "",
@@ -1688,7 +1717,7 @@ asmlinkage void do_ftlb(void)
1688 unsigned int reg_val; 1717 unsigned int reg_val;
1689 1718
1690 /* For the moment, report the problem and hang. */ 1719 /* For the moment, report the problem and hang. */
1691 if (cpu_has_mips_r2 && 1720 if ((cpu_has_mips_r2_r6) &&
1692 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1721 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1693 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1722 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1694 read_c0_ecc()); 1723 read_c0_ecc());
@@ -1977,7 +2006,7 @@ static void configure_hwrena(void)
1977{ 2006{
1978 unsigned int hwrena = cpu_hwrena_impl_bits; 2007 unsigned int hwrena = cpu_hwrena_impl_bits;
1979 2008
1980 if (cpu_has_mips_r2) 2009 if (cpu_has_mips_r2_r6)
1981 hwrena |= 0x0000000f; 2010 hwrena |= 0x0000000f;
1982 2011
1983 if (!noulri && cpu_has_userlocal) 2012 if (!noulri && cpu_has_userlocal)
@@ -2021,7 +2050,7 @@ void per_cpu_trap_init(bool is_boot_cpu)
2021 * o read IntCtl.IPTI to determine the timer interrupt 2050 * o read IntCtl.IPTI to determine the timer interrupt
2022 * o read IntCtl.IPPCI to determine the performance counter interrupt 2051 * o read IntCtl.IPPCI to determine the performance counter interrupt
2023 */ 2052 */
2024 if (cpu_has_mips_r2) { 2053 if (cpu_has_mips_r2_r6) {
2025 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2054 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2026 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2055 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2027 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2056 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
@@ -2112,7 +2141,7 @@ void __init trap_init(void)
2112#else 2141#else
2113 ebase = CKSEG0; 2142 ebase = CKSEG0;
2114#endif 2143#endif
2115 if (cpu_has_mips_r2) 2144 if (cpu_has_mips_r2_r6)
2116 ebase += (read_c0_ebase() & 0x3ffff000); 2145 ebase += (read_c0_ebase() & 0x3ffff000);
2117 } 2146 }
2118 2147
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index e11906dff885..bbb69695a0a1 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -129,6 +129,7 @@ extern void show_registers(struct pt_regs *regs);
129 : "=&r" (value), "=r" (res) \ 129 : "=&r" (value), "=r" (res) \
130 : "r" (addr), "i" (-EFAULT)); 130 : "r" (addr), "i" (-EFAULT));
131 131
132#ifndef CONFIG_CPU_MIPSR6
132#define LoadW(addr, value, res) \ 133#define LoadW(addr, value, res) \
133 __asm__ __volatile__ ( \ 134 __asm__ __volatile__ ( \
134 "1:\t"user_lwl("%0", "(%2)")"\n" \ 135 "1:\t"user_lwl("%0", "(%2)")"\n" \
@@ -146,6 +147,39 @@ extern void show_registers(struct pt_regs *regs);
146 ".previous" \ 147 ".previous" \
147 : "=&r" (value), "=r" (res) \ 148 : "=&r" (value), "=r" (res) \
148 : "r" (addr), "i" (-EFAULT)); 149 : "r" (addr), "i" (-EFAULT));
150#else
151/* MIPSR6 has no lwl instruction */
152#define LoadW(addr, value, res) \
153 __asm__ __volatile__ ( \
154 ".set\tpush\n" \
155 ".set\tnoat\n\t" \
156 "1:"user_lb("%0", "0(%2)")"\n\t" \
157 "2:"user_lbu("$1", "1(%2)")"\n\t" \
158 "sll\t%0, 0x8\n\t" \
159 "or\t%0, $1\n\t" \
160 "3:"user_lbu("$1", "2(%2)")"\n\t" \
161 "sll\t%0, 0x8\n\t" \
162 "or\t%0, $1\n\t" \
163 "4:"user_lbu("$1", "3(%2)")"\n\t" \
164 "sll\t%0, 0x8\n\t" \
165 "or\t%0, $1\n\t" \
166 "li\t%1, 0\n" \
167 ".set\tpop\n" \
168 "10:\n\t" \
169 ".insn\n\t" \
170 ".section\t.fixup,\"ax\"\n\t" \
171 "11:\tli\t%1, %3\n\t" \
172 "j\t10b\n\t" \
173 ".previous\n\t" \
174 ".section\t__ex_table,\"a\"\n\t" \
175 STR(PTR)"\t1b, 11b\n\t" \
176 STR(PTR)"\t2b, 11b\n\t" \
177 STR(PTR)"\t3b, 11b\n\t" \
178 STR(PTR)"\t4b, 11b\n\t" \
179 ".previous" \
180 : "=&r" (value), "=r" (res) \
181 : "r" (addr), "i" (-EFAULT));
182#endif /* CONFIG_CPU_MIPSR6 */
149 183
150#define LoadHWU(addr, value, res) \ 184#define LoadHWU(addr, value, res) \
151 __asm__ __volatile__ ( \ 185 __asm__ __volatile__ ( \
@@ -169,6 +203,7 @@ extern void show_registers(struct pt_regs *regs);
169 : "=&r" (value), "=r" (res) \ 203 : "=&r" (value), "=r" (res) \
170 : "r" (addr), "i" (-EFAULT)); 204 : "r" (addr), "i" (-EFAULT));
171 205
206#ifndef CONFIG_CPU_MIPSR6
172#define LoadWU(addr, value, res) \ 207#define LoadWU(addr, value, res) \
173 __asm__ __volatile__ ( \ 208 __asm__ __volatile__ ( \
174 "1:\t"user_lwl("%0", "(%2)")"\n" \ 209 "1:\t"user_lwl("%0", "(%2)")"\n" \
@@ -206,6 +241,87 @@ extern void show_registers(struct pt_regs *regs);
206 ".previous" \ 241 ".previous" \
207 : "=&r" (value), "=r" (res) \ 242 : "=&r" (value), "=r" (res) \
208 : "r" (addr), "i" (-EFAULT)); 243 : "r" (addr), "i" (-EFAULT));
244#else
245/* MIPSR6 has not lwl and ldl instructions */
246#define LoadWU(addr, value, res) \
247 __asm__ __volatile__ ( \
248 ".set\tpush\n\t" \
249 ".set\tnoat\n\t" \
250 "1:"user_lbu("%0", "0(%2)")"\n\t" \
251 "2:"user_lbu("$1", "1(%2)")"\n\t" \
252 "sll\t%0, 0x8\n\t" \
253 "or\t%0, $1\n\t" \
254 "3:"user_lbu("$1", "2(%2)")"\n\t" \
255 "sll\t%0, 0x8\n\t" \
256 "or\t%0, $1\n\t" \
257 "4:"user_lbu("$1", "3(%2)")"\n\t" \
258 "sll\t%0, 0x8\n\t" \
259 "or\t%0, $1\n\t" \
260 "li\t%1, 0\n" \
261 ".set\tpop\n" \
262 "10:\n\t" \
263 ".insn\n\t" \
264 ".section\t.fixup,\"ax\"\n\t" \
265 "11:\tli\t%1, %3\n\t" \
266 "j\t10b\n\t" \
267 ".previous\n\t" \
268 ".section\t__ex_table,\"a\"\n\t" \
269 STR(PTR)"\t1b, 11b\n\t" \
270 STR(PTR)"\t2b, 11b\n\t" \
271 STR(PTR)"\t3b, 11b\n\t" \
272 STR(PTR)"\t4b, 11b\n\t" \
273 ".previous" \
274 : "=&r" (value), "=r" (res) \
275 : "r" (addr), "i" (-EFAULT));
276
277#define LoadDW(addr, value, res) \
278 __asm__ __volatile__ ( \
279 ".set\tpush\n\t" \
280 ".set\tnoat\n\t" \
281 "1:lb\t%0, 0(%2)\n\t" \
282 "2:lbu\t $1, 1(%2)\n\t" \
283 "dsll\t%0, 0x8\n\t" \
284 "or\t%0, $1\n\t" \
285 "3:lbu\t$1, 2(%2)\n\t" \
286 "dsll\t%0, 0x8\n\t" \
287 "or\t%0, $1\n\t" \
288 "4:lbu\t$1, 3(%2)\n\t" \
289 "dsll\t%0, 0x8\n\t" \
290 "or\t%0, $1\n\t" \
291 "5:lbu\t$1, 4(%2)\n\t" \
292 "dsll\t%0, 0x8\n\t" \
293 "or\t%0, $1\n\t" \
294 "6:lbu\t$1, 5(%2)\n\t" \
295 "dsll\t%0, 0x8\n\t" \
296 "or\t%0, $1\n\t" \
297 "7:lbu\t$1, 6(%2)\n\t" \
298 "dsll\t%0, 0x8\n\t" \
299 "or\t%0, $1\n\t" \
300 "8:lbu\t$1, 7(%2)\n\t" \
301 "dsll\t%0, 0x8\n\t" \
302 "or\t%0, $1\n\t" \
303 "li\t%1, 0\n" \
304 ".set\tpop\n\t" \
305 "10:\n\t" \
306 ".insn\n\t" \
307 ".section\t.fixup,\"ax\"\n\t" \
308 "11:\tli\t%1, %3\n\t" \
309 "j\t10b\n\t" \
310 ".previous\n\t" \
311 ".section\t__ex_table,\"a\"\n\t" \
312 STR(PTR)"\t1b, 11b\n\t" \
313 STR(PTR)"\t2b, 11b\n\t" \
314 STR(PTR)"\t3b, 11b\n\t" \
315 STR(PTR)"\t4b, 11b\n\t" \
316 STR(PTR)"\t5b, 11b\n\t" \
317 STR(PTR)"\t6b, 11b\n\t" \
318 STR(PTR)"\t7b, 11b\n\t" \
319 STR(PTR)"\t8b, 11b\n\t" \
320 ".previous" \
321 : "=&r" (value), "=r" (res) \
322 : "r" (addr), "i" (-EFAULT));
323#endif /* CONFIG_CPU_MIPSR6 */
324
209 325
210#define StoreHW(addr, value, res) \ 326#define StoreHW(addr, value, res) \
211 __asm__ __volatile__ ( \ 327 __asm__ __volatile__ ( \
@@ -228,6 +344,7 @@ extern void show_registers(struct pt_regs *regs);
228 : "=r" (res) \ 344 : "=r" (res) \
229 : "r" (value), "r" (addr), "i" (-EFAULT)); 345 : "r" (value), "r" (addr), "i" (-EFAULT));
230 346
347#ifndef CONFIG_CPU_MIPSR6
231#define StoreW(addr, value, res) \ 348#define StoreW(addr, value, res) \
232 __asm__ __volatile__ ( \ 349 __asm__ __volatile__ ( \
233 "1:\t"user_swl("%1", "(%2)")"\n" \ 350 "1:\t"user_swl("%1", "(%2)")"\n" \
@@ -263,9 +380,82 @@ extern void show_registers(struct pt_regs *regs);
263 ".previous" \ 380 ".previous" \
264 : "=r" (res) \ 381 : "=r" (res) \
265 : "r" (value), "r" (addr), "i" (-EFAULT)); 382 : "r" (value), "r" (addr), "i" (-EFAULT));
266#endif 383#else
384/* MIPSR6 has no swl and sdl instructions */
385#define StoreW(addr, value, res) \
386 __asm__ __volatile__ ( \
387 ".set\tpush\n\t" \
388 ".set\tnoat\n\t" \
389 "1:"user_sb("%1", "3(%2)")"\n\t" \
390 "srl\t$1, %1, 0x8\n\t" \
391 "2:"user_sb("$1", "2(%2)")"\n\t" \
392 "srl\t$1, $1, 0x8\n\t" \
393 "3:"user_sb("$1", "1(%2)")"\n\t" \
394 "srl\t$1, $1, 0x8\n\t" \
395 "4:"user_sb("$1", "0(%2)")"\n\t" \
396 ".set\tpop\n\t" \
397 "li\t%0, 0\n" \
398 "10:\n\t" \
399 ".insn\n\t" \
400 ".section\t.fixup,\"ax\"\n\t" \
401 "11:\tli\t%0, %3\n\t" \
402 "j\t10b\n\t" \
403 ".previous\n\t" \
404 ".section\t__ex_table,\"a\"\n\t" \
405 STR(PTR)"\t1b, 11b\n\t" \
406 STR(PTR)"\t2b, 11b\n\t" \
407 STR(PTR)"\t3b, 11b\n\t" \
408 STR(PTR)"\t4b, 11b\n\t" \
409 ".previous" \
410 : "=&r" (res) \
411 : "r" (value), "r" (addr), "i" (-EFAULT) \
412 : "memory");
413
414#define StoreDW(addr, value, res) \
415 __asm__ __volatile__ ( \
416 ".set\tpush\n\t" \
417 ".set\tnoat\n\t" \
418 "1:sb\t%1, 7(%2)\n\t" \
419 "dsrl\t$1, %1, 0x8\n\t" \
420 "2:sb\t$1, 6(%2)\n\t" \
421 "dsrl\t$1, $1, 0x8\n\t" \
422 "3:sb\t$1, 5(%2)\n\t" \
423 "dsrl\t$1, $1, 0x8\n\t" \
424 "4:sb\t$1, 4(%2)\n\t" \
425 "dsrl\t$1, $1, 0x8\n\t" \
426 "5:sb\t$1, 3(%2)\n\t" \
427 "dsrl\t$1, $1, 0x8\n\t" \
428 "6:sb\t$1, 2(%2)\n\t" \
429 "dsrl\t$1, $1, 0x8\n\t" \
430 "7:sb\t$1, 1(%2)\n\t" \
431 "dsrl\t$1, $1, 0x8\n\t" \
432 "8:sb\t$1, 0(%2)\n\t" \
433 "dsrl\t$1, $1, 0x8\n\t" \
434 ".set\tpop\n\t" \
435 "li\t%0, 0\n" \
436 "10:\n\t" \
437 ".insn\n\t" \
438 ".section\t.fixup,\"ax\"\n\t" \
439 "11:\tli\t%0, %3\n\t" \
440 "j\t10b\n\t" \
441 ".previous\n\t" \
442 ".section\t__ex_table,\"a\"\n\t" \
443 STR(PTR)"\t1b, 11b\n\t" \
444 STR(PTR)"\t2b, 11b\n\t" \
445 STR(PTR)"\t3b, 11b\n\t" \
446 STR(PTR)"\t4b, 11b\n\t" \
447 STR(PTR)"\t5b, 11b\n\t" \
448 STR(PTR)"\t6b, 11b\n\t" \
449 STR(PTR)"\t7b, 11b\n\t" \
450 STR(PTR)"\t8b, 11b\n\t" \
451 ".previous" \
452 : "=&r" (res) \
453 : "r" (value), "r" (addr), "i" (-EFAULT) \
454 : "memory");
455#endif /* CONFIG_CPU_MIPSR6 */
456
457#else /* __BIG_ENDIAN */
267 458
268#ifdef __LITTLE_ENDIAN
269#define LoadHW(addr, value, res) \ 459#define LoadHW(addr, value, res) \
270 __asm__ __volatile__ (".set\tnoat\n" \ 460 __asm__ __volatile__ (".set\tnoat\n" \
271 "1:\t"user_lb("%0", "1(%2)")"\n" \ 461 "1:\t"user_lb("%0", "1(%2)")"\n" \
@@ -286,6 +476,7 @@ extern void show_registers(struct pt_regs *regs);
286 : "=&r" (value), "=r" (res) \ 476 : "=&r" (value), "=r" (res) \
287 : "r" (addr), "i" (-EFAULT)); 477 : "r" (addr), "i" (-EFAULT));
288 478
479#ifndef CONFIG_CPU_MIPSR6
289#define LoadW(addr, value, res) \ 480#define LoadW(addr, value, res) \
290 __asm__ __volatile__ ( \ 481 __asm__ __volatile__ ( \
291 "1:\t"user_lwl("%0", "3(%2)")"\n" \ 482 "1:\t"user_lwl("%0", "3(%2)")"\n" \
@@ -303,6 +494,40 @@ extern void show_registers(struct pt_regs *regs);
303 ".previous" \ 494 ".previous" \
304 : "=&r" (value), "=r" (res) \ 495 : "=&r" (value), "=r" (res) \
305 : "r" (addr), "i" (-EFAULT)); 496 : "r" (addr), "i" (-EFAULT));
497#else
498/* MIPSR6 has no lwl instruction */
499#define LoadW(addr, value, res) \
500 __asm__ __volatile__ ( \
501 ".set\tpush\n" \
502 ".set\tnoat\n\t" \
503 "1:"user_lb("%0", "3(%2)")"\n\t" \
504 "2:"user_lbu("$1", "2(%2)")"\n\t" \
505 "sll\t%0, 0x8\n\t" \
506 "or\t%0, $1\n\t" \
507 "3:"user_lbu("$1", "1(%2)")"\n\t" \
508 "sll\t%0, 0x8\n\t" \
509 "or\t%0, $1\n\t" \
510 "4:"user_lbu("$1", "0(%2)")"\n\t" \
511 "sll\t%0, 0x8\n\t" \
512 "or\t%0, $1\n\t" \
513 "li\t%1, 0\n" \
514 ".set\tpop\n" \
515 "10:\n\t" \
516 ".insn\n\t" \
517 ".section\t.fixup,\"ax\"\n\t" \
518 "11:\tli\t%1, %3\n\t" \
519 "j\t10b\n\t" \
520 ".previous\n\t" \
521 ".section\t__ex_table,\"a\"\n\t" \
522 STR(PTR)"\t1b, 11b\n\t" \
523 STR(PTR)"\t2b, 11b\n\t" \
524 STR(PTR)"\t3b, 11b\n\t" \
525 STR(PTR)"\t4b, 11b\n\t" \
526 ".previous" \
527 : "=&r" (value), "=r" (res) \
528 : "r" (addr), "i" (-EFAULT));
529#endif /* CONFIG_CPU_MIPSR6 */
530
306 531
307#define LoadHWU(addr, value, res) \ 532#define LoadHWU(addr, value, res) \
308 __asm__ __volatile__ ( \ 533 __asm__ __volatile__ ( \
@@ -326,6 +551,7 @@ extern void show_registers(struct pt_regs *regs);
326 : "=&r" (value), "=r" (res) \ 551 : "=&r" (value), "=r" (res) \
327 : "r" (addr), "i" (-EFAULT)); 552 : "r" (addr), "i" (-EFAULT));
328 553
554#ifndef CONFIG_CPU_MIPSR6
329#define LoadWU(addr, value, res) \ 555#define LoadWU(addr, value, res) \
330 __asm__ __volatile__ ( \ 556 __asm__ __volatile__ ( \
331 "1:\t"user_lwl("%0", "3(%2)")"\n" \ 557 "1:\t"user_lwl("%0", "3(%2)")"\n" \
@@ -363,6 +589,86 @@ extern void show_registers(struct pt_regs *regs);
363 ".previous" \ 589 ".previous" \
364 : "=&r" (value), "=r" (res) \ 590 : "=&r" (value), "=r" (res) \
365 : "r" (addr), "i" (-EFAULT)); 591 : "r" (addr), "i" (-EFAULT));
592#else
593/* MIPSR6 has not lwl and ldl instructions */
594#define LoadWU(addr, value, res) \
595 __asm__ __volatile__ ( \
596 ".set\tpush\n\t" \
597 ".set\tnoat\n\t" \
598 "1:"user_lbu("%0", "3(%2)")"\n\t" \
599 "2:"user_lbu("$1", "2(%2)")"\n\t" \
600 "sll\t%0, 0x8\n\t" \
601 "or\t%0, $1\n\t" \
602 "3:"user_lbu("$1", "1(%2)")"\n\t" \
603 "sll\t%0, 0x8\n\t" \
604 "or\t%0, $1\n\t" \
605 "4:"user_lbu("$1", "0(%2)")"\n\t" \
606 "sll\t%0, 0x8\n\t" \
607 "or\t%0, $1\n\t" \
608 "li\t%1, 0\n" \
609 ".set\tpop\n" \
610 "10:\n\t" \
611 ".insn\n\t" \
612 ".section\t.fixup,\"ax\"\n\t" \
613 "11:\tli\t%1, %3\n\t" \
614 "j\t10b\n\t" \
615 ".previous\n\t" \
616 ".section\t__ex_table,\"a\"\n\t" \
617 STR(PTR)"\t1b, 11b\n\t" \
618 STR(PTR)"\t2b, 11b\n\t" \
619 STR(PTR)"\t3b, 11b\n\t" \
620 STR(PTR)"\t4b, 11b\n\t" \
621 ".previous" \
622 : "=&r" (value), "=r" (res) \
623 : "r" (addr), "i" (-EFAULT));
624
625#define LoadDW(addr, value, res) \
626 __asm__ __volatile__ ( \
627 ".set\tpush\n\t" \
628 ".set\tnoat\n\t" \
629 "1:lb\t%0, 7(%2)\n\t" \
630 "2:lbu\t$1, 6(%2)\n\t" \
631 "dsll\t%0, 0x8\n\t" \
632 "or\t%0, $1\n\t" \
633 "3:lbu\t$1, 5(%2)\n\t" \
634 "dsll\t%0, 0x8\n\t" \
635 "or\t%0, $1\n\t" \
636 "4:lbu\t$1, 4(%2)\n\t" \
637 "dsll\t%0, 0x8\n\t" \
638 "or\t%0, $1\n\t" \
639 "5:lbu\t$1, 3(%2)\n\t" \
640 "dsll\t%0, 0x8\n\t" \
641 "or\t%0, $1\n\t" \
642 "6:lbu\t$1, 2(%2)\n\t" \
643 "dsll\t%0, 0x8\n\t" \
644 "or\t%0, $1\n\t" \
645 "7:lbu\t$1, 1(%2)\n\t" \
646 "dsll\t%0, 0x8\n\t" \
647 "or\t%0, $1\n\t" \
648 "8:lbu\t$1, 0(%2)\n\t" \
649 "dsll\t%0, 0x8\n\t" \
650 "or\t%0, $1\n\t" \
651 "li\t%1, 0\n" \
652 ".set\tpop\n\t" \
653 "10:\n\t" \
654 ".insn\n\t" \
655 ".section\t.fixup,\"ax\"\n\t" \
656 "11:\tli\t%1, %3\n\t" \
657 "j\t10b\n\t" \
658 ".previous\n\t" \
659 ".section\t__ex_table,\"a\"\n\t" \
660 STR(PTR)"\t1b, 11b\n\t" \
661 STR(PTR)"\t2b, 11b\n\t" \
662 STR(PTR)"\t3b, 11b\n\t" \
663 STR(PTR)"\t4b, 11b\n\t" \
664 STR(PTR)"\t5b, 11b\n\t" \
665 STR(PTR)"\t6b, 11b\n\t" \
666 STR(PTR)"\t7b, 11b\n\t" \
667 STR(PTR)"\t8b, 11b\n\t" \
668 ".previous" \
669 : "=&r" (value), "=r" (res) \
670 : "r" (addr), "i" (-EFAULT));
671#endif /* CONFIG_CPU_MIPSR6 */
366 672
367#define StoreHW(addr, value, res) \ 673#define StoreHW(addr, value, res) \
368 __asm__ __volatile__ ( \ 674 __asm__ __volatile__ ( \
@@ -384,7 +690,7 @@ extern void show_registers(struct pt_regs *regs);
384 ".previous" \ 690 ".previous" \
385 : "=r" (res) \ 691 : "=r" (res) \
386 : "r" (value), "r" (addr), "i" (-EFAULT)); 692 : "r" (value), "r" (addr), "i" (-EFAULT));
387 693#ifndef CONFIG_CPU_MIPSR6
388#define StoreW(addr, value, res) \ 694#define StoreW(addr, value, res) \
389 __asm__ __volatile__ ( \ 695 __asm__ __volatile__ ( \
390 "1:\t"user_swl("%1", "3(%2)")"\n" \ 696 "1:\t"user_swl("%1", "3(%2)")"\n" \
@@ -420,6 +726,79 @@ extern void show_registers(struct pt_regs *regs);
420 ".previous" \ 726 ".previous" \
421 : "=r" (res) \ 727 : "=r" (res) \
422 : "r" (value), "r" (addr), "i" (-EFAULT)); 728 : "r" (value), "r" (addr), "i" (-EFAULT));
729#else
730/* MIPSR6 has no swl and sdl instructions */
731#define StoreW(addr, value, res) \
732 __asm__ __volatile__ ( \
733 ".set\tpush\n\t" \
734 ".set\tnoat\n\t" \
735 "1:"user_sb("%1", "0(%2)")"\n\t" \
736 "srl\t$1, %1, 0x8\n\t" \
737 "2:"user_sb("$1", "1(%2)")"\n\t" \
738 "srl\t$1, $1, 0x8\n\t" \
739 "3:"user_sb("$1", "2(%2)")"\n\t" \
740 "srl\t$1, $1, 0x8\n\t" \
741 "4:"user_sb("$1", "3(%2)")"\n\t" \
742 ".set\tpop\n\t" \
743 "li\t%0, 0\n" \
744 "10:\n\t" \
745 ".insn\n\t" \
746 ".section\t.fixup,\"ax\"\n\t" \
747 "11:\tli\t%0, %3\n\t" \
748 "j\t10b\n\t" \
749 ".previous\n\t" \
750 ".section\t__ex_table,\"a\"\n\t" \
751 STR(PTR)"\t1b, 11b\n\t" \
752 STR(PTR)"\t2b, 11b\n\t" \
753 STR(PTR)"\t3b, 11b\n\t" \
754 STR(PTR)"\t4b, 11b\n\t" \
755 ".previous" \
756 : "=&r" (res) \
757 : "r" (value), "r" (addr), "i" (-EFAULT) \
758 : "memory");
759
760#define StoreDW(addr, value, res) \
761 __asm__ __volatile__ ( \
762 ".set\tpush\n\t" \
763 ".set\tnoat\n\t" \
764 "1:sb\t%1, 0(%2)\n\t" \
765 "dsrl\t$1, %1, 0x8\n\t" \
766 "2:sb\t$1, 1(%2)\n\t" \
767 "dsrl\t$1, $1, 0x8\n\t" \
768 "3:sb\t$1, 2(%2)\n\t" \
769 "dsrl\t$1, $1, 0x8\n\t" \
770 "4:sb\t$1, 3(%2)\n\t" \
771 "dsrl\t$1, $1, 0x8\n\t" \
772 "5:sb\t$1, 4(%2)\n\t" \
773 "dsrl\t$1, $1, 0x8\n\t" \
774 "6:sb\t$1, 5(%2)\n\t" \
775 "dsrl\t$1, $1, 0x8\n\t" \
776 "7:sb\t$1, 6(%2)\n\t" \
777 "dsrl\t$1, $1, 0x8\n\t" \
778 "8:sb\t$1, 7(%2)\n\t" \
779 "dsrl\t$1, $1, 0x8\n\t" \
780 ".set\tpop\n\t" \
781 "li\t%0, 0\n" \
782 "10:\n\t" \
783 ".insn\n\t" \
784 ".section\t.fixup,\"ax\"\n\t" \
785 "11:\tli\t%0, %3\n\t" \
786 "j\t10b\n\t" \
787 ".previous\n\t" \
788 ".section\t__ex_table,\"a\"\n\t" \
789 STR(PTR)"\t1b, 11b\n\t" \
790 STR(PTR)"\t2b, 11b\n\t" \
791 STR(PTR)"\t3b, 11b\n\t" \
792 STR(PTR)"\t4b, 11b\n\t" \
793 STR(PTR)"\t5b, 11b\n\t" \
794 STR(PTR)"\t6b, 11b\n\t" \
795 STR(PTR)"\t7b, 11b\n\t" \
796 STR(PTR)"\t8b, 11b\n\t" \
797 ".previous" \
798 : "=&r" (res) \
799 : "r" (value), "r" (addr), "i" (-EFAULT) \
800 : "memory");
801#endif /* CONFIG_CPU_MIPSR6 */
423#endif 802#endif
424 803
425static void emulate_load_store_insn(struct pt_regs *regs, 804static void emulate_load_store_insn(struct pt_regs *regs,
@@ -703,10 +1082,13 @@ static void emulate_load_store_insn(struct pt_regs *regs,
703 break; 1082 break;
704 return; 1083 return;
705 1084
1085#ifndef CONFIG_CPU_MIPSR6
706 /* 1086 /*
707 * COP2 is available to implementor for application specific use. 1087 * COP2 is available to implementor for application specific use.
708 * It's up to applications to register a notifier chain and do 1088 * It's up to applications to register a notifier chain and do
709 * whatever they have to do, including possible sending of signals. 1089 * whatever they have to do, including possible sending of signals.
1090 *
1091 * This instruction has been reallocated in Release 6
710 */ 1092 */
711 case lwc2_op: 1093 case lwc2_op:
712 cu2_notifier_call_chain(CU2_LWC2_OP, regs); 1094 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
@@ -723,7 +1105,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
723 case sdc2_op: 1105 case sdc2_op:
724 cu2_notifier_call_chain(CU2_SDC2_OP, regs); 1106 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
725 break; 1107 break;
726 1108#endif
727 default: 1109 default:
728 /* 1110 /*
729 * Pheeee... We encountered an yet unknown instruction or 1111 * Pheeee... We encountered an yet unknown instruction or
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 21:24:15 -0400