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authorDavid Daney <ddaney@avtrex.com>2008-09-23 03:07:16 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:56 -0400
commit654f57bfb467996fb730eae96dc30ea4de989fdc (patch)
tree20843169f98a37ffe4908486de587a5817653140 /arch/mips/kernel
parent6aa3524c182c01b8b8b7c21c4da20c742a9b4d86 (diff)
MIPS: Probe watch registers and report configuration.
Probe for watch register characteristics, and report them in /proc/cpuinfo. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c2
-rw-r--r--arch/mips/kernel/proc.c13
2 files changed, 13 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e621fda8ab37..0cf15457ecac 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -21,6 +21,7 @@
21#include <asm/fpu.h> 21#include <asm/fpu.h>
22#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
23#include <asm/system.h> 23#include <asm/system.h>
24#include <asm/watch.h>
24 25
25/* 26/*
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -677,6 +678,7 @@ static inline void spram_config(void) {}
677static inline void cpu_probe_mips(struct cpuinfo_mips *c) 678static inline void cpu_probe_mips(struct cpuinfo_mips *c)
678{ 679{
679 decode_configs(c); 680 decode_configs(c);
681 mips_probe_watch_registers(c);
680 switch (c->processor_id & 0xff00) { 682 switch (c->processor_id & 0xff00) {
681 case PRID_IMP_4KC: 683 case PRID_IMP_4KC:
682 c->cputype = CPU_4KC; 684 c->cputype = CPU_4KC;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 36f065398243..75bb1300dd7a 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -23,6 +23,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
23 unsigned int version = cpu_data[n].processor_id; 23 unsigned int version = cpu_data[n].processor_id;
24 unsigned int fp_vers = cpu_data[n].fpu_id; 24 unsigned int fp_vers = cpu_data[n].fpu_id;
25 char fmt [64]; 25 char fmt [64];
26 int i;
26 27
27#ifdef CONFIG_SMP 28#ifdef CONFIG_SMP
28 if (!cpu_isset(n, cpu_online_map)) 29 if (!cpu_isset(n, cpu_online_map))
@@ -50,8 +51,16 @@ static int show_cpuinfo(struct seq_file *m, void *v)
50 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); 51 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
51 seq_printf(m, "extra interrupt vector\t: %s\n", 52 seq_printf(m, "extra interrupt vector\t: %s\n",
52 cpu_has_divec ? "yes" : "no"); 53 cpu_has_divec ? "yes" : "no");
53 seq_printf(m, "hardware watchpoint\t: %s\n", 54 seq_printf(m, "hardware watchpoint\t: %s",
54 cpu_has_watch ? "yes" : "no"); 55 cpu_has_watch ? "yes, " : "no\n");
56 if (cpu_has_watch) {
57 seq_printf(m, "count: %d, address/irw mask: [",
58 cpu_data[n].watch_reg_count);
59 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
60 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
61 cpu_data[n].watch_reg_masks[i]);
62 seq_printf(m, "]\n");
63 }
55 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", 64 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
56 cpu_has_mips16 ? " mips16" : "", 65 cpu_has_mips16 ? " mips16" : "",
57 cpu_has_mdmx ? " mdmx" : "", 66 cpu_has_mdmx ? " mdmx" : "",