MIPS: Correct FP ISA requirements

Correct ISA requirements for floating-point instructions:

* the CU3 exception signifies a real COP3 instruction in MIPS I & II,

* the BC1FL and BC1TL instructions are not supported in MIPS I,

* the SQRT.fmt instructions are indeed supported in MIPS II,

* the LDC1 and SDC1 instructions are indeed supported in MIPS32r1,

* the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions
  are indeed supported in MIPS32,

* the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in
  MIPS32r2 and MIPS32r6,

* the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions
  are indeed supported in MIPS32r2 and MIPS32r6,

* the RSQRT.fmt and RECIP.fmt instructions are indeed supported in
  MIPS64r1,

Also simplify conditionals for MIPS III and MIPS IV FPU instructions and
the handling of the MOVCI minor opcode.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9700/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 11 insertions, 12 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index dc6eaf4d93ea..88f04f0d2d21 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1349,19 +1349,18 @@ asmlinkage void do_cpu(struct pt_regs *regs)
 
         case 3:
                 /*
-                 * Old (MIPS I and MIPS II) processors will set this code
-                 * for COP1X opcode instructions that replaced the original
-                 * COP3 space.  We don't limit COP1 space instructions in
-                 * the emulator according to the CPU ISA, so we want to
-                 * treat COP1X instructions consistently regardless of which
-                 * code the CPU chose.  Therefore we redirect this trap to
-                 * the FP emulator too.
-                 *
-                 * Then some newer FPU-less processors use this code
-                 * erroneously too, so they are covered by this choice
-                 * as well.
+                 * The COP3 opcode space and consequently the CP0.Status.CU3
+                 * bit and the CP0.Cause.CE=3 encoding have been removed as
+                 * of the MIPS III ISA.  From the MIPS IV and MIPS32r2 ISAs
+                 * up the space has been reused for COP1X instructions, that
+                 * are enabled by the CP0.Status.CU1 bit and consequently
+                 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
+                 * exceptions.  Some FPU-less processors that implement one
+                 * of these ISAs however use this code erroneously for COP1X
+                 * instructions.  Therefore we redirect this trap to the FP
+                 * emulator too.
                  */
-                if (raw_cpu_has_fpu) {
+                if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
                         force_sig(SIGILL, current);
                         break;
                 }