diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2014-11-21 18:22:09 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 16:47:31 -0500 |
commit | 15d45cce3a0e0716fa49c768f887c6406dfb91f7 (patch) | |
tree | e2235d1a04b61a6c2100f781474e37bda78f5770 /arch/mips/kernel | |
parent | 34adb28d500e644cc260da4ceb66ba6dc0beaf93 (diff) |
MIPS: Replace use of phys_t with phys_addr_t.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/mips-cm.c | 12 | ||||
-rw-r--r-- | arch/mips/kernel/mips-cpc.c | 4 | ||||
-rw-r--r-- | arch/mips/kernel/setup.c | 10 |
3 files changed, 13 insertions, 13 deletions
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index f76f7a08412d..85bbe9b96759 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c | |||
@@ -16,7 +16,7 @@ | |||
16 | void __iomem *mips_cm_base; | 16 | void __iomem *mips_cm_base; |
17 | void __iomem *mips_cm_l2sync_base; | 17 | void __iomem *mips_cm_l2sync_base; |
18 | 18 | ||
19 | phys_t __mips_cm_phys_base(void) | 19 | phys_addr_t __mips_cm_phys_base(void) |
20 | { | 20 | { |
21 | u32 config3 = read_c0_config3(); | 21 | u32 config3 = read_c0_config3(); |
22 | u32 cmgcr; | 22 | u32 cmgcr; |
@@ -30,10 +30,10 @@ phys_t __mips_cm_phys_base(void) | |||
30 | return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); | 30 | return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); |
31 | } | 31 | } |
32 | 32 | ||
33 | phys_t mips_cm_phys_base(void) | 33 | phys_addr_t mips_cm_phys_base(void) |
34 | __attribute__((weak, alias("__mips_cm_phys_base"))); | 34 | __attribute__((weak, alias("__mips_cm_phys_base"))); |
35 | 35 | ||
36 | phys_t __mips_cm_l2sync_phys_base(void) | 36 | phys_addr_t __mips_cm_l2sync_phys_base(void) |
37 | { | 37 | { |
38 | u32 base_reg; | 38 | u32 base_reg; |
39 | 39 | ||
@@ -49,13 +49,13 @@ phys_t __mips_cm_l2sync_phys_base(void) | |||
49 | return mips_cm_phys_base() + MIPS_CM_GCR_SIZE; | 49 | return mips_cm_phys_base() + MIPS_CM_GCR_SIZE; |
50 | } | 50 | } |
51 | 51 | ||
52 | phys_t mips_cm_l2sync_phys_base(void) | 52 | phys_addr_t mips_cm_l2sync_phys_base(void) |
53 | __attribute__((weak, alias("__mips_cm_l2sync_phys_base"))); | 53 | __attribute__((weak, alias("__mips_cm_l2sync_phys_base"))); |
54 | 54 | ||
55 | static void mips_cm_probe_l2sync(void) | 55 | static void mips_cm_probe_l2sync(void) |
56 | { | 56 | { |
57 | unsigned major_rev; | 57 | unsigned major_rev; |
58 | phys_t addr; | 58 | phys_addr_t addr; |
59 | 59 | ||
60 | /* L2-only sync was introduced with CM major revision 6 */ | 60 | /* L2-only sync was introduced with CM major revision 6 */ |
61 | major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >> | 61 | major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >> |
@@ -78,7 +78,7 @@ static void mips_cm_probe_l2sync(void) | |||
78 | 78 | ||
79 | int mips_cm_probe(void) | 79 | int mips_cm_probe(void) |
80 | { | 80 | { |
81 | phys_t addr; | 81 | phys_addr_t addr; |
82 | u32 base_reg; | 82 | u32 base_reg; |
83 | 83 | ||
84 | addr = mips_cm_phys_base(); | 84 | addr = mips_cm_phys_base(); |
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c index ba473608a347..11964501c4b0 100644 --- a/arch/mips/kernel/mips-cpc.c +++ b/arch/mips/kernel/mips-cpc.c | |||
@@ -21,7 +21,7 @@ static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock); | |||
21 | 21 | ||
22 | static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags); | 22 | static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags); |
23 | 23 | ||
24 | phys_t __weak mips_cpc_phys_base(void) | 24 | phys_addr_t __weak mips_cpc_phys_base(void) |
25 | { | 25 | { |
26 | u32 cpc_base; | 26 | u32 cpc_base; |
27 | 27 | ||
@@ -44,7 +44,7 @@ phys_t __weak mips_cpc_phys_base(void) | |||
44 | 44 | ||
45 | int mips_cpc_probe(void) | 45 | int mips_cpc_probe(void) |
46 | { | 46 | { |
47 | phys_t addr; | 47 | phys_addr_t addr; |
48 | unsigned cpu; | 48 | unsigned cpu; |
49 | 49 | ||
50 | for_each_possible_cpu(cpu) | 50 | for_each_possible_cpu(cpu) |
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index eacfd7dbe8cc..a51c023d0707 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c | |||
@@ -82,7 +82,7 @@ static struct resource data_resource = { .name = "Kernel data", }; | |||
82 | 82 | ||
83 | static void *detect_magic __initdata = detect_memory_region; | 83 | static void *detect_magic __initdata = detect_memory_region; |
84 | 84 | ||
85 | void __init add_memory_region(phys_t start, phys_t size, long type) | 85 | void __init add_memory_region(phys_addr_t start, phys_addr_t size, long type) |
86 | { | 86 | { |
87 | int x = boot_mem_map.nr_map; | 87 | int x = boot_mem_map.nr_map; |
88 | int i; | 88 | int i; |
@@ -127,10 +127,10 @@ void __init add_memory_region(phys_t start, phys_t size, long type) | |||
127 | boot_mem_map.nr_map++; | 127 | boot_mem_map.nr_map++; |
128 | } | 128 | } |
129 | 129 | ||
130 | void __init detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max) | 130 | void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max) |
131 | { | 131 | { |
132 | void *dm = &detect_magic; | 132 | void *dm = &detect_magic; |
133 | phys_t size; | 133 | phys_addr_t size; |
134 | 134 | ||
135 | for (size = sz_min; size < sz_max; size <<= 1) { | 135 | for (size = sz_min; size < sz_max; size <<= 1) { |
136 | if (!memcmp(dm, dm + size, sizeof(detect_magic))) | 136 | if (!memcmp(dm, dm + size, sizeof(detect_magic))) |
@@ -545,9 +545,9 @@ static int __init early_parse_elfcorehdr(char *p) | |||
545 | early_param("elfcorehdr", early_parse_elfcorehdr); | 545 | early_param("elfcorehdr", early_parse_elfcorehdr); |
546 | #endif | 546 | #endif |
547 | 547 | ||
548 | static void __init arch_mem_addpart(phys_t mem, phys_t end, int type) | 548 | static void __init arch_mem_addpart(phys_addr_t mem, phys_addr_t end, int type) |
549 | { | 549 | { |
550 | phys_t size; | 550 | phys_addr_t size; |
551 | int i; | 551 | int i; |
552 | 552 | ||
553 | size = end - mem; | 553 | size = end - mem; |