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authorRalf Baechle <ralf@linux-mips.org>2005-05-25 09:32:49 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:17 -0400
commit10f650db1bcc193ea07d4f8c2f07315da38ea0c4 (patch)
treea6fdabdaa8493efd8d5f14ada3cdbc67f62bfe46 /arch/mips/kernel
parentffd099bd33c97db4be698ff8d8733bd6a301f6a3 (diff)
64-bit fixes for Alchemy code ;)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index cde88285a52f..552d2b6c191e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -53,14 +53,13 @@ static void r4k_wait(void)
53/* The Au1xxx wait is available only if using 32khz counter or 53/* The Au1xxx wait is available only if using 32khz counter or
54 * external timer source, but specifically not CP0 Counter. */ 54 * external timer source, but specifically not CP0 Counter. */
55int allow_au1k_wait; 55int allow_au1k_wait;
56
56static void au1k_wait(void) 57static void au1k_wait(void)
57{ 58{
58 unsigned long addr = 0;
59 /* using the wait instruction makes CP0 counter unusable */ 59 /* using the wait instruction makes CP0 counter unusable */
60 __asm__("la %0,au1k_wait\n\t" 60 __asm__(".set mips3\n\t"
61 ".set mips3\n\t" 61 "cache 0x14, 0(%0)\n\t"
62 "cache 0x14,0(%0)\n\t" 62 "cache 0x14, 32(%0)\n\t"
63 "cache 0x14,32(%0)\n\t"
64 "sync\n\t" 63 "sync\n\t"
65 "nop\n\t" 64 "nop\n\t"
66 "wait\n\t" 65 "wait\n\t"
@@ -69,7 +68,7 @@ static void au1k_wait(void)
69 "nop\n\t" 68 "nop\n\t"
70 "nop\n\t" 69 "nop\n\t"
71 ".set mips0\n\t" 70 ".set mips0\n\t"
72 : : "r" (addr)); 71 : : "r" (au1k_wait));
73} 72}
74 73
75static inline void check_wait(void) 74static inline void check_wait(void)