aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel/traps.c
diff options
context:
space:
mode:
authorDavid Daney <david.daney@cavium.com>2012-05-15 03:04:50 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-05-16 17:34:34 -0400
commit6650df3c380e0db558dbfec63ed860402c6afb2a (patch)
treee63f022dbb69c5920fd734aecb44cf8c7a225b51 /arch/mips/kernel/traps.c
parent9cd9669bd60ee41d34d1b41d7a0b884806939d7b (diff)
MIPS: Move cache setup to setup_arch().
commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize jump-label subsystem much earlier) breaks MIPS. The jump_label_init() call was moved before trap_init() which is where we initialize flush_icache_range(). In order to be good citizens, we move cache initialization earlier so that we don't jump through a null flush_icache_range function pointer when doing the jump label initialization. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3822/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r--arch/mips/kernel/traps.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 24325780f831..8e3488afbcc1 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1490,7 +1490,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
1490 return set_vi_srs_handler(n, addr, 0); 1490 return set_vi_srs_handler(n, addr, 0);
1491} 1491}
1492 1492
1493extern void cpu_cache_init(void);
1494extern void tlb_init(void); 1493extern void tlb_init(void);
1495extern void flush_tlb_handlers(void); 1494extern void flush_tlb_handlers(void);
1496 1495
@@ -1517,7 +1516,7 @@ static int __init ulri_disable(char *s)
1517} 1516}
1518__setup("noulri", ulri_disable); 1517__setup("noulri", ulri_disable);
1519 1518
1520void __cpuinit per_cpu_trap_init(void) 1519void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
1521{ 1520{
1522 unsigned int cpu = smp_processor_id(); 1521 unsigned int cpu = smp_processor_id();
1523 unsigned int status_set = ST0_CU0; 1522 unsigned int status_set = ST0_CU0;
@@ -1616,7 +1615,9 @@ void __cpuinit per_cpu_trap_init(void)
1616#ifdef CONFIG_MIPS_MT_SMTC 1615#ifdef CONFIG_MIPS_MT_SMTC
1617 if (bootTC) { 1616 if (bootTC) {
1618#endif /* CONFIG_MIPS_MT_SMTC */ 1617#endif /* CONFIG_MIPS_MT_SMTC */
1619 cpu_cache_init(); 1618 /* Boot CPU's cache setup in setup_arch(). */
1619 if (!is_boot_cpu)
1620 cpu_cache_init();
1620 tlb_init(); 1621 tlb_init();
1621#ifdef CONFIG_MIPS_MT_SMTC 1622#ifdef CONFIG_MIPS_MT_SMTC
1622 } else if (!secondaryTC) { 1623 } else if (!secondaryTC) {
@@ -1693,7 +1694,7 @@ void __init trap_init(void)
1693 1694
1694 if (board_ebase_setup) 1695 if (board_ebase_setup)
1695 board_ebase_setup(); 1696 board_ebase_setup();
1696 per_cpu_trap_init(); 1697 per_cpu_trap_init(true);
1697 1698
1698 /* 1699 /*
1699 * Copy the generic exception handlers to their final destination. 1700 * Copy the generic exception handlers to their final destination.