Merge branch 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr

Pull MIPS updates from Ralf Baechle:
 - Support for Imgtec's Aptiv family of MIPS cores.
 - Improved detection of BCM47xx configurations.
 - Fix hiberation for certain configurations.
 - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and
   systems.
 - Detection and support for the MIPS P5600 core.
 - A few more random fixes that didn't make 3.14.
 - Support for the EVA Extended Virtual Addressing
 - Switch Alchemy to the platform PATA driver
 - Complete unification of Alchemy support
 - Allow availability of I/O cache coherency to be runtime detected
 - Improvments to multiprocessing support for Imgtec platforms
 - A few microoptimizations
 - Cleanups of FPU support
 - Paul Gortmaker's fixes for the init stuff
 - Support for seccomp

* 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits)
  MIPS: CPC: Use __raw_ memory access functions
  MIPS: CM: use __raw_ memory access functions
  MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n
  MIPS: Malta: GIC IPIs may be used without MT
  MIPS: smp-mt: Use common GIC IPI implementation
  MIPS: smp-cmp: Remove incorrect core number probe
  MIPS: Fix gigaton of warning building with microMIPS.
  MIPS: Fix core number detection for MT cores
  MIPS: MT: core_nvpes function to retrieve VPE count
  MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n
  MIPS: Lasat: Replace del_timer by del_timer_sync
  MIPS: Malta: Setup PM I/O region on boot
  MIPS: Loongson: Add a Loongson-3 default config file
  MIPS: Loongson 3: Add CPU hotplug support
  MIPS: Loongson 3: Add Loongson-3 SMP support
  MIPS: Loongson: Add Loongson-3 Kconfig options
  MIPS: Loongson: Add swiotlb to support All-Memory DMA
  MIPS: Loongson 3: Add serial port support
  MIPS: Loongson 3: Add IRQ init and dispatch support
  MIPS: Loongson 3: Add HT-linked PCI support
  ...

1 files changed, 121 insertions, 0 deletions

diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
new file mode 100644
index 000000000000..f76f7a08412d
--- /dev/null
+++ b/arch/mips/kernel/mips-cm.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/errno.h>
+
+#include <asm/mips-cm.h>
+#include <asm/mipsregs.h>
+
+void __iomem *mips_cm_base;
+void __iomem *mips_cm_l2sync_base;
+
+phys_t __mips_cm_phys_base(void)
+{
+        u32 config3 = read_c0_config3();
+        u32 cmgcr;
+
+        /* Check the CMGCRBase register is implemented */
+        if (!(config3 & MIPS_CONF3_CMGCR))
+                return 0;
+
+        /* Read the address from CMGCRBase */
+        cmgcr = read_c0_cmgcrbase();
+        return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
+}
+
+phys_t mips_cm_phys_base(void)
+        __attribute__((weak, alias("__mips_cm_phys_base")));
+
+phys_t __mips_cm_l2sync_phys_base(void)
+{
+        u32 base_reg;
+
+        /*
+         * If the L2-only sync region is already enabled then leave it at it's
+         * current location.
+         */
+        base_reg = read_gcr_l2_only_sync_base();
+        if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
+                return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;
+
+        /* Default to following the CM */
+        return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
+}
+
+phys_t mips_cm_l2sync_phys_base(void)
+        __attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
+
+static void mips_cm_probe_l2sync(void)
+{
+        unsigned major_rev;
+        phys_t addr;
+
+        /* L2-only sync was introduced with CM major revision 6 */
+        major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
+                CM_GCR_REV_MAJOR_SHF;
+        if (major_rev < 6)
+                return;
+
+        /* Find a location for the L2 sync region */
+        addr = mips_cm_l2sync_phys_base();
+        BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
+        if (!addr)
+                return;
+
+        /* Set the region base address & enable it */
+        write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);
+
+        /* Map the region */
+        mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
+}
+
+int mips_cm_probe(void)
+{
+        phys_t addr;
+        u32 base_reg;
+
+        addr = mips_cm_phys_base();
+        BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
+        if (!addr)
+                return -ENODEV;
+
+        mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
+        if (!mips_cm_base)
+                return -ENXIO;
+
+        /* sanity check that we're looking at a CM */
+        base_reg = read_gcr_base();
+        if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
+                pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
+                       (unsigned long)addr);
+                mips_cm_base = NULL;
+                return -ENODEV;
+        }
+
+        /* set default target to memory */
+        base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
+        base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
+        write_gcr_base(base_reg);
+
+        /* disable CM regions */
+        write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+
+        /* probe for an L2-only sync region */
+        mips_cm_probe_l2sync();
+
+        return 0;
+}