diff options
author | Andrew Bresticker <abrestic@chromium.org> | 2014-09-18 17:47:07 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 01:44:51 -0500 |
commit | 0f84c305351c993e4307e1e8c128d44760314e31 (patch) | |
tree | e9210f9e74933bbf2badc5867b6f23b8cfcdaef2 /arch/mips/kernel/irq_cpu.c | |
parent | 97f4ad29dae24861dc08bfea48b1b446fc195d99 (diff) |
MIPS: Always use IRQ domains for CPU IRQs
Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7799/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/irq_cpu.c')
-rw-r--r-- | arch/mips/kernel/irq_cpu.c | 36 |
1 files changed, 11 insertions, 25 deletions
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index e498f2b3646a..b097f7df7a29 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -94,28 +94,6 @@ static struct irq_chip mips_mt_cpu_irq_controller = { | |||
94 | .irq_eoi = unmask_mips_irq, | 94 | .irq_eoi = unmask_mips_irq, |
95 | }; | 95 | }; |
96 | 96 | ||
97 | void __init mips_cpu_irq_init(void) | ||
98 | { | ||
99 | int irq_base = MIPS_CPU_IRQ_BASE; | ||
100 | int i; | ||
101 | |||
102 | /* Mask interrupts. */ | ||
103 | clear_c0_status(ST0_IM); | ||
104 | clear_c0_cause(CAUSEF_IP); | ||
105 | |||
106 | /* Software interrupts are used for MT/CMT IPI */ | ||
107 | for (i = irq_base; i < irq_base + 2; i++) | ||
108 | irq_set_chip_and_handler(i, cpu_has_mipsmt ? | ||
109 | &mips_mt_cpu_irq_controller : | ||
110 | &mips_cpu_irq_controller, | ||
111 | handle_percpu_irq); | ||
112 | |||
113 | for (i = irq_base + 2; i < irq_base + 8; i++) | ||
114 | irq_set_chip_and_handler(i, &mips_cpu_irq_controller, | ||
115 | handle_percpu_irq); | ||
116 | } | ||
117 | |||
118 | #ifdef CONFIG_IRQ_DOMAIN | ||
119 | static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, | 97 | static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, |
120 | irq_hw_number_t hw) | 98 | irq_hw_number_t hw) |
121 | { | 99 | { |
@@ -138,8 +116,7 @@ static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = { | |||
138 | .xlate = irq_domain_xlate_onecell, | 116 | .xlate = irq_domain_xlate_onecell, |
139 | }; | 117 | }; |
140 | 118 | ||
141 | int __init mips_cpu_intc_init(struct device_node *of_node, | 119 | static void __init __mips_cpu_irq_init(struct device_node *of_node) |
142 | struct device_node *parent) | ||
143 | { | 120 | { |
144 | struct irq_domain *domain; | 121 | struct irq_domain *domain; |
145 | 122 | ||
@@ -151,7 +128,16 @@ int __init mips_cpu_intc_init(struct device_node *of_node, | |||
151 | &mips_cpu_intc_irq_domain_ops, NULL); | 128 | &mips_cpu_intc_irq_domain_ops, NULL); |
152 | if (!domain) | 129 | if (!domain) |
153 | panic("Failed to add irqdomain for MIPS CPU"); | 130 | panic("Failed to add irqdomain for MIPS CPU"); |
131 | } | ||
132 | |||
133 | void __init mips_cpu_irq_init(void) | ||
134 | { | ||
135 | __mips_cpu_irq_init(NULL); | ||
136 | } | ||
154 | 137 | ||
138 | int __init mips_cpu_intc_init(struct device_node *of_node, | ||
139 | struct device_node *parent) | ||
140 | { | ||
141 | __mips_cpu_irq_init(of_node); | ||
155 | return 0; | 142 | return 0; |
156 | } | 143 | } |
157 | #endif /* CONFIG_IRQ_DOMAIN */ | ||