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authorIngo Molnar <mingo@elte.hu>2008-10-13 05:05:51 -0400
committerIngo Molnar <mingo@elte.hu>2008-10-13 05:05:51 -0400
commitaccba5f3965d6a9d1bf7c1e1a7995d17e9d521b6 (patch)
tree8fb40782e79472ed882ff2098d4dd295557278ee /arch/mips/kernel/cpu-probe.c
parent6852fd9b86d05063c6ef49d2e12e061cc7f6a105 (diff)
parent4480f15b3306f43bbb0310d461142b4e897ca45b (diff)
Merge branch 'linus' into oprofile-v2
Conflicts: arch/x86/kernel/apic_32.c arch/x86/oprofile/nmi_int.c include/linux/pci_ids.h
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c28
1 files changed, 11 insertions, 17 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae3d594..0cf15457ecac 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -21,6 +21,7 @@
21#include <asm/fpu.h> 21#include <asm/fpu.h>
22#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
23#include <asm/system.h> 23#include <asm/system.h>
24#include <asm/watch.h>
24 25
25/* 26/*
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -45,18 +46,7 @@ static void r39xx_wait(void)
45 local_irq_enable(); 46 local_irq_enable();
46} 47}
47 48
48/* 49extern void r4k_wait(void);
49 * There is a race when WAIT instruction executed with interrupt
50 * enabled.
51 * But it is implementation-dependent wheter the pipelie restarts when
52 * a non-enabled interrupt is requested.
53 */
54static void r4k_wait(void)
55{
56 __asm__(" .set mips3 \n"
57 " wait \n"
58 " .set mips0 \n");
59}
60 50
61/* 51/*
62 * This variant is preferable as it allows testing need_resched and going to 52 * This variant is preferable as it allows testing need_resched and going to
@@ -65,14 +55,18 @@ static void r4k_wait(void)
65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 55 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
66 * using this version a gamble. 56 * using this version a gamble.
67 */ 57 */
68static void r4k_wait_irqoff(void) 58void r4k_wait_irqoff(void)
69{ 59{
70 local_irq_disable(); 60 local_irq_disable();
71 if (!need_resched()) 61 if (!need_resched())
72 __asm__(" .set mips3 \n" 62 __asm__(" .set push \n"
63 " .set mips3 \n"
73 " wait \n" 64 " wait \n"
74 " .set mips0 \n"); 65 " .set pop \n");
75 local_irq_enable(); 66 local_irq_enable();
67 __asm__(" .globl __pastwait \n"
68 "__pastwait: \n");
69 return;
76} 70}
77 71
78/* 72/*
@@ -128,7 +122,7 @@ static int __init wait_disable(char *s)
128 122
129__setup("nowait", wait_disable); 123__setup("nowait", wait_disable);
130 124
131static inline void check_wait(void) 125void __init check_wait(void)
132{ 126{
133 struct cpuinfo_mips *c = &current_cpu_data; 127 struct cpuinfo_mips *c = &current_cpu_data;
134 128
@@ -242,7 +236,6 @@ static inline void check_errata(void)
242 236
243void __init check_bugs32(void) 237void __init check_bugs32(void)
244{ 238{
245 check_wait();
246 check_errata(); 239 check_errata();
247} 240}
248 241
@@ -685,6 +678,7 @@ static inline void spram_config(void) {}
685static inline void cpu_probe_mips(struct cpuinfo_mips *c) 678static inline void cpu_probe_mips(struct cpuinfo_mips *c)
686{ 679{
687 decode_configs(c); 680 decode_configs(c);
681 mips_probe_watch_registers(c);
688 switch (c->processor_id & 0xff00) { 682 switch (c->processor_id & 0xff00) {
689 case PRID_IMP_4KC: 683 case PRID_IMP_4KC:
690 c->cputype = CPU_4KC; 684 c->cputype = CPU_4KC;