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authorIngo Molnar <mingo@elte.hu>2008-07-08 01:47:47 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-08 01:47:47 -0400
commit93022136fff9e6130aa128a5ed8a599e93ac813c (patch)
tree185390fb75a3d7423cc508610b76637c957205b9 /arch/mips/kernel/cevt-txx9.c
parentc49c412a47b5102516d3313d4eba38cb1e968721 (diff)
parentb7279469d66b55119784b8b9529c99c1955fe747 (diff)
Merge commit 'v2.6.26-rc9' into x86/cpu
Diffstat (limited to 'arch/mips/kernel/cevt-txx9.c')
-rw-r--r--arch/mips/kernel/cevt-txx9.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 795cb8fb0d74..b5fc4eb412d2 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr)
161 struct txx9_tmr_reg __iomem *tmrptr; 161 struct txx9_tmr_reg __iomem *tmrptr;
162 162
163 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); 163 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
164 /* Start once to make CounterResetEnable effective */
165 __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
166 /* Stop and reset the counter */
164 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); 167 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
165 __raw_writel(0, &tmrptr->tisr); 168 __raw_writel(0, &tmrptr->tisr);
166 __raw_writel(0xffffffff, &tmrptr->cpra); 169 __raw_writel(0xffffffff, &tmrptr->cpra);