MIPS: Fix build with binutils 2.24.51+

Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:

{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
  LD      arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
 uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
 arch/mips/alchemy/common/sleeper.o uses -mhard-float

To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS;  but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 6 deletions

diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 7b2df224f041..4d7d99d601cc 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -144,7 +144,7 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                 case mm_bc1t_op:
                         preempt_disable();
                         if (is_fpu_owner())
-                                asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+                                fcr31 = read_32bit_cp1_register(CP1_STATUS);
                         else
                                 fcr31 = current->thread.fpu.fcr31;
                         preempt_enable();
@@ -562,11 +562,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
         case cop1_op:
                 preempt_disable();
                 if (is_fpu_owner())
-                        asm volatile(
-                                ".set push\n"
-                                "\t.set mips1\n"
-                                "\tcfc1\t%0,$31\n"
-                                "\t.set pop" : "=r" (fcr31));
+                        fcr31 = read_32bit_cp1_register(CP1_STATUS);
                 else
                         fcr31 = current->thread.fpu.fcr31;
                 preempt_enable();