Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

1 files changed, 21 insertions, 13 deletions

diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index 7d33ff83580f..d82c0c430e03 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -43,32 +43,37 @@ static uint32_t jz_intc_saved;
 
 #define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
 
-static void intc_irq_unmask(unsigned int irq)
+static inline unsigned long intc_irq_bit(struct irq_data *data)
 {
-        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+        return (unsigned long)irq_data_get_irq_chip_data(data);
 }
 
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *data)
 {
-        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
+        writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
 }
 
-static int intc_irq_set_wake(unsigned int irq, unsigned int on)
+static void intc_irq_mask(struct irq_data *data)
+{
+        writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
 {
         if (on)
-                jz_intc_wakeup |= IRQ_BIT(irq);
+                jz_intc_wakeup |= intc_irq_bit(data);
         else
-                jz_intc_wakeup &= ~IRQ_BIT(irq);
+                jz_intc_wakeup &= ~intc_irq_bit(data);
 
         return 0;
 }
 
 static struct irq_chip intc_irq_type = {
         .name =         "INTC",
-        .mask =         intc_irq_mask,
-        .mask_ack =     intc_irq_mask,
-        .unmask =       intc_irq_unmask,
-        .set_wake =     intc_irq_set_wake,
+        .irq_mask =     intc_irq_mask,
+        .irq_mask_ack = intc_irq_mask,
+        .irq_unmask =   intc_irq_unmask,
+        .irq_set_wake = intc_irq_set_wake,
 };
 
 static irqreturn_t jz4740_cascade(int irq, void *data)
@@ -95,9 +100,12 @@ void __init arch_init_irq(void)
 
         jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
 
+        /* Mask all irqs */
+        writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
+
         for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
-                intc_irq_mask(i);
-                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+                irq_set_chip_data(i, (void *)IRQ_BIT(i));
+                irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
         }
 
         setup_irq(2, &jz4740_cascade_action);