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authorMaxime Bizon <mbizon@freebox.fr>2011-11-04 14:09:31 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:03:03 -0500
commitf61cced99347783c1f3a7464e88b855a5ca6c227 (patch)
tree2ada1d4ab8271fbf65ad207612bbcef0e3333bbb /arch/mips/include
parentd430b6c5e7b3a16ad3b4cd921b3a22b553f53ca2 (diff)
MIPS: BCM63XX: Change irq code to prepare for per-cpu peculiarity.
No functionnal change is introduced by this patch. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 3ea2681c162d..25676cdeb30f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -88,10 +88,16 @@
88#define SYS_PLL_SOFT_RESET 0x1 88#define SYS_PLL_SOFT_RESET 0x1
89 89
90/* Interrupt Mask register */ 90/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc 91#define PERF_IRQMASK_6338_REG 0xc
92#define PERF_IRQMASK_6345_REG 0xc
93#define PERF_IRQMASK_6348_REG 0xc
94#define PERF_IRQMASK_6358_REG 0xc
92 95
93/* Interrupt Status register */ 96/* Interrupt Status register */
94#define PERF_IRQSTAT_REG 0x10 97#define PERF_IRQSTAT_6338_REG 0x10
98#define PERF_IRQSTAT_6345_REG 0x10
99#define PERF_IRQSTAT_6348_REG 0x10
100#define PERF_IRQSTAT_6358_REG 0x10
95 101
96/* External Interrupt Configuration register */ 102/* External Interrupt Configuration register */
97#define PERF_EXTIRQ_CFG_REG 0x14 103#define PERF_EXTIRQ_CFG_REG 0x14