MIPS: Loongson1B: Some fixes/updates for LS1B

- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data.
   (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1)
 - Add GMAC1 support and setup MUX in terms of PHY mode.
 - Add CPUFreq support.
 - Add MUX Register Definitions.
 - Add PWM Register Definitions.
 - Update clock register bitfields according to the latest spec.
 - Update clock related stuff.

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8024/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

6 files changed, 152 insertions, 8 deletions

diff --git a/arch/mips/include/asm/mach-loongson1/cpufreq.h b/arch/mips/include/asm/mach-loongson1/cpufreq.h
new file mode 100644
index 000000000000..e7765ce30bcf
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/cpufreq.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 CPUFreq platform support.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_CPUFREQ_H
+#define __ASM_MACH_LOONGSON1_CPUFREQ_H
+
+struct plat_ls1x_cpufreq {
+        const char      *clk_name;      /* CPU clk */
+        const char      *osc_clk_name;  /* OSC clk */
+        unsigned int    max_freq;       /* in kHz */
+        unsigned int    min_freq;       /* in kHz */
+};
+
+#endif /* __ASM_MACH_LOONGSON1_CPUFREQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
index 5c437c2ba6b3..20e0c2b155dd 100644
--- a/arch/mips/include/asm/mach-loongson1/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -16,6 +16,7 @@
 #define DEFAULT_MEMSIZE                 256     /* If no memsize provided */
 
 /* Loongson 1 Register Bases */
+#define LS1X_MUX_BASE                   0x1fd00420
 #define LS1X_INTC_BASE                  0x1fd01040
 #define LS1X_EHCI_BASE                  0x1fe00000
 #define LS1X_OHCI_BASE                  0x1fe08000
@@ -31,7 +32,10 @@
 #define LS1X_I2C0_BASE                  0x1fe58000
 #define LS1X_I2C1_BASE                  0x1fe68000
 #define LS1X_I2C2_BASE                  0x1fe70000
-#define LS1X_PWM_BASE                   0x1fe5c000
+#define LS1X_PWM0_BASE                  0x1fe5c000
+#define LS1X_PWM1_BASE                  0x1fe5c010
+#define LS1X_PWM2_BASE                  0x1fe5c020
+#define LS1X_PWM3_BASE                  0x1fe5c030
 #define LS1X_WDT_BASE                   0x1fe5c060
 #define LS1X_RTC_BASE                   0x1fe64000
 #define LS1X_AC97_BASE                  0x1fe74000
@@ -39,6 +43,8 @@
 #define LS1X_CLK_BASE                   0x1fe78030
 
 #include <regs-clk.h>
+#include <regs-mux.h>
+#include <regs-pwm.h>
 #include <regs-wdt.h>
 
 #endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
index 30c13e508fff..47de55e0c835 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -13,10 +13,12 @@
 
 #include <linux/platform_device.h>
 
-extern struct platform_device ls1x_uart_device;
-extern struct platform_device ls1x_eth0_device;
-extern struct platform_device ls1x_ehci_device;
-extern struct platform_device ls1x_rtc_device;
+extern struct platform_device ls1x_uart_pdev;
+extern struct platform_device ls1x_cpufreq_pdev;
+extern struct platform_device ls1x_eth0_pdev;
+extern struct platform_device ls1x_eth1_pdev;
+extern struct platform_device ls1x_ehci_pdev;
+extern struct platform_device ls1x_rtc_pdev;
 
 extern void __init ls1x_clk_init(void);
 extern void __init ls1x_serial_setup(struct platform_device *pdev);
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index fb6a3ff9318f..ee2445b10fc3 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,15 +20,32 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN                       (0x1 << 31)
+#define DIV_DC_RST                      (0x1 << 30)
 #define DIV_CPU_EN                      (0x1 << 25)
+#define DIV_CPU_RST                     (0x1 << 24)
 #define DIV_DDR_EN                      (0x1 << 19)
+#define DIV_DDR_RST                     (0x1 << 18)
+#define RST_DC_EN                       (0x1 << 5)
+#define RST_DC                          (0x1 << 4)
+#define RST_DDR_EN                      (0x1 << 3)
+#define RST_DDR                         (0x1 << 2)
+#define RST_CPU_EN                      (0x1 << 1)
+#define RST_CPU                         0x1
 
 #define DIV_DC_SHIFT                    26
 #define DIV_CPU_SHIFT                   20
 #define DIV_DDR_SHIFT                   14
 
-#define DIV_DC_WIDTH                    5
-#define DIV_CPU_WIDTH                   5
-#define DIV_DDR_WIDTH                   5
+#define DIV_DC_WIDTH                    4
+#define DIV_CPU_WIDTH                   4
+#define DIV_DDR_WIDTH                   4
+
+#define BYPASS_DC_SHIFT                 12
+#define BYPASS_DDR_SHIFT                10
+#define BYPASS_CPU_SHIFT                8
+
+#define BYPASS_DC_WIDTH                 1
+#define BYPASS_DDR_WIDTH                1
+#define BYPASS_CPU_WIDTH                1
 
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-mux.h b/arch/mips/include/asm/mach-loongson1/regs-mux.h
new file mode 100644
index 000000000000..fb1e36efaa19
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-mux.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 MUX Register Definitions.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_MUX_H
+#define __ASM_MACH_LOONGSON1_REGS_MUX_H
+
+#define LS1X_MUX_REG(x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
+
+#define LS1X_MUX_CTRL0                  LS1X_MUX_REG(0x0)
+#define LS1X_MUX_CTRL1                  LS1X_MUX_REG(0x4)
+
+/* MUX CTRL0 Register Bits */
+#define UART0_USE_PWM23                 (0x1 << 28)
+#define UART0_USE_PWM01                 (0x1 << 27)
+#define UART1_USE_LCD0_5_6_11           (0x1 << 26)
+#define I2C2_USE_CAN1                   (0x1 << 25)
+#define I2C1_USE_CAN0                   (0x1 << 24)
+#define NAND3_USE_UART5                 (0x1 << 23)
+#define NAND3_USE_UART4                 (0x1 << 22)
+#define NAND3_USE_UART1_DAT             (0x1 << 21)
+#define NAND3_USE_UART1_CTS             (0x1 << 20)
+#define NAND3_USE_PWM23                 (0x1 << 19)
+#define NAND3_USE_PWM01                 (0x1 << 18)
+#define NAND2_USE_UART5                 (0x1 << 17)
+#define NAND2_USE_UART4                 (0x1 << 16)
+#define NAND2_USE_UART1_DAT             (0x1 << 15)
+#define NAND2_USE_UART1_CTS             (0x1 << 14)
+#define NAND2_USE_PWM23                 (0x1 << 13)
+#define NAND2_USE_PWM01                 (0x1 << 12)
+#define NAND1_USE_UART5                 (0x1 << 11)
+#define NAND1_USE_UART4                 (0x1 << 10)
+#define NAND1_USE_UART1_DAT             (0x1 << 9)
+#define NAND1_USE_UART1_CTS             (0x1 << 8)
+#define NAND1_USE_PWM23                 (0x1 << 7)
+#define NAND1_USE_PWM01                 (0x1 << 6)
+#define GMAC1_USE_UART1                 (0x1 << 4)
+#define GMAC1_USE_UART0                 (0x1 << 3)
+#define LCD_USE_UART0_DAT               (0x1 << 2)
+#define LCD_USE_UART15                  (0x1 << 1)
+#define LCD_USE_UART0                   0x1
+
+/* MUX CTRL1 Register Bits */
+#define USB_RESET                       (0x1 << 31)
+#define SPI1_CS_USE_PWM01               (0x1 << 24)
+#define SPI1_USE_CAN                    (0x1 << 23)
+#define DISABLE_DDR_CONFSPACE           (0x1 << 20)
+#define DDR32TO16EN                     (0x1 << 16)
+#define GMAC1_SHUT                      (0x1 << 13)
+#define GMAC0_SHUT                      (0x1 << 12)
+#define USB_SHUT                        (0x1 << 11)
+#define UART1_3_USE_CAN1                (0x1 << 5)
+#define UART1_2_USE_CAN0                (0x1 << 4)
+#define GMAC1_USE_TXCLK                 (0x1 << 3)
+#define GMAC0_USE_TXCLK                 (0x1 << 2)
+#define GMAC1_USE_PWM23                 (0x1 << 1)
+#define GMAC0_USE_PWM01                 0x1
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_MUX_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-pwm.h b/arch/mips/include/asm/mach-loongson1/regs-pwm.h
new file mode 100644
index 000000000000..99f2bcc586f0
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-pwm.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 PWM Register Definitions.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_PWM_H
+#define __ASM_MACH_LOONGSON1_REGS_PWM_H
+
+/* Loongson 1 PWM Timer Register Definitions */
+#define PWM_CNT                 0x0
+#define PWM_HRC                 0x4
+#define PWM_LRC                 0x8
+#define PWM_CTRL                0xc
+
+/* PWM Control Register Bits */
+#define CNT_RST                 (0x1 << 7)
+#define INT_SR                  (0x1 << 6)
+#define INT_EN                  (0x1 << 5)
+#define PWM_SINGLE              (0x1 << 4)
+#define PWM_OE                  (0x1 << 3)
+#define CNT_EN                  0x1
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_PWM_H */