MIPS: KVM: Reformat code and comments

No logic changes inside.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2 files changed, 10 insertions, 3 deletions

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index b0aa95565752..3f813f295134 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -359,13 +359,17 @@ enum emulation_result {
 #define MIPS3_PG_FRAME          0x3fffffc0
 
 #define VPN2_MASK               0xffffe000
-#define TLB_IS_GLOBAL(x)        (((x).tlb_lo0 & MIPS3_PG_G) &&  \
+#define TLB_IS_GLOBAL(x)        (((x).tlb_lo0 & MIPS3_PG_G) &&          \
                                  ((x).tlb_lo1 & MIPS3_PG_G))
 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 #define TLB_ASID(x)             ((x).tlb_hi & ASID_MASK)
-#define TLB_IS_VALID(x, va)     (((va) & (1 << PAGE_SHIFT))     \
-                                 ? ((x).tlb_lo1 & MIPS3_PG_V)   \
+#define TLB_IS_VALID(x, va)     (((va) & (1 << PAGE_SHIFT))             \
+                                 ? ((x).tlb_lo1 & MIPS3_PG_V)           \
                                  : ((x).tlb_lo0 & MIPS3_PG_V))
+#define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
+                                 ((y) & VPN2_MASK & ~(x).tlb_mask))
+#define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
+                                 TLB_ASID(x) == ((y) & ASID_MASK))
 
 struct kvm_mips_tlb {
         long tlb_mask;
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 0b8bd28a0df1..4520adc8699b 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -19,6 +19,9 @@
 #include <asm/mipsmtregs.h>
 #include <asm/uaccess.h> /* for segment_eq() */
 
+extern void (*r4k_blast_dcache)(void);
+extern void (*r4k_blast_icache)(void);
+
 /*
  * This macro return a properly sign-extended address suitable as base address
  * for indexed cache operations.  Two issues here: