Merge branch 'bfin_rotary' into next

Merge bfin_rotary driver changes from Sonic Zhang.

7 files changed, 57 insertions, 35 deletions

diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 994d21939676..affebb78f5d6 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -64,7 +64,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
                         return SIGFPE;
 
                 /* set FRE */
-                write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);
+                set_c0_config5(MIPS_CONF5_FRE);
                 goto fr_common;
 
         case FPU_64BIT:
@@ -74,8 +74,10 @@ static inline int __enable_fpu(enum fpu_mode mode)
 #endif
                 /* fall through */
         case FPU_32BIT:
-                /* clear FRE */
-                write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
+                if (cpu_has_fre) {
+                        /* clear FRE */
+                        clear_c0_config5(MIPS_CONF5_FRE);
+                }
 fr_common:
                 /* set CU1 & change FR appropriately */
                 fr = (int)mode & FPU_FR_MASK;
@@ -182,25 +184,32 @@ static inline int init_fpu(void)
         int ret = 0;
 
         if (cpu_has_fpu) {
+                unsigned int config5;
+
                 ret = __own_fpu();
-                if (!ret) {
-                        unsigned int config5 = read_c0_config5();
-
-                        /*
-                         * Ensure FRE is clear whilst running _init_fpu, since
-                         * single precision FP instructions are used. If FRE
-                         * was set then we'll just end up initialising all 32
-                         * 64b registers.
-                         */
-                        write_c0_config5(config5 & ~MIPS_CONF5_FRE);
-                        enable_fpu_hazard();
+                if (ret)
+                        return ret;
 
+                if (!cpu_has_fre) {
                         _init_fpu();
 
-                        /* Restore FRE */
-                        write_c0_config5(config5);
-                        enable_fpu_hazard();
+                        return 0;
                 }
+
+                /*
+                 * Ensure FRE is clear whilst running _init_fpu, since
+                 * single precision FP instructions are used. If FRE
+                 * was set then we'll just end up initialising all 32
+                 * 64b registers.
+                 */
+                config5 = clear_c0_config5(MIPS_CONF5_FRE);
+                enable_fpu_hazard();
+
+                _init_fpu();
+
+                /* Restore FRE */
+                write_c0_config5(config5);
+                enable_fpu_hazard();
         } else
                 fpu_emulator_init_fpu();
 
diff --git a/arch/mips/include/asm/fw/arc/hinv.h b/arch/mips/include/asm/fw/arc/hinv.h
index f8d37d1df5de..9fac64a26353 100644
--- a/arch/mips/include/asm/fw/arc/hinv.h
+++ b/arch/mips/include/asm/fw/arc/hinv.h
@@ -119,7 +119,7 @@ union key_u {
 #define SGI_ARCS_REV    10                      /* rev .10, 3/04/92 */
 #endif
 
-typedef struct component {
+typedef struct {
         CONFIGCLASS     Class;
         CONFIGTYPE      Type;
         IDENTIFIERFLAG  Flags;
@@ -140,7 +140,7 @@ struct cfgdata {
 };
 
 /* System ID */
-typedef struct systemid {
+typedef struct {
         CHAR VendorId[8];
         CHAR ProductId[8];
 } SYSTEMID;
@@ -166,7 +166,7 @@ typedef enum memorytype {
 #endif  /* _NT_PROM */
 } MEMORYTYPE;
 
-typedef struct memorydescriptor {
+typedef struct {
         MEMORYTYPE      Type;
         LONG            BasePage;
         LONG            PageCount;
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index b95a827d763e..59c0901bdd84 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -89,9 +89,9 @@ static inline bool mips_cm_has_l2sync(void)
 
 /* Macros to ease the creation of register access functions */
 #define BUILD_CM_R_(name, off)                                  \
-static inline u32 *addr_gcr_##name(void)                        \
+static inline u32 __iomem *addr_gcr_##name(void)                \
 {                                                               \
-        return (u32 *)(mips_cm_base + (off));                   \
+        return (u32 __iomem *)(mips_cm_base + (off));           \
 }                                                               \
                                                                 \
 static inline u32 read_gcr_##name(void)                         \
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 5e4aef304b02..5b720d8c2745 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1386,12 +1386,27 @@ do {									\
         __res;                                                          \
 })
 
+#define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    reorder                                 \n"     \
+        "       "STR(gas_hardfloat)"                            \n"     \
+        "       ctc1    %0,"STR(dest)"                          \n"     \
+        "       .set    pop                                     \n"     \
+        : : "r" (val));                                                 \
+} while (0)
+
 #ifdef GAS_HAS_SET_HARDFLOAT
 #define read_32bit_cp1_register(source)                                 \
         _read_32bit_cp1_register(source, .set hardfloat)
+#define write_32bit_cp1_register(dest, val)                             \
+        _write_32bit_cp1_register(dest, val, .set hardfloat)
 #else
 #define read_32bit_cp1_register(source)                                 \
         _read_32bit_cp1_register(source, )
+#define write_32bit_cp1_register(dest, val)                             \
+        _write_32bit_cp1_register(dest, val, )
 #endif
 
 #ifdef HAVE_AS_DSP
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index bb7963753730..6499d93ae68d 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -29,13 +29,7 @@
 static inline long syscall_get_nr(struct task_struct *task,
                                   struct pt_regs *regs)
 {
-        /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
-        if ((config_enabled(CONFIG_32BIT) ||
-            test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
-            (regs->regs[2] == __NR_syscall))
-                return regs->regs[4];
-        else
-                return regs->regs[2];
+        return current_thread_info()->syscall;
 }
 
 static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 99eea59604e9..e4440f92b366 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -36,6 +36,7 @@ struct thread_info {
                                                  */
         struct restart_block    restart_block;
         struct pt_regs          *regs;
+        long                    syscall;        /* syscall number */
 };
 
 /*
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index d001bb1ad177..c03088f9f514 100644
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -376,16 +376,17 @@
 #define __NR_getrandom                  (__NR_Linux + 353)
 #define __NR_memfd_create               (__NR_Linux + 354)
 #define __NR_bpf                        (__NR_Linux + 355)
+#define __NR_execveat                   (__NR_Linux + 356)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             355
+#define __NR_Linux_syscalls             356
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         355
+#define __NR_O32_Linux_syscalls         356
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -709,16 +710,17 @@
 #define __NR_getrandom                  (__NR_Linux + 313)
 #define __NR_memfd_create               (__NR_Linux + 314)
 #define __NR_bpf                        (__NR_Linux + 315)
+#define __NR_execveat                   (__NR_Linux + 316)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             315
+#define __NR_Linux_syscalls             316
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          315
+#define __NR_64_Linux_syscalls          316
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -1046,15 +1048,16 @@
 #define __NR_getrandom                  (__NR_Linux + 317)
 #define __NR_memfd_create               (__NR_Linux + 318)
 #define __NR_bpf                        (__NR_Linux + 319)
+#define __NR_execveat                   (__NR_Linux + 320)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             319
+#define __NR_Linux_syscalls             320
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         319
+#define __NR_N32_Linux_syscalls         320
 
 #endif /* _UAPI_ASM_UNISTD_H */