Merge branch 'next/alchemy' into mips-for-linux-next

18 files changed, 634 insertions, 472 deletions

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2f7f41873f24..79e4a0dad0d9 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -169,6 +169,7 @@
 #define PRID_IMP_NETLOGIC_XLS412B       0x4c00
 #define PRID_IMP_NETLOGIC_XLS408B       0x4e00
 #define PRID_IMP_NETLOGIC_XLS404B       0x4f00
+#define PRID_IMP_NETLOGIC_AU13XX        0x8000
 
 /*
  * Definitions for 7:0 on legacy processors
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index de24ec57dd2f..569828d3ccab 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
 #define ALCHEMY_CPU_AU1100      2
 #define ALCHEMY_CPU_AU1550      3
 #define ALCHEMY_CPU_AU1200      4
+#define ALCHEMY_CPU_AU1300      5
 
 static inline int alchemy_get_cputype(void)
 {
@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
         case 0x05030000:
                 return ALCHEMY_CPU_AU1200;
                 break;
+        case 0x800c0000:
+                return ALCHEMY_CPU_AU1300;
+                break;
         }
 
         return ALCHEMY_CPU_UNKNOWN;
@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
 {
         switch (type) {
         case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1300:
                 return 4;
         case ALCHEMY_CPU_AU1500:
         case ALCHEMY_CPU_AU1200:
@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
 void alchemy_sleep_au1000(void);
 void alchemy_sleep_au1550(void);
+void alchemy_sleep_au1300(void);
 void au_sleep(void);
 
 /* USB: drivers/usb/host/alchemy-common.c */
@@ -251,6 +257,7 @@ enum alchemy_usb_block {
         ALCHEMY_USB_UDC0,
         ALCHEMY_USB_EHCI0,
         ALCHEMY_USB_OTG0,
+        ALCHEMY_USB_OHCI1,
 };
 int alchemy_usb_control(int block, int enable);
 
@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
         unsigned long pci_cfg_clr;
 };
 
-/* SOC Interrupt numbers */
+/* Multifunction pins: Each of these pins can either be assigned to the
+ * GPIO controller or a on-chip peripheral.
+ * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
+ * assign one of these to either the GPIO controller or the device.
+ */
+enum au1300_multifunc_pins {
+        /* wake-from-str pins 0-3 */
+        AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
+        AU1300_PIN_WAKE3,
+        /* external clock sources for PSCs: 4-5 */
+        AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
+        /* 8bit MMC interface on SD0: 6-9 */
+        AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
+        AU1300_PIN_SD0DAT7,
+        /* aux clk input for freqgen 3: 10 */
+        AU1300_PIN_FG3AUX,
+        /* UART1 pins: 11-18 */
+        AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
+        AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
+        AU1300_PIN_U1RX, AU1300_PIN_U1TX,
+        /* UART0 pins: 19-24 */
+        AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
+        AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
+        /* UART2: 25-26 */
+        AU1300_PIN_U2RX, AU1300_PIN_U2TX,
+        /* UART3: 27-28 */
+        AU1300_PIN_U3RX, AU1300_PIN_U3TX,
+        /* LCD controller PWMs, ext pixclock: 29-31 */
+        AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
+        /* SD1 interface: 32-37 */
+        AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
+        AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
+        /* SD2 interface: 38-43 */
+        AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
+        AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
+        /* PSC0/1 clocks: 44-45 */
+        AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
+        /* PSCs: 46-49/50-53/54-57/58-61 */
+        AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
+        AU1300_PIN_PSC0D1,
+        AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
+        AU1300_PIN_PSC1D1,
+        AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
+        AU1300_PIN_PSC2D1,
+        AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
+        AU1300_PIN_PSC3D1,
+        /* PCMCIA interface: 62-70 */
+        AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
+        AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
+        AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
+        /* camera interface H/V sync inputs: 71-72 */
+        AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
+        /* PSC2/3 clocks: 73-74 */
+        AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
+};
+
+/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
+extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
+extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
+extern void au1300_set_irq_priority(unsigned int irq, int p);
+extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
+
+/* Au1300 allows to disconnect certain blocks from internal power supply */
+enum au1300_vss_block {
+        AU1300_VSS_MPE = 0,
+        AU1300_VSS_BSA,
+        AU1300_VSS_GPE,
+        AU1300_VSS_MGP,
+};
 
+extern void au1300_vss_block_control(int block, int enable);
+
+
+/* SOC Interrupt numbers */
+/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
 #define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
 #define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
 #define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_LAST + 1)
 #define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
 #define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
 
+/* Au1300-style (GPIC): 1 controller with up to 128 sources */
+#define ALCHEMY_GPIC_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#define ALCHEMY_GPIC_INT_NUM    128
+#define ALCHEMY_GPIC_INT_LAST   (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
+
 enum soc_au1000_ints {
         AU1000_FIRST_INT        = AU1000_INTC0_INT_BASE,
         AU1000_UART0_INT        = AU1000_FIRST_INT,
@@ -591,24 +676,77 @@ enum soc_au1200_ints {
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
+/* Au1300 peripheral interrupt numbers */
+#define AU1300_FIRST_INT        (ALCHEMY_GPIC_INT_BASE)
+#define AU1300_UART1_INT        (AU1300_FIRST_INT + 17)
+#define AU1300_UART2_INT        (AU1300_FIRST_INT + 25)
+#define AU1300_UART3_INT        (AU1300_FIRST_INT + 27)
+#define AU1300_SD1_INT          (AU1300_FIRST_INT + 32)
+#define AU1300_SD2_INT          (AU1300_FIRST_INT + 38)
+#define AU1300_PSC0_INT         (AU1300_FIRST_INT + 48)
+#define AU1300_PSC1_INT         (AU1300_FIRST_INT + 52)
+#define AU1300_PSC2_INT         (AU1300_FIRST_INT + 56)
+#define AU1300_PSC3_INT         (AU1300_FIRST_INT + 60)
+#define AU1300_NAND_INT         (AU1300_FIRST_INT + 62)
+#define AU1300_DDMA_INT         (AU1300_FIRST_INT + 75)
+#define AU1300_MMU_INT          (AU1300_FIRST_INT + 76)
+#define AU1300_MPU_INT          (AU1300_FIRST_INT + 77)
+#define AU1300_GPU_INT          (AU1300_FIRST_INT + 78)
+#define AU1300_UDMA_INT         (AU1300_FIRST_INT + 79)
+#define AU1300_TOY_INT          (AU1300_FIRST_INT + 80)
+#define AU1300_TOY_MATCH0_INT   (AU1300_FIRST_INT + 81)
+#define AU1300_TOY_MATCH1_INT   (AU1300_FIRST_INT + 82)
+#define AU1300_TOY_MATCH2_INT   (AU1300_FIRST_INT + 83)
+#define AU1300_RTC_INT          (AU1300_FIRST_INT + 84)
+#define AU1300_RTC_MATCH0_INT   (AU1300_FIRST_INT + 85)
+#define AU1300_RTC_MATCH1_INT   (AU1300_FIRST_INT + 86)
+#define AU1300_RTC_MATCH2_INT   (AU1300_FIRST_INT + 87)
+#define AU1300_UART0_INT        (AU1300_FIRST_INT + 88)
+#define AU1300_SD0_INT          (AU1300_FIRST_INT + 89)
+#define AU1300_USB_INT          (AU1300_FIRST_INT + 90)
+#define AU1300_LCD_INT          (AU1300_FIRST_INT + 91)
+#define AU1300_BSA_INT          (AU1300_FIRST_INT + 92)
+#define AU1300_MPE_INT          (AU1300_FIRST_INT + 93)
+#define AU1300_ITE_INT          (AU1300_FIRST_INT + 94)
+#define AU1300_AES_INT          (AU1300_FIRST_INT + 95)
+#define AU1300_CIM_INT          (AU1300_FIRST_INT + 96)
+
+/**********************************************************************/
+
 /*
  * Physical base addresses for integrated peripherals
- * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
  */
 
 #define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
+#define AU1300_ROM_PHYS_ADDR            0x10000000 /* 5 */
+#define AU1300_OTP_PHYS_ADDR            0x10002000 /* 5 */
+#define AU1300_VSS_PHYS_ADDR            0x10003000 /* 5 */
+#define AU1300_UART0_PHYS_ADDR          0x10100000 /* 5 */
+#define AU1300_UART1_PHYS_ADDR          0x10101000 /* 5 */
+#define AU1300_UART2_PHYS_ADDR          0x10102000 /* 5 */
+#define AU1300_UART3_PHYS_ADDR          0x10103000 /* 5 */
 #define AU1000_USB_OHCI_PHYS_ADDR       0x10100000 /* 012 */
 #define AU1000_USB_UDC_PHYS_ADDR        0x10200000 /* 0123 */
+#define AU1300_GPIC_PHYS_ADDR           0x10200000 /* 5 */
 #define AU1000_IRDA_PHYS_ADDR           0x10300000 /* 02 */
-#define AU1200_AES_PHYS_ADDR            0x10300000 /* 4 */
+#define AU1200_AES_PHYS_ADDR            0x10300000 /* 45 */
 #define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
+#define AU1300_GPU_PHYS_ADDR            0x10500000 /* 5 */
 #define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
 #define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
 #define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
-#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 24 */
+#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 245 */
+#define AU1300_SD1_PHYS_ADDR            0x10601000 /* 5 */
+#define AU1300_SD2_PHYS_ADDR            0x10602000 /* 5 */
 #define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
+#define AU1300_SYS_PHYS_ADDR            0x10900000 /* 5 */
 #define AU1550_PSC2_PHYS_ADDR           0x10A00000 /* 3 */
 #define AU1550_PSC3_PHYS_ADDR           0x10B00000 /* 3 */
+#define AU1300_PSC0_PHYS_ADDR           0x10A00000 /* 5 */
+#define AU1300_PSC1_PHYS_ADDR           0x10A01000 /* 5 */
+#define AU1300_PSC2_PHYS_ADDR           0x10A02000 /* 5 */
+#define AU1300_PSC3_PHYS_ADDR           0x10A03000 /* 5 */
 #define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
 #define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
 #define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
@@ -622,37 +760,96 @@ enum soc_au1200_ints {
 #define AU1000_SSI1_PHYS_ADDR           0x11680000 /* 02 */
 #define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
 #define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
-#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 01234 */
+#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 012345 */
 #define AU1550_PSC0_PHYS_ADDR           0x11A00000 /* 34 */
 #define AU1550_PSC1_PHYS_ADDR           0x11B00000 /* 34 */
 #define AU1000_MEM_PHYS_ADDR            0x14000000 /* 01234 */
 #define AU1000_STATIC_MEM_PHYS_ADDR     0x14001000 /* 01234 */
+#define AU1300_UDMA_PHYS_ADDR           0x14001800 /* 5 */
 #define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
-#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 34 */
-#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 34 */
+#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 345 */
+#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 345 */
 #define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
 #define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
-#define AU1200_CIM_PHYS_ADDR            0x14004000 /* 4 */
+#define AU1200_CIM_PHYS_ADDR            0x14004000 /* 45 */
 #define AU1500_PCI_PHYS_ADDR            0x14005000 /* 13 */
 #define AU1550_PE_PHYS_ADDR             0x14008000 /* 3 */
 #define AU1200_MAEBE_PHYS_ADDR          0x14010000 /* 4 */
 #define AU1200_MAEFE_PHYS_ADDR          0x14012000 /* 4 */
+#define AU1300_MAEITE_PHYS_ADDR         0x14010000 /* 5 */
+#define AU1300_MAEMPE_PHYS_ADDR         0x14014000 /* 5 */
 #define AU1550_USB_OHCI_PHYS_ADDR       0x14020000 /* 3 */
 #define AU1200_USB_CTL_PHYS_ADDR        0x14020000 /* 4 */
 #define AU1200_USB_OTG_PHYS_ADDR        0x14020020 /* 4 */
 #define AU1200_USB_OHCI_PHYS_ADDR       0x14020100 /* 4 */
 #define AU1200_USB_EHCI_PHYS_ADDR       0x14020200 /* 4 */
 #define AU1200_USB_UDC_PHYS_ADDR        0x14022000 /* 4 */
+#define AU1300_USB_EHCI_PHYS_ADDR       0x14020000 /* 5 */
+#define AU1300_USB_OHCI0_PHYS_ADDR      0x14020400 /* 5 */
+#define AU1300_USB_OHCI1_PHYS_ADDR      0x14020800 /* 5 */
+#define AU1300_USB_CTL_PHYS_ADDR        0x14021000 /* 5 */
+#define AU1300_USB_OTG_PHYS_ADDR        0x14022000 /* 5 */
+#define AU1300_MAEBSA_PHYS_ADDR         0x14030000 /* 5 */
 #define AU1100_LCD_PHYS_ADDR            0x15000000 /* 2 */
-#define AU1200_LCD_PHYS_ADDR            0x15000000 /* 4 */
+#define AU1200_LCD_PHYS_ADDR            0x15000000 /* 45 */
 #define AU1500_PCI_MEM_PHYS_ADDR        0x400000000ULL /* 13 */
 #define AU1500_PCI_IO_PHYS_ADDR         0x500000000ULL /* 13 */
 #define AU1500_PCI_CONFIG0_PHYS_ADDR    0x600000000ULL /* 13 */
 #define AU1500_PCI_CONFIG1_PHYS_ADDR    0x680000000ULL /* 13 */
-#define AU1000_PCMCIA_IO_PHYS_ADDR      0xF00000000ULL /* 01234 */
-#define AU1000_PCMCIA_ATTR_PHYS_ADDR    0xF40000000ULL /* 01234 */
-#define AU1000_PCMCIA_MEM_PHYS_ADDR     0xF80000000ULL /* 01234 */
+#define AU1000_PCMCIA_IO_PHYS_ADDR      0xF00000000ULL /* 012345 */
+#define AU1000_PCMCIA_ATTR_PHYS_ADDR    0xF40000000ULL /* 012345 */
+#define AU1000_PCMCIA_MEM_PHYS_ADDR     0xF80000000ULL /* 012345 */
 
+/**********************************************************************/
+
+
+/*
+ * Au1300 GPIO+INT controller (GPIC) register offsets and bits
+ * Registers are 128bits (0x10 bytes), divided into 4 "banks".
+ */
+#define AU1300_GPIC_PINVAL      0x0000
+#define AU1300_GPIC_PINVALCLR   0x0010
+#define AU1300_GPIC_IPEND       0x0020
+#define AU1300_GPIC_PRIENC      0x0030
+#define AU1300_GPIC_IEN         0x0040  /* int_mask in manual */
+#define AU1300_GPIC_IDIS        0x0050  /* int_maskclr in manual */
+#define AU1300_GPIC_DMASEL      0x0060
+#define AU1300_GPIC_DEVSEL      0x0080
+#define AU1300_GPIC_DEVCLR      0x0090
+#define AU1300_GPIC_RSTVAL      0x00a0
+/* pin configuration space. one 32bit register for up to 128 IRQs */
+#define AU1300_GPIC_PINCFG      0x1000
+
+#define GPIC_GPIO_TO_BIT(gpio)  \
+        (1 << ((gpio) & 0x1f))
+
+#define GPIC_GPIO_BANKOFF(gpio) \
+        (((gpio) >> 5) * 4)
+
+/* Pin Control bits: who owns the pin, what does it do */
+#define GPIC_CFG_PC_GPIN                0
+#define GPIC_CFG_PC_DEV                 1
+#define GPIC_CFG_PC_GPOLOW              2
+#define GPIC_CFG_PC_GPOHIGH             3
+#define GPIC_CFG_PC_MASK                3
+
+/* assign pin to MIPS IRQ line */
+#define GPIC_CFG_IL_SET(x)      (((x) & 3) << 2)
+#define GPIC_CFG_IL_MASK        (3 << 2)
+
+/* pin interrupt type setup */
+#define GPIC_CFG_IC_OFF         (0 << 4)
+#define GPIC_CFG_IC_LEVEL_LOW   (1 << 4)
+#define GPIC_CFG_IC_LEVEL_HIGH  (2 << 4)
+#define GPIC_CFG_IC_EDGE_FALL   (5 << 4)
+#define GPIC_CFG_IC_EDGE_RISE   (6 << 4)
+#define GPIC_CFG_IC_EDGE_BOTH   (7 << 4)
+#define GPIC_CFG_IC_MASK        (7 << 4)
+
+/* allow interrupt to wake cpu from 'wait' */
+#define GPIC_CFG_IDLEWAKE       (1 << 7)
+
+/***********************************************************************/
 
 /* Au1000 SDRAM memory controller register offsets */
 #define AU1000_MEM_SDMODE0              0x0000
@@ -1068,44 +1265,20 @@ enum soc_au1200_ints {
 #define SSI_ENABLE_CD           (1 << 1)
 #define SSI_ENABLE_E            (1 << 0)
 
-/* IrDA Controller */
-#define IRDA_BASE               0xB0300000
-#define IR_RING_PTR_STATUS      (IRDA_BASE + 0x00)
-#define IR_RING_BASE_ADDR_H     (IRDA_BASE + 0x04)
-#define IR_RING_BASE_ADDR_L     (IRDA_BASE + 0x08)
-#define IR_RING_SIZE            (IRDA_BASE + 0x0C)
-#define IR_RING_PROMPT          (IRDA_BASE + 0x10)
-#define IR_RING_ADDR_CMPR       (IRDA_BASE + 0x14)
-#define IR_INT_CLEAR            (IRDA_BASE + 0x18)
-#define IR_CONFIG_1             (IRDA_BASE + 0x20)
-#  define IR_RX_INVERT_LED      (1 << 0)
-#  define IR_TX_INVERT_LED      (1 << 1)
-#  define IR_ST                 (1 << 2)
-#  define IR_SF                 (1 << 3)
-#  define IR_SIR                (1 << 4)
-#  define IR_MIR                (1 << 5)
-#  define IR_FIR                (1 << 6)
-#  define IR_16CRC              (1 << 7)
-#  define IR_TD                 (1 << 8)
-#  define IR_RX_ALL             (1 << 9)
-#  define IR_DMA_ENABLE         (1 << 10)
-#  define IR_RX_ENABLE          (1 << 11)
-#  define IR_TX_ENABLE          (1 << 12)
-#  define IR_LOOPBACK           (1 << 14)
-#  define IR_SIR_MODE           (IR_SIR | IR_DMA_ENABLE | \
-                                 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS            (IRDA_BASE + 0x24)
-#define IR_ENABLE               (IRDA_BASE + 0x28)
-#  define IR_RX_STATUS          (1 << 9)
-#  define IR_TX_STATUS          (1 << 10)
-#define IR_READ_PHY_CONFIG      (IRDA_BASE + 0x2C)
-#define IR_WRITE_PHY_CONFIG     (IRDA_BASE + 0x30)
-#define IR_MAX_PKT_LEN          (IRDA_BASE + 0x34)
-#define IR_RX_BYTE_CNT          (IRDA_BASE + 0x38)
-#define IR_CONFIG_2             (IRDA_BASE + 0x3C)
-#  define IR_MODE_INV           (1 << 0)
-#  define IR_ONE_PIN            (1 << 1)
-#define IR_INTERFACE_CONFIG     (IRDA_BASE + 0x40)
+
+/*
+ * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
+ * used to select FIR/SIR mode on the transceiver but as a GPIO.  Instead a
+ * CPLD has to be told about the mode.
+ */
+#define AU1000_IRDA_PHY_MODE_OFF        0
+#define AU1000_IRDA_PHY_MODE_SIR        1
+#define AU1000_IRDA_PHY_MODE_FIR        2
+
+struct au1k_irda_platform_data {
+        void(*set_phy_mode)(int mode);
+};
+
 
 /* GPIO */
 #define SYS_PINFUNC             0xB190002C
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index 94000a3b6f0b..e221659f1bca 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
 #define SD_CONFIG2_DF   (0x00000008)
 #define SD_CONFIG2_DC   (0x00000010)
 #define SD_CONFIG2_xx2  (0x000000e0)
+#define SD_CONFIG2_BB   (0x00000080)
 #define SD_CONFIG2_WB   (0x00000100)
 #define SD_CONFIG2_RW   (0x00000200)
+#define SD_CONFIG2_DP   (0x00000400)
 
 
 /*
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
new file mode 100644
index 000000000000..b3c87cc64bb9
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h
@@ -0,0 +1,14 @@
+/*
+ * platform data for au1200fb driver.
+ */
+
+#ifndef _AU1200FB_PLAT_H_
+#define _AU1200FB_PLAT_H_
+
+struct au1200fb_platdata {
+        int (*panel_index)(void);
+        int (*panel_init)(void);
+        int (*panel_shutdown)(void);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
new file mode 100644
index 000000000000..ad4c0a03afef
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h
@@ -0,0 +1,16 @@
+/*
+ * platform data for the Au1550 NAND driver
+ */
+
+#ifndef _AU1550ND_H_
+#define _AU1550ND_H_
+
+#include <linux/mtd/partitions.h>
+
+struct au1550nd_platdata {
+        struct mtd_partition *parts;
+        int num_parts;
+        int devwidth;   /* 0 = 8bit device, 1 = 16bit device */
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 323ce2d145f2..217810e18361 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
 #define AU1200_DSCR_CMD0_PSC1_SYNC      25
 #define AU1200_DSCR_CMD0_CIM_SYNC       26
 
+#define AU1300_DSCR_CMD0_UART0_TX      0
+#define AU1300_DSCR_CMD0_UART0_RX      1
+#define AU1300_DSCR_CMD0_UART1_TX      2
+#define AU1300_DSCR_CMD0_UART1_RX      3
+#define AU1300_DSCR_CMD0_UART2_TX      4
+#define AU1300_DSCR_CMD0_UART2_RX      5
+#define AU1300_DSCR_CMD0_UART3_TX      6
+#define AU1300_DSCR_CMD0_UART3_RX      7
+#define AU1300_DSCR_CMD0_SDMS_TX0      8
+#define AU1300_DSCR_CMD0_SDMS_RX0      9
+#define AU1300_DSCR_CMD0_SDMS_TX1      10
+#define AU1300_DSCR_CMD0_SDMS_RX1      11
+#define AU1300_DSCR_CMD0_AES_TX        12
+#define AU1300_DSCR_CMD0_AES_RX        13
+#define AU1300_DSCR_CMD0_PSC0_TX       14
+#define AU1300_DSCR_CMD0_PSC0_RX       15
+#define AU1300_DSCR_CMD0_PSC1_TX       16
+#define AU1300_DSCR_CMD0_PSC1_RX       17
+#define AU1300_DSCR_CMD0_PSC2_TX       18
+#define AU1300_DSCR_CMD0_PSC2_RX       19
+#define AU1300_DSCR_CMD0_PSC3_TX       20
+#define AU1300_DSCR_CMD0_PSC3_RX       21
+#define AU1300_DSCR_CMD0_LCD           22
+#define AU1300_DSCR_CMD0_NAND_FLASH    23
+#define AU1300_DSCR_CMD0_SDMS_TX2      24
+#define AU1300_DSCR_CMD0_SDMS_RX2      25
+#define AU1300_DSCR_CMD0_CIM_SYNC      26
+#define AU1300_DSCR_CMD0_UDMA          27
+#define AU1300_DSCR_CMD0_DMA_REQ0      28
+#define AU1300_DSCR_CMD0_DMA_REQ1      29
+
 #define DSCR_CMD0_THROTTLE      30
 #define DSCR_CMD0_ALWAYS        31
 #define DSCR_NDEV_IDS           32
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index d5df0cab9b87..3f741af37d47 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,12 +13,14 @@
 #define cpu_has_4k_cache                1
 #define cpu_has_tx39_cache              0
 #define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
 #define cpu_has_counter                 1
 #define cpu_has_watch                   1
 #define cpu_has_divec                   1
 #define cpu_has_vce                     0
 #define cpu_has_cache_cdex_p            0
 #define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
 #define cpu_has_mcheck                  1
 #define cpu_has_ejtag                   1
 #define cpu_has_llsc                    1
@@ -29,6 +31,7 @@
 #define cpu_has_vtag_icache             0
 #define cpu_has_dc_aliases              0
 #define cpu_has_ic_fills_f_dc           1
+#define cpu_has_pindexed_dcache         0
 #define cpu_has_mips32r1                1
 #define cpu_has_mips32r2                0
 #define cpu_has_mips64r1                0
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 000000000000..556e1be20bf6
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,241 @@
+/*
+ * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
+ *
+ * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
+ */
+
+#ifndef _GPIO_AU1300_H_
+#define _GPIO_AU1300_H_
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+
+/* with the current GPIC design, up to 128 GPIOs are possible.
+ * The only implementation so far is in the Au1300, which has 75 externally
+ * available GPIOs.
+ */
+#define AU1300_GPIO_BASE        0
+#define AU1300_GPIO_NUM         75
+#define AU1300_GPIO_MAX         (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
+
+#define AU1300_GPIC_ADDR        \
+        (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
+
+static inline int au1300_gpio_get_value(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        int bit;
+
+        gpio -= AU1300_GPIO_BASE;
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
+}
+
+static inline int au1300_gpio_direction_input(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        gpio -= AU1300_GPIO_BASE;
+
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
+        wmb();
+
+        return 0;
+}
+
+static inline int au1300_gpio_set_value(unsigned int gpio, int v)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        gpio -= AU1300_GPIO_BASE;
+
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
+                                    : AU1300_GPIC_PINVALCLR));
+        wmb();
+
+        return 0;
+}
+
+static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
+{
+        /* hw switches to output automatically */
+        return au1300_gpio_set_value(gpio, v);
+}
+
+static inline int au1300_gpio_to_irq(unsigned int gpio)
+{
+        return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
+}
+
+static inline int au1300_irq_to_gpio(unsigned int irq)
+{
+        return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
+}
+
+static inline int au1300_gpio_is_valid(unsigned int gpio)
+{
+        int ret;
+
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1300:
+                ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
+                break;
+        default:
+                ret = 0;
+        }
+        return ret;
+}
+
+static inline int au1300_gpio_cansleep(unsigned int gpio)
+{
+        return 0;
+}
+
+/* hardware remembers gpio 0-63 levels on powerup */
+static inline int au1300_gpio_getinitlvl(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long v;
+
+        if (unlikely(gpio > 63))
+                return 0;
+        else if (gpio > 31) {
+                gpio -= 32;
+                roff += 4;
+        }
+
+        v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
+        return (v >> gpio) & 1;
+}
+
+/**********************************************************************/
+
+/* Linux gpio framework integration.
+*
+* 4 use cases of Alchemy GPIOS:
+*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
+*       Board must register gpiochips.
+*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
+*       A gpiochip for the 75 GPIOs is registered.
+*
+*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
+*       the boards' gpio.h must provide the linux gpio wrapper functions,
+*
+*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
+*       inlinable gpio functions are provided which enable access to the
+*       Au1300 gpios only by using the numbers straight out of the data-
+*       sheets.
+
+* Cases 1 and 3 are intended for boards which want to provide their own
+* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
+* which are in part provided by spare Au1300 GPIO pins and in part by
+* an external FPGA but you still want them to be accssible in linux
+* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
+* as required).
+*/
+
+#ifndef CONFIG_GPIOLIB
+
+#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
+
+#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (4) */
+
+static inline int gpio_direction_input(unsigned int gpio)
+{
+        return au1300_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned int gpio, int v)
+{
+        return au1300_gpio_direction_output(gpio, v);
+}
+
+static inline int gpio_get_value(unsigned int gpio)
+{
+        return au1300_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int v)
+{
+        au1300_gpio_set_value(gpio, v);
+}
+
+static inline int gpio_get_value_cansleep(unsigned gpio)
+{
+        return gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value_cansleep(unsigned gpio, int value)
+{
+        gpio_set_value(gpio, value);
+}
+
+static inline int gpio_is_valid(unsigned int gpio)
+{
+        return au1300_gpio_is_valid(gpio);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+        return au1300_gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+        return au1300_gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        return au1300_irq_to_gpio(irq);
+}
+
+static inline int gpio_request(unsigned int gpio, const char *label)
+{
+        return 0;
+}
+
+static inline void gpio_free(unsigned int gpio)
+{
+}
+
+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
+{
+        return -ENOSYS;
+}
+
+static inline void gpio_unexport(unsigned gpio)
+{
+}
+
+static inline int gpio_export(unsigned gpio, bool direction_may_change)
+{
+        return -ENOSYS;
+}
+
+static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
+{
+        return -ENOSYS;
+}
+
+static inline int gpio_export_link(struct device *dev, const char *name,
+                                   unsigned gpio)
+{
+        return -ENOSYS;
+}
+
+#endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
+
+#endif  /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
+
+#endif  /* CONFIG GPIOLIB */
+
+#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index fcdc8c4809db..22e7ff17fc48 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -12,6 +12,7 @@
 
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/gpio-au1000.h>
+#include <asm/mach-au1x00/gpio-au1300.h>
 
 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
  * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200/Au1300 this
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
         switch (alchemy_get_cputype()) {
         case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
                 return alchemy_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1300:
+                return au1300_irq_to_gpio(irq);
         }
         return -EINVAL;
 }
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 618d2de02ed3..bb9fc23d853a 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,6 +34,8 @@
 #define PB1200_BCSR_PHYS_ADDR   0x0D800000
 #define PB1200_BCSR_HEXLED_OFS  0x00400000
 
+#define DB1300_BCSR_PHYS_ADDR   0x19800000
+#define DB1300_BCSR_HEXLED_OFS  0x00400000
 
 enum bcsr_id {
         /* BCSR base 1 */
@@ -105,6 +107,7 @@ enum bcsr_whoami_boards {
         BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
         BCSR_WHOAMI_PB1200_DDR2,
         BCSR_WHOAMI_DB1200,
+        BCSR_WHOAMI_DB1300,
 };
 
 /* STATUS reg.  Unless otherwise noted, they're valid on all boards.
@@ -118,12 +121,12 @@ enum bcsr_whoami_boards {
 #define BCSR_STATUS_SRAMWIDTH           0x0080
 #define BCSR_STATUS_FLASHBUSY           0x0100
 #define BCSR_STATUS_ROMBUSY             0x0400
-#define BCSR_STATUS_SD0WP               0x0400  /* DB1200 */
+#define BCSR_STATUS_SD0WP               0x0400  /* DB1200/DB1300:SD1 */
 #define BCSR_STATUS_SD1WP               0x0800
 #define BCSR_STATUS_USBOTGID            0x0800  /* PB/DB1550 */
 #define BCSR_STATUS_DB1000_SWAPBOOT     0x2000
-#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200 */
-#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200 */
+#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200/1300 */
+#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200/1300 */
 #define BCSR_STATUS_DB1200_U0RXD        0x1000  /* DB1200 */
 #define BCSR_STATUS_DB1200_U1RXD        0x2000  /* DB1200 */
 #define BCSR_STATUS_FLASHDEN            0xC000
@@ -133,6 +136,11 @@ enum bcsr_whoami_boards {
 #define BCSR_STATUS_PB1550_U1RXD        0x2000  /* PB1550 */
 #define BCSR_STATUS_PB1550_U3RXD        0x8000  /* PB1550 */
 
+#define BCSR_STATUS_CFWP                0x4000  /* DB1300 */
+#define BCSR_STATUS_USBOCn              0x2000  /* DB1300 */
+#define BCSR_STATUS_OTGOCn              0x1000  /* DB1300 */
+#define BCSR_STATUS_DCDMARQ             0x0010  /* DB1300 */
+#define BCSR_STATUS_IDEDMARQ            0x0020  /* DB1300 */
 
 /* DB/PB1000,1100,1500,1550 */
 #define BCSR_RESETS_PHY0                0x0001
@@ -155,17 +163,17 @@ enum bcsr_whoami_boards {
 #define BCSR_BOARD_GPIO200RST           0x0400
 #define BCSR_BOARD_PCICLKOUT            0x0800
 #define BCSR_BOARD_PCICFG               0x1000
-#define BCSR_BOARD_SPISEL               0x4000  /* PB/DB1550 */
+#define BCSR_BOARD_SPISEL               0x2000  /* PB/DB1550 */
 #define BCSR_BOARD_SD0WP                0x4000  /* DB1100 */
 #define BCSR_BOARD_SD1WP                0x8000  /* DB1100 */
 
 
-/* DB/PB1200 */
+/* DB/PB1200/1300 */
 #define BCSR_RESETS_ETH                 0x0001
 #define BCSR_RESETS_CAMERA              0x0002
 #define BCSR_RESETS_DC                  0x0004
 #define BCSR_RESETS_IDE                 0x0008
-#define BCSR_RESETS_TV                  0x0010  /* DB1200 */
+#define BCSR_RESETS_TV                  0x0010  /* DB1200/1300 */
 /* Not resets but in the same register */
 #define BCSR_RESETS_PWMR1MUX            0x0800  /* DB1200 */
 #define BCSR_RESETS_PB1200_WSCFSM       0x0800  /* PB1200 */
@@ -174,13 +182,22 @@ enum bcsr_whoami_boards {
 #define BCSR_RESETS_SPISEL              0x4000
 #define BCSR_RESETS_SD1MUX              0x8000  /* PB1200 */
 
+#define BCSR_RESETS_VDDQSHDN            0x0200  /* DB1300 */
+#define BCSR_RESETS_OTPPGM              0x0400  /* DB1300 */
+#define BCSR_RESETS_OTPSCLK             0x0800  /* DB1300 */
+#define BCSR_RESETS_OTPWRPROT           0x1000  /* DB1300 */
+#define BCSR_RESETS_OTPCSB              0x2000  /* DB1300 */
+#define BCSR_RESETS_OTGPWR              0x4000  /* DB1300 */
+#define BCSR_RESETS_USBHPWR             0x8000  /* DB1300 */
+
 #define BCSR_BOARD_LCDVEE               0x0001
 #define BCSR_BOARD_LCDVDD               0x0002
 #define BCSR_BOARD_LCDBL                0x0004
 #define BCSR_BOARD_CAMSNAP              0x0010
 #define BCSR_BOARD_CAMPWR               0x0020
 #define BCSR_BOARD_SD0PWR               0x0040
-
+#define BCSR_BOARD_CAMCS                0x0010  /* DB1300 */
+#define BCSR_BOARD_HDMI_DE              0x0040  /* DB1300 */
 
 #define BCSR_SWITCHES_DIP               0x00FF
 #define BCSR_SWITCHES_DIP_1             0x0080
@@ -214,7 +231,10 @@ enum bcsr_whoami_boards {
 #define BCSR_SYSTEM_RESET               0x8000  /* clear to reset */
 #define BCSR_SYSTEM_PWROFF              0x4000  /* set to power off */
 #define BCSR_SYSTEM_VDDI                0x001F  /* PB1xxx boards */
-
+#define BCSR_SYSTEM_DEBUGCSMASK         0x003F  /* DB1300 */
+#define BCSR_SYSTEM_UDMAMODE            0x0100  /* DB1300 */
+#define BCSR_SYSTEM_WAKEONIRQ           0x0200  /* DB1300 */
+#define BCSR_SYSTEM_VDDI1300            0x3C00  /* DB1300 */
 
 
 
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c4..b2a8319521e5 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
 #define BCSR_INT_PC1EJECT       0x0800
 #define BCSR_INT_SD0INSERT      0x1000
 #define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
 
-#define IDE_PHYS_ADDR           0x18800000
 #define IDE_REG_SHIFT           5
 
-#define DB1200_IDE_PHYS_ADDR    IDE_PHYS_ADDR
+#define DB1200_IDE_PHYS_ADDR    0x18800000
 #define DB1200_IDE_PHYS_LEN     (16 << IDE_REG_SHIFT)
 #define DB1200_ETH_PHYS_ADDR    0x19000300
 #define DB1200_NAND_PHYS_ADDR   0x20000000
 
+#define PB1200_IDE_PHYS_ADDR    0x0C800000
+#define PB1200_ETH_PHYS_ADDR    0x0D000300
+#define PB1200_NAND_PHYS_ADDR   0x1C000000
+
 /*
  * External Interrupts for DBAu1200 as of 8/6/2004.
  * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
         DB1200_PC1_EJECT_INT,
         DB1200_SD0_INSERT_INT,
         DB1200_SD0_EJECT_INT,
+        PB1200_SD1_INSERT_INT,
+        PB1200_SD1_EJECT_INT,
 
         DB1200_INT_END          = DB1200_INT_BEGIN + 15,
 };
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
new file mode 100644
index 000000000000..7fe5fb3ba877
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -0,0 +1,40 @@
+/*
+ * NetLogic DB1300 board constants
+ */
+
+#ifndef _DB1300_H_
+#define _DB1300_H_
+
+/* FPGA (external mux) interrupt sources */
+#define DB1300_FIRST_INT        (ALCHEMY_GPIC_INT_LAST + 1)
+#define DB1300_IDE_INT          (DB1300_FIRST_INT + 0)
+#define DB1300_ETH_INT          (DB1300_FIRST_INT + 1)
+#define DB1300_CF_INT           (DB1300_FIRST_INT + 2)
+#define DB1300_VIDEO_INT        (DB1300_FIRST_INT + 4)
+#define DB1300_HDMI_INT         (DB1300_FIRST_INT + 5)
+#define DB1300_DC_INT           (DB1300_FIRST_INT + 6)
+#define DB1300_FLASH_INT        (DB1300_FIRST_INT + 7)
+#define DB1300_CF_INSERT_INT    (DB1300_FIRST_INT + 8)
+#define DB1300_CF_EJECT_INT     (DB1300_FIRST_INT + 9)
+#define DB1300_AC97_INT         (DB1300_FIRST_INT + 10)
+#define DB1300_AC97_PEN_INT     (DB1300_FIRST_INT + 11)
+#define DB1300_SD1_INSERT_INT   (DB1300_FIRST_INT + 12)
+#define DB1300_SD1_EJECT_INT    (DB1300_FIRST_INT + 13)
+#define DB1300_OTG_VBUS_OC_INT  (DB1300_FIRST_INT + 14)
+#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
+#define DB1300_LAST_INT         (DB1300_FIRST_INT + 15)
+
+/* SMSC9210 CS */
+#define DB1300_ETH_PHYS_ADDR    0x19000000
+#define DB1300_ETH_PHYS_END     0x197fffff
+
+/* ATA CS */
+#define DB1300_IDE_PHYS_ADDR    0x18800000
+#define DB1300_IDE_REG_SHIFT    5
+#define DB1300_IDE_PHYS_LEN     (16 << DB1300_IDE_REG_SHIFT)
+
+/* NAND CS */
+#define DB1300_NAND_PHYS_ADDR   0x20000000
+#define DB1300_NAND_PHYS_END    0x20000fff
+
+#endif  /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index a5affb0568ef..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * AMD Alchemy DBAu1x00 Reference Boards
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_DB1X00_H
-#define __ASM_DB1X00_H
-
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#ifdef CONFIG_MIPS_DB1550
-
-#define DBDMA_AC97_TX_CHAN      AU1550_DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      AU1550_DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       AU1550_DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN       AU1550_DSCR_CMD0_PSC3_RX
-
-#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
-#define AC97_PSC_BASE           AU1550_PSC1_PHYS_ADDR
-#define SMBUS_PSC_BASE          AU1550_PSC2_PHYS_ADDR
-#define I2S_PSC_BASE            AU1550_PSC3_PHYS_ADDR
-
-#define NAND_PHYS_ADDR          0x20000000
-
-#endif
-
-/*
- * NAND defines
- *
- * Timing values as described in databook, * ns value stripped of the
- * lower 2 bits.
- * These defines are here rather than an Au1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-#define NAND_CS         1
-
-/* Should be done by YAMON */
-#define NAND_STCFG      0x00400005 /* 8-bit NAND */
-#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 000000000000..15b26693238f
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_IRQ_H
+#define __ASM_MACH_GENERIC_IRQ_H
+
+
+#ifdef NR_IRQS
+#undef NR_IRQS
+#endif
+
+#ifndef MIPS_CPU_IRQ_BASE
+#define MIPS_CPU_IRQ_BASE 0
+#endif
+
+/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
+#define NR_IRQS 152
+
+#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
deleted file mode 100644
index 622c58710e5b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
- *
- * RTC routines for PC style attached Dallas chip.
- */
-#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
-#define __ASM_MACH_AU1XX_MC146818RTC_H
-
-#include <asm/io.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#define RTC_PORT(x)     (0x0c000000 + (x))
-#define RTC_IRQ         8
-#define PB1500_RTC_ADDR 0x0c000000
-
-static inline unsigned char CMOS_READ(unsigned long offset)
-{
-        offset <<= 2;
-        return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
-{
-        offset <<= 2;
-        au_writel(data, offset + PB1500_RTC_ADDR);
-}
-
-#define RTC_ALWAYS_BCD  1
-
-#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
deleted file mode 100644
index 65059255dc1e..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Alchemy Semi Pb1000 Reference Board
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1000_H
-#define __ASM_PB1000_H
-
-/* PCMCIA PB1000 specific defines */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-#define PB1000_PCR              0xBE000000
-#  define PCR_SLOT_0_VPP0       (1 << 0)
-#  define PCR_SLOT_0_VPP1       (1 << 1)
-#  define PCR_SLOT_0_VCC0       (1 << 2)
-#  define PCR_SLOT_0_VCC1       (1 << 3)
-#  define PCR_SLOT_0_RST        (1 << 4)
-#  define PCR_SLOT_1_VPP0       (1 << 8)
-#  define PCR_SLOT_1_VPP1       (1 << 9)
-#  define PCR_SLOT_1_VCC0       (1 << 10)
-#  define PCR_SLOT_1_VCC1       (1 << 11)
-#  define PCR_SLOT_1_RST        (1 << 12)
-
-#define PB1000_MDR              0xBE000004
-#  define MDR_PI                (1 << 5)        /* PCMCIA int latch  */
-#  define MDR_EPI               (1 << 14)       /* enable PCMCIA int */
-#  define MDR_CPI               (1 << 15)       /* clear  PCMCIA int  */
-
-#define PB1000_ACR1             0xBE000008
-#  define ACR1_SLOT_0_CD1       (1 << 0)        /* card detect 1        */
-#  define ACR1_SLOT_0_CD2       (1 << 1)        /* card detect 2        */
-#  define ACR1_SLOT_0_READY     (1 << 2)        /* ready                */
-#  define ACR1_SLOT_0_STATUS    (1 << 3)        /* status change        */
-#  define ACR1_SLOT_0_VS1       (1 << 4)        /* voltage sense 1      */
-#  define ACR1_SLOT_0_VS2       (1 << 5)        /* voltage sense 2      */
-#  define ACR1_SLOT_0_INPACK    (1 << 6)        /* inpack pin status    */
-#  define ACR1_SLOT_1_CD1       (1 << 8)        /* card detect 1        */
-#  define ACR1_SLOT_1_CD2       (1 << 9)        /* card detect 2        */
-#  define ACR1_SLOT_1_READY     (1 << 10)       /* ready                */
-#  define ACR1_SLOT_1_STATUS    (1 << 11)       /* status change        */
-#  define ACR1_SLOT_1_VS1       (1 << 12)       /* voltage sense 1      */
-#  define ACR1_SLOT_1_VS2       (1 << 13)       /* voltage sense 2      */
-#  define ACR1_SLOT_1_INPACK    (1 << 14)       /* inpack pin status    */
-
-#define CPLD_AUX0               0xBE00000C
-#define CPLD_AUX1               0xBE000010
-#define CPLD_AUX2               0xBE000014
-
-/* Voltage levels */
-
-/* VPPEN1 - VPPEN0 */
-#define VPP_GND ((0 << 1) | (0 << 0))
-#define VPP_5V  ((1 << 1) | (0 << 0))
-#define VPP_3V  ((0 << 1) | (1 << 0))
-#define VPP_12V ((0 << 1) | (1 << 0))
-#define VPP_HIZ ((1 << 1) | (1 << 0))
-
-/* VCCEN1 - VCCEN0 */
-#define VCC_3V  ((0 << 1) | (1 << 0))
-#define VCC_5V  ((1 << 1) | (0 << 0))
-#define VCC_HIZ ((0 << 1) | (0 << 0))
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
deleted file mode 100644
index 374416adb65b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * AMD Alchemy Pb1200 Reference Board
- * Board Registers defines.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1200_H
-#define __ASM_PB1200_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN      AU1200_DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      AU1200_DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       AU1200_DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN       AU1200_DSCR_CMD0_PSC1_RX
-
-/*
- * SPI and SMB are muxed on the Pb1200 board.
- * Refer to board documentation.
- */
-#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
-#define SMBUS_PSC_BASE          AU1550_PSC0_PHYS_ADDR
-/*
- * AC97 and I2S are muxed on the Pb1200 board.
- * Refer to board documentation.
- */
-#define AC97_PSC_BASE       AU1550_PSC1_PHYS_ADDR
-#define I2S_PSC_BASE    AU1550_PSC1_PHYS_ADDR
-
-
-#define BCSR_SYSTEM_VDDI        0x001F
-#define BCSR_SYSTEM_POWEROFF    0x4000
-#define BCSR_SYSTEM_RESET       0x8000
-
-/* Bit positions for the different interrupt sources */
-#define BCSR_INT_IDE            0x0001
-#define BCSR_INT_ETH            0x0002
-#define BCSR_INT_PC0            0x0004
-#define BCSR_INT_PC0STSCHG      0x0008
-#define BCSR_INT_PC1            0x0010
-#define BCSR_INT_PC1STSCHG      0x0020
-#define BCSR_INT_DC             0x0040
-#define BCSR_INT_FLASHBUSY      0x0080
-#define BCSR_INT_PC0INSERT      0x0100
-#define BCSR_INT_PC0EJECT       0x0200
-#define BCSR_INT_PC1INSERT      0x0400
-#define BCSR_INT_PC1EJECT       0x0800
-#define BCSR_INT_SD0INSERT      0x1000
-#define BCSR_INT_SD0EJECT       0x2000
-#define BCSR_INT_SD1INSERT      0x4000
-#define BCSR_INT_SD1EJECT       0x8000
-
-#define SMC91C111_PHYS_ADDR     0x0D000300
-#define SMC91C111_INT           PB1200_ETH_INT
-
-#define IDE_PHYS_ADDR           0x0C800000
-#define IDE_REG_SHIFT           5
-#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
-#define IDE_INT                 PB1200_IDE_INT
-
-#define NAND_PHYS_ADDR  0x1C000000
-
-/*
- * Timing values as described in databook, * ns value stripped of
- * lower 2 bits.
- * These defines are here rather than an Au1200 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-
-/*
- * External Interrupts for Pb1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the PB1200_INT_BEGIN value.
- *
- *   Example: IDE bis pos is  = 64 - 64
- *            ETH bit pos is  = 65 - 64
- */
-enum external_pb1200_ints {
-        PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
-
-        PB1200_IDE_INT          = PB1200_INT_BEGIN,
-        PB1200_ETH_INT,
-        PB1200_PC0_INT,
-        PB1200_PC0_STSCHG_INT,
-        PB1200_PC1_INT,
-        PB1200_PC1_STSCHG_INT,
-        PB1200_DC_INT,
-        PB1200_FLASHBUSY_INT,
-        PB1200_PC0_INSERT_INT,
-        PB1200_PC0_EJECT_INT,
-        PB1200_PC1_INSERT_INT,
-        PB1200_PC1_EJECT_INT,
-        PB1200_SD0_INSERT_INT,
-        PB1200_SD0_EJECT_INT,
-        PB1200_SD1_INSERT_INT,
-        PB1200_SD1_EJECT_INT,
-
-        PB1200_INT_END          = PB1200_INT_BEGIN + 15
-};
-
-/* NAND chip select */
-#define NAND_CS 1
-
-#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88adebf1..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * AMD Alchemy Semi PB1550 Reference Board
- * Board Registers defines.
- *
- * Copyright 2004 Embedded Edge LLC.
- * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1550_H
-#define __ASM_PB1550_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN      AU1550_DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      AU1550_DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       AU1550_DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN       AU1550_DSCR_CMD0_PSC3_RX
-
-#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
-#define AC97_PSC_BASE           AU1550_PSC1_PHYS_ADDR
-#define SMBUS_PSC_BASE          AU1550_PSC2_PHYS_ADDR
-#define I2S_PSC_BASE            AU1550_PSC3_PHYS_ADDR
-
-/*
- * Timing values as described in databook, * ns value stripped of
- * lower 2 bits.
- * These defines are here rather than an SOC1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-
-#define NAND_CS 1
-
-/* Should be done by YAMON */
-#define NAND_STCFG      0x00400005 /* 8-bit NAND */
-#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_PB1550_H */