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authorJiri Kosina <jkosina@suse.cz>2013-01-29 04:48:30 -0500
committerJiri Kosina <jkosina@suse.cz>2013-01-29 04:48:30 -0500
commit617677295b53a40d0e54aac4cbbc216ffbc755dd (patch)
tree51b9e87213243ed5efff252c8e8d8fec4eebc588 /arch/mips/include
parent5c8d1b68e01a144813e38795fe6dbe7ebb506131 (diff)
parent6abb7c25775b7fb2225ad0508236d63ca710e65f (diff)
Merge branch 'master' into for-next
Conflicts: drivers/devfreq/exynos4_bus.c Sync with Linus' tree to be able to apply patches that are against newer code (mvneta).
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/Kbuild1
-rw-r--r--arch/mips/include/asm/bitops.h128
-rw-r--r--arch/mips/include/asm/compat.h2
-rw-r--r--arch/mips/include/asm/cpu.h6
-rw-r--r--arch/mips/include/asm/dma-mapping.h2
-rw-r--r--arch/mips/include/asm/fw/arc/types.h8
-rw-r--r--arch/mips/include/asm/hazards.h25
-rw-r--r--arch/mips/include/asm/hugetlb.h12
-rw-r--r--arch/mips/include/asm/io.h1
-rw-r--r--arch/mips/include/asm/irqflags.h207
-rw-r--r--arch/mips/include/asm/kexec.h27
-rw-r--r--arch/mips/include/asm/mach-ar7/war.h1
-rw-r--r--arch/mips/include/asm/mach-ath79/war.h1
-rw-r--r--arch/mips/include/asm/mach-au1x00/war.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx.h4
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/gpio.h154
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h35
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h29
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h21
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h17
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h1
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/war.h1
-rw-r--r--arch/mips/include/asm/mach-cobalt/war.h1
-rw-r--r--arch/mips/include/asm/mach-dec/war.h1
-rw-r--r--arch/mips/include/asm/mach-emma2rh/war.h1
-rw-r--r--arch/mips/include/asm/mach-generic/irq.h6
-rw-r--r--arch/mips/include/asm/mach-ip22/war.h1
-rw-r--r--arch/mips/include/asm/mach-ip27/war.h1
-rw-r--r--arch/mips/include/asm/mach-ip28/war.h1
-rw-r--r--arch/mips/include/asm/mach-ip32/war.h1
-rw-r--r--arch/mips/include/asm/mach-jazz/war.h1
-rw-r--r--arch/mips/include/asm/mach-jz4740/war.h1
-rw-r--r--arch/mips/include/asm/mach-lantiq/war.h1
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h3
-rw-r--r--arch/mips/include/asm/mach-lasat/war.h1
-rw-r--r--arch/mips/include/asm/mach-loongson/war.h1
-rw-r--r--arch/mips/include/asm/mach-loongson1/platform.h3
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-clk.h7
-rw-r--r--arch/mips/include/asm/mach-loongson1/war.h1
-rw-r--r--arch/mips/include/asm/mach-malta/war.h1
-rw-r--r--arch/mips/include/asm/mach-netlogic/irq.h4
-rw-r--r--arch/mips/include/asm/mach-netlogic/multi-node.h54
-rw-r--r--arch/mips/include/asm/mach-netlogic/war.h1
-rw-r--r--arch/mips/include/asm/mach-pnx833x/war.h1
-rw-r--r--arch/mips/include/asm/mach-pnx8550/war.h1
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h1
-rw-r--r--arch/mips/include/asm/mach-rc32434/war.h1
-rw-r--r--arch/mips/include/asm/mach-rm/war.h1
-rw-r--r--arch/mips/include/asm/mach-sead3/war.h1
-rw-r--r--arch/mips/include/asm/mach-sibyte/war.h1
-rw-r--r--arch/mips/include/asm/mach-tx39xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-tx49xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-vr41xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-wrppmc/war.h1
-rw-r--r--arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h48
-rw-r--r--arch/mips/include/asm/mach-yosemite/war.h25
-rw-r--r--arch/mips/include/asm/mipsregs.h10
-rw-r--r--arch/mips/include/asm/mmu_context.h6
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/netlogic/common.h51
-rw-r--r--arch/mips/include/asm/netlogic/interrupt.h2
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h142
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h44
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h1
-rw-r--r--arch/mips/include/asm/netlogic/xlr/fmn.h363
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h6
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-lmcx-defs.h3457
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h6
-rw-r--r--arch/mips/include/asm/octeon/octeon.h7
-rw-r--r--arch/mips/include/asm/page.h17
-rw-r--r--arch/mips/include/asm/pci.h4
-rw-r--r--arch/mips/include/asm/pgtable-64.h2
-rw-r--r--arch/mips/include/asm/pgtable-bits.h131
-rw-r--r--arch/mips/include/asm/pgtable.h179
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/war.h1
-rw-r--r--arch/mips/include/asm/processor.h6
-rw-r--r--arch/mips/include/asm/ptrace.h7
-rw-r--r--arch/mips/include/asm/sgiarcs.h8
-rw-r--r--arch/mips/include/asm/signal.h2
-rw-r--r--arch/mips/include/asm/smp.h6
-rw-r--r--arch/mips/include/asm/smvp.h19
-rw-r--r--arch/mips/include/asm/sparsemem.h2
-rw-r--r--arch/mips/include/asm/thread_info.h15
-rw-r--r--arch/mips/include/asm/time.h4
-rw-r--r--arch/mips/include/asm/titan_dep.h231
-rw-r--r--arch/mips/include/asm/war.h8
-rw-r--r--arch/mips/include/uapi/asm/ioctls.h3
-rw-r--r--arch/mips/include/uapi/asm/mman.h11
-rw-r--r--arch/mips/include/uapi/asm/signal.h6
-rw-r--r--arch/mips/include/uapi/asm/socket.h1
-rw-r--r--arch/mips/include/uapi/asm/unistd.h15
95 files changed, 4647 insertions, 994 deletions
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 533053d12ced..9b54b7a403d4 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -1 +1,2 @@
1# MIPS headers 1# MIPS headers
2generic-y += trace_clock.h
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 82ad35ce2b45..46ac73abd5ee 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -14,7 +14,6 @@
14#endif 14#endif
15 15
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <linux/irqflags.h>
18#include <linux/types.h> 17#include <linux/types.h>
19#include <asm/barrier.h> 18#include <asm/barrier.h>
20#include <asm/byteorder.h> /* sigh ... */ 19#include <asm/byteorder.h> /* sigh ... */
@@ -44,6 +43,24 @@
44#define smp_mb__before_clear_bit() smp_mb__before_llsc() 43#define smp_mb__before_clear_bit() smp_mb__before_llsc()
45#define smp_mb__after_clear_bit() smp_llsc_mb() 44#define smp_mb__after_clear_bit() smp_llsc_mb()
46 45
46
47/*
48 * These are the "slower" versions of the functions and are in bitops.c.
49 * These functions call raw_local_irq_{save,restore}().
50 */
51void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
52void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
53void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
54int __mips_test_and_set_bit(unsigned long nr,
55 volatile unsigned long *addr);
56int __mips_test_and_set_bit_lock(unsigned long nr,
57 volatile unsigned long *addr);
58int __mips_test_and_clear_bit(unsigned long nr,
59 volatile unsigned long *addr);
60int __mips_test_and_change_bit(unsigned long nr,
61 volatile unsigned long *addr);
62
63
47/* 64/*
48 * set_bit - Atomically set a bit in memory 65 * set_bit - Atomically set a bit in memory
49 * @nr: the bit to set 66 * @nr: the bit to set
@@ -57,7 +74,7 @@
57static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 74static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
58{ 75{
59 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 76 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
60 unsigned short bit = nr & SZLONG_MASK; 77 int bit = nr & SZLONG_MASK;
61 unsigned long temp; 78 unsigned long temp;
62 79
63 if (kernel_uses_llsc && R10000_LLSC_WAR) { 80 if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
92 : "=&r" (temp), "+m" (*m) 109 : "=&r" (temp), "+m" (*m)
93 : "ir" (1UL << bit)); 110 : "ir" (1UL << bit));
94 } while (unlikely(!temp)); 111 } while (unlikely(!temp));
95 } else { 112 } else
96 volatile unsigned long *a = addr; 113 __mips_set_bit(nr, addr);
97 unsigned long mask;
98 unsigned long flags;
99
100 a += nr >> SZLONG_LOG;
101 mask = 1UL << bit;
102 raw_local_irq_save(flags);
103 *a |= mask;
104 raw_local_irq_restore(flags);
105 }
106} 114}
107 115
108/* 116/*
@@ -118,7 +126,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
118static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 126static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
119{ 127{
120 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 128 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
121 unsigned short bit = nr & SZLONG_MASK; 129 int bit = nr & SZLONG_MASK;
122 unsigned long temp; 130 unsigned long temp;
123 131
124 if (kernel_uses_llsc && R10000_LLSC_WAR) { 132 if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
153 : "=&r" (temp), "+m" (*m) 161 : "=&r" (temp), "+m" (*m)
154 : "ir" (~(1UL << bit))); 162 : "ir" (~(1UL << bit)));
155 } while (unlikely(!temp)); 163 } while (unlikely(!temp));
156 } else { 164 } else
157 volatile unsigned long *a = addr; 165 __mips_clear_bit(nr, addr);
158 unsigned long mask;
159 unsigned long flags;
160
161 a += nr >> SZLONG_LOG;
162 mask = 1UL << bit;
163 raw_local_irq_save(flags);
164 *a &= ~mask;
165 raw_local_irq_restore(flags);
166 }
167} 166}
168 167
169/* 168/*
@@ -191,7 +190,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad
191 */ 190 */
192static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 191static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
193{ 192{
194 unsigned short bit = nr & SZLONG_MASK; 193 int bit = nr & SZLONG_MASK;
195 194
196 if (kernel_uses_llsc && R10000_LLSC_WAR) { 195 if (kernel_uses_llsc && R10000_LLSC_WAR) {
197 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 196 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
220 : "=&r" (temp), "+m" (*m) 219 : "=&r" (temp), "+m" (*m)
221 : "ir" (1UL << bit)); 220 : "ir" (1UL << bit));
222 } while (unlikely(!temp)); 221 } while (unlikely(!temp));
223 } else { 222 } else
224 volatile unsigned long *a = addr; 223 __mips_change_bit(nr, addr);
225 unsigned long mask;
226 unsigned long flags;
227
228 a += nr >> SZLONG_LOG;
229 mask = 1UL << bit;
230 raw_local_irq_save(flags);
231 *a ^= mask;
232 raw_local_irq_restore(flags);
233 }
234} 224}
235 225
236/* 226/*
@@ -244,7 +234,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
244static inline int test_and_set_bit(unsigned long nr, 234static inline int test_and_set_bit(unsigned long nr,
245 volatile unsigned long *addr) 235 volatile unsigned long *addr)
246{ 236{
247 unsigned short bit = nr & SZLONG_MASK; 237 int bit = nr & SZLONG_MASK;
248 unsigned long res; 238 unsigned long res;
249 239
250 smp_mb__before_llsc(); 240 smp_mb__before_llsc();
@@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr,
281 } while (unlikely(!res)); 271 } while (unlikely(!res));
282 272
283 res = temp & (1UL << bit); 273 res = temp & (1UL << bit);
284 } else { 274 } else
285 volatile unsigned long *a = addr; 275 res = __mips_test_and_set_bit(nr, addr);
286 unsigned long mask;
287 unsigned long flags;
288
289 a += nr >> SZLONG_LOG;
290 mask = 1UL << bit;
291 raw_local_irq_save(flags);
292 res = (mask & *a);
293 *a |= mask;
294 raw_local_irq_restore(flags);
295 }
296 276
297 smp_llsc_mb(); 277 smp_llsc_mb();
298 278
@@ -310,7 +290,7 @@ static inline int test_and_set_bit(unsigned long nr,
310static inline int test_and_set_bit_lock(unsigned long nr, 290static inline int test_and_set_bit_lock(unsigned long nr,
311 volatile unsigned long *addr) 291 volatile unsigned long *addr)
312{ 292{
313 unsigned short bit = nr & SZLONG_MASK; 293 int bit = nr & SZLONG_MASK;
314 unsigned long res; 294 unsigned long res;
315 295
316 if (kernel_uses_llsc && R10000_LLSC_WAR) { 296 if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
345 } while (unlikely(!res)); 325 } while (unlikely(!res));
346 326
347 res = temp & (1UL << bit); 327 res = temp & (1UL << bit);
348 } else { 328 } else
349 volatile unsigned long *a = addr; 329 res = __mips_test_and_set_bit_lock(nr, addr);
350 unsigned long mask;
351 unsigned long flags;
352
353 a += nr >> SZLONG_LOG;
354 mask = 1UL << bit;
355 raw_local_irq_save(flags);
356 res = (mask & *a);
357 *a |= mask;
358 raw_local_irq_restore(flags);
359 }
360 330
361 smp_llsc_mb(); 331 smp_llsc_mb();
362 332
@@ -373,7 +343,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
373static inline int test_and_clear_bit(unsigned long nr, 343static inline int test_and_clear_bit(unsigned long nr,
374 volatile unsigned long *addr) 344 volatile unsigned long *addr)
375{ 345{
376 unsigned short bit = nr & SZLONG_MASK; 346 int bit = nr & SZLONG_MASK;
377 unsigned long res; 347 unsigned long res;
378 348
379 smp_mb__before_llsc(); 349 smp_mb__before_llsc();
@@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr,
428 } while (unlikely(!res)); 398 } while (unlikely(!res));
429 399
430 res = temp & (1UL << bit); 400 res = temp & (1UL << bit);
431 } else { 401 } else
432 volatile unsigned long *a = addr; 402 res = __mips_test_and_clear_bit(nr, addr);
433 unsigned long mask;
434 unsigned long flags;
435
436 a += nr >> SZLONG_LOG;
437 mask = 1UL << bit;
438 raw_local_irq_save(flags);
439 res = (mask & *a);
440 *a &= ~mask;
441 raw_local_irq_restore(flags);
442 }
443 403
444 smp_llsc_mb(); 404 smp_llsc_mb();
445 405
@@ -457,7 +417,7 @@ static inline int test_and_clear_bit(unsigned long nr,
457static inline int test_and_change_bit(unsigned long nr, 417static inline int test_and_change_bit(unsigned long nr,
458 volatile unsigned long *addr) 418 volatile unsigned long *addr)
459{ 419{
460 unsigned short bit = nr & SZLONG_MASK; 420 int bit = nr & SZLONG_MASK;
461 unsigned long res; 421 unsigned long res;
462 422
463 smp_mb__before_llsc(); 423 smp_mb__before_llsc();
@@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr,
494 } while (unlikely(!res)); 454 } while (unlikely(!res));
495 455
496 res = temp & (1UL << bit); 456 res = temp & (1UL << bit);
497 } else { 457 } else
498 volatile unsigned long *a = addr; 458 res = __mips_test_and_change_bit(nr, addr);
499 unsigned long mask;
500 unsigned long flags;
501
502 a += nr >> SZLONG_LOG;
503 mask = 1UL << bit;
504 raw_local_irq_save(flags);
505 res = (mask & *a);
506 *a ^= mask;
507 raw_local_irq_restore(flags);
508 }
509 459
510 smp_llsc_mb(); 460 smp_llsc_mb();
511 461
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 58277e0e9cd4..3c5d1464b7bd 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -290,7 +290,7 @@ struct compat_shmid64_ds {
290 290
291static inline int is_compat_task(void) 291static inline int is_compat_task(void)
292{ 292{
293 return test_thread_flag(TIF_32BIT); 293 return test_thread_flag(TIF_32BIT_ADDR);
294} 294}
295 295
296#endif /* _ASM_COMPAT_H */ 296#endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 52c4e914f95a..90112adb1940 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -243,9 +243,9 @@ enum cpu_type_enum {
243 */ 243 */
244 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 244 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
245 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 245 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
246 CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, 246 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
247 CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, 247 CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
248 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 248 CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
249 CPU_SR71000, CPU_RM9000, CPU_TX49XX, 249 CPU_SR71000, CPU_RM9000, CPU_TX49XX,
250 250
251 /* 251 /*
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index be39a12901c6..006b43e38a9c 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -40,6 +40,8 @@ static inline int dma_supported(struct device *dev, u64 mask)
40static inline int dma_mapping_error(struct device *dev, u64 mask) 40static inline int dma_mapping_error(struct device *dev, u64 mask)
41{ 41{
42 struct dma_map_ops *ops = get_dma_ops(dev); 42 struct dma_map_ops *ops = get_dma_ops(dev);
43
44 debug_dma_mapping_error(dev, mask);
43 return ops->mapping_error(dev, mask); 45 return ops->mapping_error(dev, mask);
44} 46}
45 47
diff --git a/arch/mips/include/asm/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h
index b9adcd6f0860..2b11f87d6fb3 100644
--- a/arch/mips/include/asm/fw/arc/types.h
+++ b/arch/mips/include/asm/fw/arc/types.h
@@ -10,7 +10,7 @@
10#define _ASM_ARC_TYPES_H 10#define _ASM_ARC_TYPES_H
11 11
12 12
13#ifdef CONFIG_ARC32 13#ifdef CONFIG_FW_ARC32
14 14
15typedef char CHAR; 15typedef char CHAR;
16typedef short SHORT; 16typedef short SHORT;
@@ -33,9 +33,9 @@ typedef LONG _PUSHORT;
33typedef LONG _PULONG; 33typedef LONG _PULONG;
34typedef LONG _PVOID; 34typedef LONG _PVOID;
35 35
36#endif /* CONFIG_ARC32 */ 36#endif /* CONFIG_FW_ARC32 */
37 37
38#ifdef CONFIG_ARC64 38#ifdef CONFIG_FW_ARC64
39 39
40typedef char CHAR; 40typedef char CHAR;
41typedef short SHORT; 41typedef short SHORT;
@@ -57,7 +57,7 @@ typedef USHORT *_PUSHORT;
57typedef ULONG *_PULONG; 57typedef ULONG *_PULONG;
58typedef VOID *_PVOID; 58typedef VOID *_PVOID;
59 59
60#endif /* CONFIG_ARC64 */ 60#endif /* CONFIG_FW_ARC64 */
61 61
62typedef CHAR *PCHAR; 62typedef CHAR *PCHAR;
63typedef SHORT *PSHORT; 63typedef SHORT *PSHORT;
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index b4c20e4f87cd..f0324e92d089 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -161,31 +161,6 @@ ASMMACRO(back_to_back_c0_hazard,
161 ) 161 )
162#define instruction_hazard() do { } while (0) 162#define instruction_hazard() do { } while (0)
163 163
164#elif defined(CONFIG_CPU_RM9000)
165
166/*
167 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
168 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
169 * for data translations should not occur for 3 cpu cycles.
170 */
171
172ASMMACRO(mtc0_tlbw_hazard,
173 _ssnop; _ssnop; _ssnop; _ssnop
174 )
175ASMMACRO(tlbw_use_hazard,
176 _ssnop; _ssnop; _ssnop; _ssnop
177 )
178ASMMACRO(tlb_probe_hazard,
179 _ssnop; _ssnop; _ssnop; _ssnop
180 )
181ASMMACRO(irq_enable_hazard,
182 )
183ASMMACRO(irq_disable_hazard,
184 )
185ASMMACRO(back_to_back_c0_hazard,
186 )
187#define instruction_hazard() do { } while (0)
188
189#elif defined(CONFIG_CPU_SB1) 164#elif defined(CONFIG_CPU_SB1)
190 165
191/* 166/*
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index bd94946a18f3..ef99db994c2f 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -95,7 +95,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
95 pte_t *ptep, pte_t pte, 95 pte_t *ptep, pte_t pte,
96 int dirty) 96 int dirty)
97{ 97{
98 return ptep_set_access_flags(vma, addr, ptep, pte, dirty); 98 int changed = !pte_same(*ptep, pte);
99
100 if (changed) {
101 set_pte_at(vma->vm_mm, addr, ptep, pte);
102 /*
103 * There could be some standard sized pages in there,
104 * get them all.
105 */
106 flush_tlb_range(vma, addr, addr + HPAGE_SIZE);
107 }
108 return changed;
99} 109}
100 110
101static inline pte_t huge_ptep_get(pte_t *ptep) 111static inline pte_t huge_ptep_get(pte_t *ptep)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 29d9c23c20c7..ff2e0345e013 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -15,6 +15,7 @@
15#include <linux/compiler.h> 15#include <linux/compiler.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/types.h> 17#include <linux/types.h>
18#include <linux/irqflags.h>
18 19
19#include <asm/addrspace.h> 20#include <asm/addrspace.h>
20#include <asm/bug.h> 21#include <asm/bug.h>
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 309cbcd6909c..9f3384c789d7 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -16,83 +16,13 @@
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <asm/hazards.h> 17#include <asm/hazards.h>
18 18
19__asm__( 19#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)
20 " .macro arch_local_irq_enable \n"
21 " .set push \n"
22 " .set reorder \n"
23 " .set noat \n"
24#ifdef CONFIG_MIPS_MT_SMTC
25 " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
26 " ori $1, 0x400 \n"
27 " xori $1, 0x400 \n"
28 " mtc0 $1, $2, 1 \n"
29#elif defined(CONFIG_CPU_MIPSR2)
30 " ei \n"
31#else
32 " mfc0 $1,$12 \n"
33 " ori $1,0x1f \n"
34 " xori $1,0x1e \n"
35 " mtc0 $1,$12 \n"
36#endif
37 " irq_enable_hazard \n"
38 " .set pop \n"
39 " .endm");
40 20
41extern void smtc_ipi_replay(void);
42
43static inline void arch_local_irq_enable(void)
44{
45#ifdef CONFIG_MIPS_MT_SMTC
46 /*
47 * SMTC kernel needs to do a software replay of queued
48 * IPIs, at the cost of call overhead on each local_irq_enable()
49 */
50 smtc_ipi_replay();
51#endif
52 __asm__ __volatile__(
53 "arch_local_irq_enable"
54 : /* no outputs */
55 : /* no inputs */
56 : "memory");
57}
58
59
60/*
61 * For cli() we have to insert nops to make sure that the new value
62 * has actually arrived in the status register before the end of this
63 * macro.
64 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
65 * no nops at all.
66 */
67/*
68 * For TX49, operating only IE bit is not enough.
69 *
70 * If mfc0 $12 follows store and the mfc0 is last instruction of a
71 * page and fetching the next instruction causes TLB miss, the result
72 * of the mfc0 might wrongly contain EXL bit.
73 *
74 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
75 *
76 * Workaround: mask EXL bit of the result or place a nop before mfc0.
77 */
78__asm__( 21__asm__(
79 " .macro arch_local_irq_disable\n" 22 " .macro arch_local_irq_disable\n"
80 " .set push \n" 23 " .set push \n"
81 " .set noat \n" 24 " .set noat \n"
82#ifdef CONFIG_MIPS_MT_SMTC
83 " mfc0 $1, $2, 1 \n"
84 " ori $1, 0x400 \n"
85 " .set noreorder \n"
86 " mtc0 $1, $2, 1 \n"
87#elif defined(CONFIG_CPU_MIPSR2)
88 " di \n" 25 " di \n"
89#else
90 " mfc0 $1,$12 \n"
91 " ori $1,0x1f \n"
92 " xori $1,0x1f \n"
93 " .set noreorder \n"
94 " mtc0 $1,$12 \n"
95#endif
96 " irq_disable_hazard \n" 26 " irq_disable_hazard \n"
97 " .set pop \n" 27 " .set pop \n"
98 " .endm \n"); 28 " .endm \n");
@@ -106,46 +36,14 @@ static inline void arch_local_irq_disable(void)
106 : "memory"); 36 : "memory");
107} 37}
108 38
109__asm__(
110 " .macro arch_local_save_flags flags \n"
111 " .set push \n"
112 " .set reorder \n"
113#ifdef CONFIG_MIPS_MT_SMTC
114 " mfc0 \\flags, $2, 1 \n"
115#else
116 " mfc0 \\flags, $12 \n"
117#endif
118 " .set pop \n"
119 " .endm \n");
120
121static inline unsigned long arch_local_save_flags(void)
122{
123 unsigned long flags;
124 asm volatile("arch_local_save_flags %0" : "=r" (flags));
125 return flags;
126}
127 39
128__asm__( 40__asm__(
129 " .macro arch_local_irq_save result \n" 41 " .macro arch_local_irq_save result \n"
130 " .set push \n" 42 " .set push \n"
131 " .set reorder \n" 43 " .set reorder \n"
132 " .set noat \n" 44 " .set noat \n"
133#ifdef CONFIG_MIPS_MT_SMTC
134 " mfc0 \\result, $2, 1 \n"
135 " ori $1, \\result, 0x400 \n"
136 " .set noreorder \n"
137 " mtc0 $1, $2, 1 \n"
138 " andi \\result, \\result, 0x400 \n"
139#elif defined(CONFIG_CPU_MIPSR2)
140 " di \\result \n" 45 " di \\result \n"
141 " andi \\result, 1 \n" 46 " andi \\result, 1 \n"
142#else
143 " mfc0 \\result, $12 \n"
144 " ori $1, \\result, 0x1f \n"
145 " xori $1, 0x1f \n"
146 " .set noreorder \n"
147 " mtc0 $1, $12 \n"
148#endif
149 " irq_disable_hazard \n" 47 " irq_disable_hazard \n"
150 " .set pop \n" 48 " .set pop \n"
151 " .endm \n"); 49 " .endm \n");
@@ -160,61 +58,37 @@ static inline unsigned long arch_local_irq_save(void)
160 return flags; 58 return flags;
161} 59}
162 60
61
163__asm__( 62__asm__(
164 " .macro arch_local_irq_restore flags \n" 63 " .macro arch_local_irq_restore flags \n"
165 " .set push \n" 64 " .set push \n"
166 " .set noreorder \n" 65 " .set noreorder \n"
167 " .set noat \n" 66 " .set noat \n"
168#ifdef CONFIG_MIPS_MT_SMTC 67#if defined(CONFIG_IRQ_CPU)
169 "mfc0 $1, $2, 1 \n"
170 "andi \\flags, 0x400 \n"
171 "ori $1, 0x400 \n"
172 "xori $1, 0x400 \n"
173 "or \\flags, $1 \n"
174 "mtc0 \\flags, $2, 1 \n"
175#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
176 /* 68 /*
177 * Slow, but doesn't suffer from a relatively unlikely race 69 * Slow, but doesn't suffer from a relatively unlikely race
178 * condition we're having since days 1. 70 * condition we're having since days 1.
179 */ 71 */
180 " beqz \\flags, 1f \n" 72 " beqz \\flags, 1f \n"
181 " di \n" 73 " di \n"
182 " ei \n" 74 " ei \n"
183 "1: \n" 75 "1: \n"
184#elif defined(CONFIG_CPU_MIPSR2) 76#else
185 /* 77 /*
186 * Fast, dangerous. Life is fun, life is good. 78 * Fast, dangerous. Life is fun, life is good.
187 */ 79 */
188 " mfc0 $1, $12 \n" 80 " mfc0 $1, $12 \n"
189 " ins $1, \\flags, 0, 1 \n" 81 " ins $1, \\flags, 0, 1 \n"
190 " mtc0 $1, $12 \n" 82 " mtc0 $1, $12 \n"
191#else
192 " mfc0 $1, $12 \n"
193 " andi \\flags, 1 \n"
194 " ori $1, 0x1f \n"
195 " xori $1, 0x1f \n"
196 " or \\flags, $1 \n"
197 " mtc0 \\flags, $12 \n"
198#endif 83#endif
199 " irq_disable_hazard \n" 84 " irq_disable_hazard \n"
200 " .set pop \n" 85 " .set pop \n"
201 " .endm \n"); 86 " .endm \n");
202 87
203
204static inline void arch_local_irq_restore(unsigned long flags) 88static inline void arch_local_irq_restore(unsigned long flags)
205{ 89{
206 unsigned long __tmp1; 90 unsigned long __tmp1;
207 91
208#ifdef CONFIG_MIPS_MT_SMTC
209 /*
210 * SMTC kernel needs to do a software replay of queued
211 * IPIs, at the cost of branch and call overhead on each
212 * local_irq_restore()
213 */
214 if (unlikely(!(flags & 0x0400)))
215 smtc_ipi_replay();
216#endif
217
218 __asm__ __volatile__( 92 __asm__ __volatile__(
219 "arch_local_irq_restore\t%0" 93 "arch_local_irq_restore\t%0"
220 : "=r" (__tmp1) 94 : "=r" (__tmp1)
@@ -232,6 +106,75 @@ static inline void __arch_local_irq_restore(unsigned long flags)
232 : "0" (flags) 106 : "0" (flags)
233 : "memory"); 107 : "memory");
234} 108}
109#else
110/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
111void arch_local_irq_disable(void);
112unsigned long arch_local_irq_save(void);
113void arch_local_irq_restore(unsigned long flags);
114void __arch_local_irq_restore(unsigned long flags);
115#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */
116
117
118__asm__(
119 " .macro arch_local_irq_enable \n"
120 " .set push \n"
121 " .set reorder \n"
122 " .set noat \n"
123#ifdef CONFIG_MIPS_MT_SMTC
124 " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
125 " ori $1, 0x400 \n"
126 " xori $1, 0x400 \n"
127 " mtc0 $1, $2, 1 \n"
128#elif defined(CONFIG_CPU_MIPSR2)
129 " ei \n"
130#else
131 " mfc0 $1,$12 \n"
132 " ori $1,0x1f \n"
133 " xori $1,0x1e \n"
134 " mtc0 $1,$12 \n"
135#endif
136 " irq_enable_hazard \n"
137 " .set pop \n"
138 " .endm");
139
140extern void smtc_ipi_replay(void);
141
142static inline void arch_local_irq_enable(void)
143{
144#ifdef CONFIG_MIPS_MT_SMTC
145 /*
146 * SMTC kernel needs to do a software replay of queued
147 * IPIs, at the cost of call overhead on each local_irq_enable()
148 */
149 smtc_ipi_replay();
150#endif
151 __asm__ __volatile__(
152 "arch_local_irq_enable"
153 : /* no outputs */
154 : /* no inputs */
155 : "memory");
156}
157
158
159__asm__(
160 " .macro arch_local_save_flags flags \n"
161 " .set push \n"
162 " .set reorder \n"
163#ifdef CONFIG_MIPS_MT_SMTC
164 " mfc0 \\flags, $2, 1 \n"
165#else
166 " mfc0 \\flags, $12 \n"
167#endif
168 " .set pop \n"
169 " .endm \n");
170
171static inline unsigned long arch_local_save_flags(void)
172{
173 unsigned long flags;
174 asm volatile("arch_local_save_flags %0" : "=r" (flags));
175 return flags;
176}
177
235 178
236static inline int arch_irqs_disabled_flags(unsigned long flags) 179static inline int arch_irqs_disabled_flags(unsigned long flags)
237{ 180{
@@ -245,7 +188,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
245#endif 188#endif
246} 189}
247 190
248#endif 191#endif /* #ifndef __ASSEMBLY__ */
249 192
250/* 193/*
251 * Do the CPU's IRQ-state tracing from assembly code. 194 * Do the CPU's IRQ-state tracing from assembly code.
diff --git a/arch/mips/include/asm/kexec.h b/arch/mips/include/asm/kexec.h
index 4314892aaebb..ee25ebbf2a28 100644
--- a/arch/mips/include/asm/kexec.h
+++ b/arch/mips/include/asm/kexec.h
@@ -9,22 +9,43 @@
9#ifndef _MIPS_KEXEC 9#ifndef _MIPS_KEXEC
10# define _MIPS_KEXEC 10# define _MIPS_KEXEC
11 11
12#include <asm/stacktrace.h>
13
12/* Maximum physical address we can use pages from */ 14/* Maximum physical address we can use pages from */
13#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000) 15#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
14/* Maximum address we can reach in physical address mode */ 16/* Maximum address we can reach in physical address mode */
15#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000) 17#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
16 /* Maximum address we can use for the control code buffer */ 18 /* Maximum address we can use for the control code buffer */
17#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000) 19#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
18 20/* Reserve 3*4096 bytes for board-specific info */
19#define KEXEC_CONTROL_PAGE_SIZE 4096 21#define KEXEC_CONTROL_PAGE_SIZE (4096 + 3*4096)
20 22
21/* The native architecture */ 23/* The native architecture */
22#define KEXEC_ARCH KEXEC_ARCH_MIPS 24#define KEXEC_ARCH KEXEC_ARCH_MIPS
25#define MAX_NOTE_BYTES 1024
23 26
24static inline void crash_setup_regs(struct pt_regs *newregs, 27static inline void crash_setup_regs(struct pt_regs *newregs,
25 struct pt_regs *oldregs) 28 struct pt_regs *oldregs)
26{ 29{
27 /* Dummy implementation for now */ 30 if (oldregs)
31 memcpy(newregs, oldregs, sizeof(*newregs));
32 else
33 prepare_frametrace(newregs);
28} 34}
29 35
36#ifdef CONFIG_KEXEC
37struct kimage;
38extern unsigned long kexec_args[4];
39extern int (*_machine_kexec_prepare)(struct kimage *);
40extern void (*_machine_kexec_shutdown)(void);
41extern void (*_machine_crash_shutdown)(struct pt_regs *regs);
42extern void default_machine_crash_shutdown(struct pt_regs *regs);
43#ifdef CONFIG_SMP
44extern const unsigned char kexec_smp_wait[];
45extern unsigned long secondary_kexec_args[4];
46extern void (*relocated_kexec_smp_wait) (void *);
47extern atomic_t kexec_ready_to_reboot;
48#endif
49#endif
50
30#endif /* !_MIPS_KEXEC */ 51#endif /* !_MIPS_KEXEC */
diff --git a/arch/mips/include/asm/mach-ar7/war.h b/arch/mips/include/asm/mach-ar7/war.h
index f4862b563080..99071e50faab 100644
--- a/arch/mips/include/asm/mach-ar7/war.h
+++ b/arch/mips/include/asm/mach-ar7/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h
index 323d9f1d8c45..0bb30905fd5b 100644
--- a/arch/mips/include/asm/mach-ath79/war.h
+++ b/arch/mips/include/asm/mach-ath79/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
index dd57d03d68ba..72e260d24e59 100644
--- a/arch/mips/include/asm/mach-au1x00/war.h
+++ b/arch/mips/include/asm/mach-au1x00/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index 26fdaf40b930..cc7563ba1cbf 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -44,8 +44,8 @@ union bcm47xx_bus {
44extern union bcm47xx_bus bcm47xx_bus; 44extern union bcm47xx_bus bcm47xx_bus;
45extern enum bcm47xx_bus_type bcm47xx_bus_type; 45extern enum bcm47xx_bus_type bcm47xx_bus_type;
46 46
47void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix); 47void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
48void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, const char *prefix); 48 bool fallback);
49 49
50#ifdef CONFIG_BCM47XX_SSB 50#ifdef CONFIG_BCM47XX_SSB
51void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo, 51void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index 2ef17e8df403..90daefa24a4d 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -1,155 +1,17 @@
1/* 1#ifndef __ASM_MIPS_MACH_BCM47XX_GPIO_H
2 * This file is subject to the terms and conditions of the GNU General Public 2#define __ASM_MIPS_MACH_BCM47XX_GPIO_H
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8 3
9#ifndef __BCM47XX_GPIO_H 4#include <asm-generic/gpio.h>
10#define __BCM47XX_GPIO_H
11 5
12#include <linux/ssb/ssb_embedded.h> 6#define gpio_get_value __gpio_get_value
13#include <linux/bcma/bcma.h> 7#define gpio_set_value __gpio_set_value
14#include <asm/mach-bcm47xx/bcm47xx.h>
15 8
16#define BCM47XX_EXTIF_GPIO_LINES 5 9#define gpio_cansleep __gpio_cansleep
17#define BCM47XX_CHIPCO_GPIO_LINES 16 10#define gpio_to_irq __gpio_to_irq
18 11
19extern int gpio_request(unsigned gpio, const char *label); 12static inline int irq_to_gpio(unsigned int irq)
20extern void gpio_free(unsigned gpio);
21extern int gpio_to_irq(unsigned gpio);
22
23static inline int gpio_get_value(unsigned gpio)
24{ 13{
25 switch (bcm47xx_bus_type) {
26#ifdef CONFIG_BCM47XX_SSB
27 case BCM47XX_BUS_TYPE_SSB:
28 return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
29#endif
30#ifdef CONFIG_BCM47XX_BCMA
31 case BCM47XX_BUS_TYPE_BCMA:
32 return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc,
33 1 << gpio);
34#endif
35 }
36 return -EINVAL; 14 return -EINVAL;
37} 15}
38 16
39#define gpio_get_value_cansleep gpio_get_value
40
41static inline void gpio_set_value(unsigned gpio, int value)
42{
43 switch (bcm47xx_bus_type) {
44#ifdef CONFIG_BCM47XX_SSB
45 case BCM47XX_BUS_TYPE_SSB:
46 ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
47 value ? 1 << gpio : 0);
48 return;
49#endif
50#ifdef CONFIG_BCM47XX_BCMA
51 case BCM47XX_BUS_TYPE_BCMA:
52 bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
53 value ? 1 << gpio : 0);
54 return;
55#endif 17#endif
56 }
57}
58
59#define gpio_set_value_cansleep gpio_set_value
60
61static inline int gpio_cansleep(unsigned gpio)
62{
63 return 0;
64}
65
66static inline int gpio_is_valid(unsigned gpio)
67{
68 return gpio < (BCM47XX_EXTIF_GPIO_LINES + BCM47XX_CHIPCO_GPIO_LINES);
69}
70
71
72static inline int gpio_direction_input(unsigned gpio)
73{
74 switch (bcm47xx_bus_type) {
75#ifdef CONFIG_BCM47XX_SSB
76 case BCM47XX_BUS_TYPE_SSB:
77 ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
78 return 0;
79#endif
80#ifdef CONFIG_BCM47XX_BCMA
81 case BCM47XX_BUS_TYPE_BCMA:
82 bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
83 0);
84 return 0;
85#endif
86 }
87 return -EINVAL;
88}
89
90static inline int gpio_direction_output(unsigned gpio, int value)
91{
92 switch (bcm47xx_bus_type) {
93#ifdef CONFIG_BCM47XX_SSB
94 case BCM47XX_BUS_TYPE_SSB:
95 /* first set the gpio out value */
96 ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
97 value ? 1 << gpio : 0);
98 /* then set the gpio mode */
99 ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
100 return 0;
101#endif
102#ifdef CONFIG_BCM47XX_BCMA
103 case BCM47XX_BUS_TYPE_BCMA:
104 /* first set the gpio out value */
105 bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
106 value ? 1 << gpio : 0);
107 /* then set the gpio mode */
108 bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
109 1 << gpio);
110 return 0;
111#endif
112 }
113 return -EINVAL;
114}
115
116static inline int gpio_intmask(unsigned gpio, int value)
117{
118 switch (bcm47xx_bus_type) {
119#ifdef CONFIG_BCM47XX_SSB
120 case BCM47XX_BUS_TYPE_SSB:
121 ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio,
122 value ? 1 << gpio : 0);
123 return 0;
124#endif
125#ifdef CONFIG_BCM47XX_BCMA
126 case BCM47XX_BUS_TYPE_BCMA:
127 bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
128 1 << gpio, value ? 1 << gpio : 0);
129 return 0;
130#endif
131 }
132 return -EINVAL;
133}
134
135static inline int gpio_polarity(unsigned gpio, int value)
136{
137 switch (bcm47xx_bus_type) {
138#ifdef CONFIG_BCM47XX_SSB
139 case BCM47XX_BUS_TYPE_SSB:
140 ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio,
141 value ? 1 << gpio : 0);
142 return 0;
143#endif
144#ifdef CONFIG_BCM47XX_BCMA
145 case BCM47XX_BUS_TYPE_BCMA:
146 bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
147 1 << gpio, value ? 1 << gpio : 0);
148 return 0;
149#endif
150 }
151 return -EINVAL;
152}
153
154
155#endif /* __BCM47XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
index 87cd4651dda3..a3d2f448b10e 100644
--- a/arch/mips/include/asm/mach-bcm47xx/war.h
+++ b/arch/mips/include/asm/mach-bcm47xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
new file mode 100644
index 000000000000..62d6a3b4d3b7
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -0,0 +1,35 @@
1#ifndef BCM63XX_NVRAM_H
2#define BCM63XX_NVRAM_H
3
4#include <linux/types.h>
5
6/**
7 * bcm63xx_nvram_init() - initializes nvram
8 * @nvram: address of the nvram data
9 *
10 * Initialized the local nvram copy from the target address and checks
11 * its checksum.
12 *
13 * Returns 0 on success.
14 */
15int __init bcm63xx_nvram_init(void *nvram);
16
17/**
18 * bcm63xx_nvram_get_name() - returns the board name according to nvram
19 *
20 * Returns the board name field from nvram. Note that it might not be
21 * null terminated if it is exactly 16 bytes long.
22 */
23u8 *bcm63xx_nvram_get_name(void);
24
25/**
26 * bcm63xx_nvram_get_mac_address() - register & return a new mac address
27 * @mac: pointer to array for allocated mac
28 *
29 * Registers and returns a mac address from the allocated macs from nvram.
30 *
31 * Returns 0 on success.
32 */
33int bcm63xx_nvram_get_mac_address(u8 *mac);
34
35#endif /* BCM63XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 12963d05da86..c3eeb90b480a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -53,13 +53,18 @@
53 CKCTL_6338_SAR_EN | \ 53 CKCTL_6338_SAR_EN | \
54 CKCTL_6338_SPI_EN) 54 CKCTL_6338_SPI_EN)
55 55
56#define CKCTL_6345_CPU_EN (1 << 0) 56/* BCM6345 clock bits are shifted by 16 on the left, because of the test
57#define CKCTL_6345_BUS_EN (1 << 1) 57 * control register which is 16-bits wide. That way we do not have any
58#define CKCTL_6345_EBI_EN (1 << 2) 58 * specific BCM6345 code for handling clocks, and writing 0 to the test
59#define CKCTL_6345_UART_EN (1 << 3) 59 * control register is fine.
60#define CKCTL_6345_ADSLPHY_EN (1 << 4) 60 */
61#define CKCTL_6345_ENET_EN (1 << 7) 61#define CKCTL_6345_CPU_EN (1 << 16)
62#define CKCTL_6345_USBH_EN (1 << 8) 62#define CKCTL_6345_BUS_EN (1 << 17)
63#define CKCTL_6345_EBI_EN (1 << 18)
64#define CKCTL_6345_UART_EN (1 << 19)
65#define CKCTL_6345_ADSLPHY_EN (1 << 20)
66#define CKCTL_6345_ENET_EN (1 << 23)
67#define CKCTL_6345_USBH_EN (1 << 24)
63 68
64#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ 69#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
65 CKCTL_6345_USBH_EN | \ 70 CKCTL_6345_USBH_EN | \
@@ -191,6 +196,7 @@
191/* Soft Reset register */ 196/* Soft Reset register */
192#define PERF_SOFTRESET_REG 0x28 197#define PERF_SOFTRESET_REG 0x28
193#define PERF_SOFTRESET_6328_REG 0x10 198#define PERF_SOFTRESET_6328_REG 0x10
199#define PERF_SOFTRESET_6358_REG 0x34
194#define PERF_SOFTRESET_6368_REG 0x10 200#define PERF_SOFTRESET_6368_REG 0x10
195 201
196#define SOFTRESET_6328_SPI_MASK (1 << 0) 202#define SOFTRESET_6328_SPI_MASK (1 << 0)
@@ -244,6 +250,15 @@
244 SOFTRESET_6348_ACLC_MASK | \ 250 SOFTRESET_6348_ACLC_MASK | \
245 SOFTRESET_6348_ADSLMIPSPLL_MASK) 251 SOFTRESET_6348_ADSLMIPSPLL_MASK)
246 252
253#define SOFTRESET_6358_SPI_MASK (1 << 0)
254#define SOFTRESET_6358_ENET_MASK (1 << 2)
255#define SOFTRESET_6358_MPI_MASK (1 << 3)
256#define SOFTRESET_6358_EPHY_MASK (1 << 6)
257#define SOFTRESET_6358_SAR_MASK (1 << 7)
258#define SOFTRESET_6358_USBH_MASK (1 << 12)
259#define SOFTRESET_6358_PCM_MASK (1 << 13)
260#define SOFTRESET_6358_ADSL_MASK (1 << 14)
261
247#define SOFTRESET_6368_SPI_MASK (1 << 0) 262#define SOFTRESET_6368_SPI_MASK (1 << 0)
248#define SOFTRESET_6368_MPI_MASK (1 << 3) 263#define SOFTRESET_6368_MPI_MASK (1 << 3)
249#define SOFTRESET_6368_EPHY_MASK (1 << 6) 264#define SOFTRESET_6368_EPHY_MASK (1 << 6)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
new file mode 100644
index 000000000000..3a6eb9c1adc6
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
@@ -0,0 +1,21 @@
1#ifndef __BCM63XX_RESET_H
2#define __BCM63XX_RESET_H
3
4enum bcm63xx_core_reset {
5 BCM63XX_RESET_SPI,
6 BCM63XX_RESET_ENET,
7 BCM63XX_RESET_USBH,
8 BCM63XX_RESET_USBD,
9 BCM63XX_RESET_SAR,
10 BCM63XX_RESET_DSL,
11 BCM63XX_RESET_EPHY,
12 BCM63XX_RESET_ENETSW,
13 BCM63XX_RESET_PCM,
14 BCM63XX_RESET_MPI,
15 BCM63XX_RESET_PCIE,
16 BCM63XX_RESET_PCIE_EXT,
17};
18
19void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
20
21#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index b0dd4bb53f7e..682bcf3b492a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -15,23 +15,6 @@
15#define BCM963XX_NVRAM_OFFSET 0x580 15#define BCM963XX_NVRAM_OFFSET 0x580
16 16
17/* 17/*
18 * nvram structure
19 */
20struct bcm963xx_nvram {
21 u32 version;
22 u8 reserved1[256];
23 u8 name[16];
24 u32 main_tp_number;
25 u32 psi_size;
26 u32 mac_addr_count;
27 u8 mac_addr_base[6];
28 u8 reserved2[2];
29 u32 checksum_old;
30 u8 reserved3[720];
31 u32 checksum_high;
32};
33
34/*
35 * board definition 18 * board definition
36 */ 19 */
37struct board_info { 20struct board_info {
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
index 8e3f3fdf3209..05ee8671bef1 100644
--- a/arch/mips/include/asm/mach-bcm63xx/war.h
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index ff0d4909d848..502bb1815ae8 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -42,7 +42,6 @@ enum octeon_irq {
42 OCTEON_IRQ_TIMER3, 42 OCTEON_IRQ_TIMER3,
43 OCTEON_IRQ_USB0, 43 OCTEON_IRQ_USB0,
44 OCTEON_IRQ_USB1, 44 OCTEON_IRQ_USB1,
45 OCTEON_IRQ_BOOTDMA,
46#ifndef CONFIG_PCI_MSI 45#ifndef CONFIG_PCI_MSI
47 OCTEON_IRQ_LAST = 127 46 OCTEON_IRQ_LAST = 127
48#endif 47#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index c4712d7cc81d..eb72b35cf04b 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -18,7 +18,6 @@
18#define MIPS4K_ICACHE_REFILL_WAR 0 18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0 19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0 20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0 21#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
index 97884fd18ac0..34ae4046541e 100644
--- a/arch/mips/include/asm/mach-cobalt/war.h
+++ b/arch/mips/include/asm/mach-cobalt/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
index ca5e2ef909ad..d29996feb3e7 100644
--- a/arch/mips/include/asm/mach-dec/war.h
+++ b/arch/mips/include/asm/mach-dec/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
index b660a4c30e6a..79ae82da3ec7 100644
--- a/arch/mips/include/asm/mach-emma2rh/war.h
+++ b/arch/mips/include/asm/mach-emma2rh/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index 70d9a25132c5..e014264b2be2 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -34,12 +34,6 @@
34#endif 34#endif
35#endif 35#endif
36 36
37#ifdef CONFIG_IRQ_CPU_RM9K
38#ifndef RM9K_CPU_IRQ_BASE
39#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
40#endif
41#endif
42
43#endif /* CONFIG_IRQ_CPU */ 37#endif /* CONFIG_IRQ_CPU */
44 38
45#endif /* __ASM_MACH_GENERIC_IRQ_H */ 39#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index a44fa9656a82..fba640517f4f 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -21,7 +21,6 @@
21#define MIPS4K_ICACHE_REFILL_WAR 0 21#define MIPS4K_ICACHE_REFILL_WAR 0
22#define MIPS_CACHE_SYNC_WAR 0 22#define MIPS_CACHE_SYNC_WAR 0
23#define TX49XX_ICACHE_INDEX_INV_WAR 0 23#define TX49XX_ICACHE_INDEX_INV_WAR 0
24#define RM9000_CDEX_SMP_WAR 0
25#define ICACHE_REFILLS_WORKAROUND_WAR 0 24#define ICACHE_REFILLS_WORKAROUND_WAR 0
26#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
27#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index e2ddcc9b1fff..4ee0e4bdf4fb 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 1 21#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index a1baafab486a..4821c7b7a38c 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 1 21#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index d194056dcd7a..7237a935a133 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
index 6158ee861bfd..5b18b9a3d0ec 100644
--- a/arch/mips/include/asm/mach-jazz/war.h
+++ b/arch/mips/include/asm/mach-jazz/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
index 3a5bc17e28fe..9b511d323838 100644
--- a/arch/mips/include/asm/mach-jz4740/war.h
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
index 01b08ef368d1..b6c568c280ef 100644
--- a/arch/mips/include/asm/mach-lantiq/war.h
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -16,7 +16,6 @@
16#define MIPS4K_ICACHE_REFILL_WAR 0 16#define MIPS4K_ICACHE_REFILL_WAR 0
17#define MIPS_CACHE_SYNC_WAR 0 17#define MIPS_CACHE_SYNC_WAR 0
18#define TX49XX_ICACHE_INDEX_INV_WAR 0 18#define TX49XX_ICACHE_INDEX_INV_WAR 0
19#define RM9000_CDEX_SMP_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0 19#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0 20#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0 21#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 6a2df709c576..133336b493b6 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -82,6 +82,9 @@ extern __iomem void *ltq_cgu_membase;
82#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) 82#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
83#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) 83#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
84 84
85/* allow booting xrx200 phys */
86int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
87
85/* request a non-gpio and set the PIO config */ 88/* request a non-gpio and set the PIO config */
86#define PMU_PPE BIT(13) 89#define PMU_PPE BIT(13)
87extern void ltq_pmu_enable(unsigned int module); 90extern void ltq_pmu_enable(unsigned int module);
diff --git a/arch/mips/include/asm/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
index bb1e0325c9be..741ae724adc6 100644
--- a/arch/mips/include/asm/mach-lasat/war.h
+++ b/arch/mips/include/asm/mach-lasat/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h
index 4b971c3ffd8d..f2570df66bb5 100644
--- a/arch/mips/include/asm/mach-loongson/war.h
+++ b/arch/mips/include/asm/mach-loongson/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
index 2f171617bade..718a1228a4f3 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -18,6 +18,7 @@ extern struct platform_device ls1x_eth0_device;
18extern struct platform_device ls1x_ehci_device; 18extern struct platform_device ls1x_ehci_device;
19extern struct platform_device ls1x_rtc_device; 19extern struct platform_device ls1x_rtc_device;
20 20
21void ls1x_serial_setup(void); 21extern void __init ls1x_clk_init(void);
22extern void __init ls1x_serial_setup(struct platform_device *pdev);
22 23
23#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */ 24#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index 8efa7fb9f73a..a81fa3d0dc91 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,14 +20,15 @@
20 20
21/* Clock PLL Divisor Register Bits */ 21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31) 22#define DIV_DC_EN (0x1 << 31)
23#define DIV_DC (0x1f << 26)
24#define DIV_CPU_EN (0x1 << 25) 23#define DIV_CPU_EN (0x1 << 25)
25#define DIV_CPU (0x1f << 20)
26#define DIV_DDR_EN (0x1 << 19) 24#define DIV_DDR_EN (0x1 << 19)
27#define DIV_DDR (0x1f << 14)
28 25
29#define DIV_DC_SHIFT 26 26#define DIV_DC_SHIFT 26
30#define DIV_CPU_SHIFT 20 27#define DIV_CPU_SHIFT 20
31#define DIV_DDR_SHIFT 14 28#define DIV_DDR_SHIFT 14
32 29
30#define DIV_DC_WIDTH 5
31#define DIV_CPU_WIDTH 5
32#define DIV_DDR_WIDTH 5
33
33#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ 34#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
index e3680a8fb349..8fb50d008131 100644
--- a/arch/mips/include/asm/mach-loongson1/war.h
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 7c6931d5f45f..d068fc411f47 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 1 17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1 18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
index b5902458e7c1..868ed8a2ed5c 100644
--- a/arch/mips/include/asm/mach-netlogic/irq.h
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -8,7 +8,9 @@
8#ifndef __ASM_NETLOGIC_IRQ_H 8#ifndef __ASM_NETLOGIC_IRQ_H
9#define __ASM_NETLOGIC_IRQ_H 9#define __ASM_NETLOGIC_IRQ_H
10 10
11#define NR_IRQS 64 11#include <asm/mach-netlogic/multi-node.h>
12#define NR_IRQS (64 * NLM_NR_NODES)
13
12#define MIPS_CPU_IRQ_BASE 0 14#define MIPS_CPU_IRQ_BASE 0
13 15
14#endif /* __ASM_NETLOGIC_IRQ_H */ 16#endif /* __ASM_NETLOGIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
new file mode 100644
index 000000000000..d62fc773f4d7
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NETLOGIC_MULTI_NODE_H_
36#define _NETLOGIC_MULTI_NODE_H_
37
38#ifndef CONFIG_NLM_MULTINODE
39#define NLM_NR_NODES 1
40#else
41#if defined(CONFIG_NLM_MULTINODE_2)
42#define NLM_NR_NODES 2
43#elif defined(CONFIG_NLM_MULTINODE_4)
44#define NLM_NR_NODES 4
45#else
46#define NLM_NR_NODES 1
47#endif
48#endif
49
50#define NLM_CORES_PER_NODE 8
51#define NLM_THREADS_PER_CORE 4
52#define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE)
53
54#endif
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
index 22da89327352..2c7216840e18 100644
--- a/arch/mips/include/asm/mach-netlogic/war.h
+++ b/arch/mips/include/asm/mach-netlogic/war.h
@@ -18,7 +18,6 @@
18#define MIPS4K_ICACHE_REFILL_WAR 0 18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0 19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0 20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0 21#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
index 82cd1e97bc2e..edaa06d9d492 100644
--- a/arch/mips/include/asm/mach-pnx833x/war.h
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
index d0458dd082f9..de8894c46686 100644
--- a/arch/mips/include/asm/mach-pnx8550/war.h
+++ b/arch/mips/include/asm/mach-pnx8550/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 7ac05ecc512b..c5651c8e58d1 100644
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -20,7 +20,6 @@
20#define MIPS4K_ICACHE_REFILL_WAR 1 20#define MIPS4K_ICACHE_REFILL_WAR 1
21#define MIPS_CACHE_SYNC_WAR 1 21#define MIPS_CACHE_SYNC_WAR 1
22#define TX49XX_ICACHE_INDEX_INV_WAR 0 22#define TX49XX_ICACHE_INDEX_INV_WAR 0
23#define RM9000_CDEX_SMP_WAR 0
24#define ICACHE_REFILLS_WORKAROUND_WAR 1 23#define ICACHE_REFILLS_WORKAROUND_WAR 1
25#define R10000_LLSC_WAR 0 24#define R10000_LLSC_WAR 0
26#define MIPS34K_MISSED_ITLB_WAR 0 25#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 3ddf187e98a6..1bfd489a3708 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 1 17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 948d3129a114..a3dde98549bb 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -21,7 +21,6 @@
21#define MIPS4K_ICACHE_REFILL_WAR 0 21#define MIPS4K_ICACHE_REFILL_WAR 0
22#define MIPS_CACHE_SYNC_WAR 0 22#define MIPS_CACHE_SYNC_WAR 0
23#define TX49XX_ICACHE_INDEX_INV_WAR 0 23#define TX49XX_ICACHE_INDEX_INV_WAR 0
24#define RM9000_CDEX_SMP_WAR 0
25#define ICACHE_REFILLS_WORKAROUND_WAR 0 24#define ICACHE_REFILLS_WORKAROUND_WAR 0
26#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
27#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
index 7c6931d5f45f..d068fc411f47 100644
--- a/arch/mips/include/asm/mach-sead3/war.h
+++ b/arch/mips/include/asm/mach-sead3/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 1 17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1 18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 743385d7b5f2..176f5b32dc69 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -33,7 +33,6 @@ extern int sb1250_m3_workaround_needed(void);
33#define MIPS4K_ICACHE_REFILL_WAR 0 33#define MIPS4K_ICACHE_REFILL_WAR 0
34#define MIPS_CACHE_SYNC_WAR 0 34#define MIPS_CACHE_SYNC_WAR 0
35#define TX49XX_ICACHE_INDEX_INV_WAR 0 35#define TX49XX_ICACHE_INDEX_INV_WAR 0
36#define RM9000_CDEX_SMP_WAR 0
37#define ICACHE_REFILLS_WORKAROUND_WAR 0 36#define ICACHE_REFILLS_WORKAROUND_WAR 0
38#define R10000_LLSC_WAR 0 37#define R10000_LLSC_WAR 0
39#define MIPS34K_MISSED_ITLB_WAR 0 38#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
index 433814616359..6a52e6534776 100644
--- a/arch/mips/include/asm/mach-tx39xx/war.h
+++ b/arch/mips/include/asm/mach-tx39xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 39b5d1177c57..a8e2c586a18c 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 1 19#define TX49XX_ICACHE_INDEX_INV_WAR 1
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
index 56a38926412a..ffe31e736009 100644
--- a/arch/mips/include/asm/mach-vr41xx/war.h
+++ b/arch/mips/include/asm/mach-vr41xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
index ac48629bb1ce..e86084c0bd6b 100644
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ b/arch/mips/include/asm/mach-wrppmc/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
deleted file mode 100644
index 56bdd3298600..000000000000
--- a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * Momentum Jaguar ATX always has the RM9000 processor.
13 */
14#define cpu_has_watch 1
15#define cpu_has_mips16 0
16#define cpu_has_divec 0
17#define cpu_has_vce 0
18#define cpu_has_cache_cdex_p 0
19#define cpu_has_cache_cdex_s 0
20#define cpu_has_prefetch 1
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23
24#define cpu_has_llsc 1
25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
29#define cpu_has_dsp2 0
30#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0
32#define cpu_icache_snoops_remote_store 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_inclusive_pcaches 0
38
39#define cpu_dcache_line_size() 32
40#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 32
42
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47
48#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
deleted file mode 100644
index e5c6d53efc86..000000000000
--- a/arch/mips/include/asm/mach-yosemite/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
9#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index eb742895dcbe..7e4e6f8fab37 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -240,7 +240,7 @@
240#define PM_HUGE_MASK PM_64M 240#define PM_HUGE_MASK PM_64M
241#elif defined(CONFIG_PAGE_SIZE_64KB) 241#elif defined(CONFIG_PAGE_SIZE_64KB)
242#define PM_HUGE_MASK PM_256M 242#define PM_HUGE_MASK PM_256M
243#elif defined(CONFIG_HUGETLB_PAGE) 243#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
244#error Bad page size configuration for hugetlbfs! 244#error Bad page size configuration for hugetlbfs!
245#endif 245#endif
246 246
@@ -977,10 +977,6 @@ do { \
977#define read_c0_framemask() __read_32bit_c0_register($21, 0) 977#define read_c0_framemask() __read_32bit_c0_register($21, 0)
978#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 978#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
979 979
980/* RM9000 PerfControl performance counter control register */
981#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
982#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
983
984#define read_c0_diag() __read_32bit_c0_register($22, 0) 980#define read_c0_diag() __read_32bit_c0_register($22, 0)
985#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 981#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
986 982
@@ -1033,10 +1029,6 @@ do { \
1033#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1029#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1034#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1030#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1035 1031
1036/* RM9000 PerfCount performance counter register */
1037#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
1038#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
1039
1040#define read_c0_ecc() __read_32bit_c0_register($26, 0) 1032#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1041#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1033#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1042 1034
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 9b02cfba7449..45cfa1ad86a6 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -72,12 +72,6 @@ extern unsigned long pgd_current[];
72#define ASID_INC 0x10 72#define ASID_INC 0x10
73#define ASID_MASK 0xff0 73#define ASID_MASK 0xff0
74 74
75#elif defined(CONFIG_CPU_RM9000)
76
77#define ASID_INC 0x1
78#define ASID_MASK 0xfff
79
80/* SMTC/34K debug hack - but maybe we'll keep it */
81#elif defined(CONFIG_MIPS_MT_SMTC) 75#elif defined(CONFIG_MIPS_MT_SMTC)
82 76
83#define ASID_INC 0x1 77#define ASID_INC 0x1
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 26137da1c713..44b705d08262 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -120,8 +120,6 @@ search_module_dbetables(unsigned long addr)
120#define MODULE_PROC_FAMILY "R10000 " 120#define MODULE_PROC_FAMILY "R10000 "
121#elif defined CONFIG_CPU_RM7000 121#elif defined CONFIG_CPU_RM7000
122#define MODULE_PROC_FAMILY "RM7000 " 122#define MODULE_PROC_FAMILY "RM7000 "
123#elif defined CONFIG_CPU_RM9000
124#define MODULE_PROC_FAMILY "RM9000 "
125#elif defined CONFIG_CPU_SB1 123#elif defined CONFIG_CPU_SB1
126#define MODULE_PROC_FAMILY "SB1 " 124#define MODULE_PROC_FAMILY "SB1 "
127#elif defined CONFIG_CPU_LOONGSON1 125#elif defined CONFIG_CPU_LOONGSON1
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index fdd2f44c7b59..42bfd5f1eeec 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -45,15 +45,19 @@
45#define BOOT_NMI_HANDLER 8 45#define BOOT_NMI_HANDLER 8
46 46
47#ifndef __ASSEMBLY__ 47#ifndef __ASSEMBLY__
48#include <linux/cpumask.h>
49#include <linux/spinlock.h>
50#include <asm/irq.h>
51#include <asm/mach-netlogic/multi-node.h>
52
48struct irq_desc; 53struct irq_desc;
49extern struct plat_smp_ops nlm_smp_ops;
50extern char nlm_reset_entry[], nlm_reset_entry_end[];
51void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); 54void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
52void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); 55void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
53void nlm_smp_irq_init(void); 56void nlm_smp_irq_init(int hwcpuid);
54void nlm_boot_secondary_cpus(void); 57void nlm_boot_secondary_cpus(void);
55int nlm_wakeup_secondary_cpus(u32 wakeup_mask); 58int nlm_wakeup_secondary_cpus(void);
56void nlm_rmiboot_preboot(void); 59void nlm_rmiboot_preboot(void);
60void nlm_percpu_init(int hwcpuid);
57 61
58static inline void 62static inline void
59nlm_set_nmi_handler(void *handler) 63nlm_set_nmi_handler(void *handler)
@@ -68,9 +72,42 @@ nlm_set_nmi_handler(void *handler)
68 * Misc. 72 * Misc.
69 */ 73 */
70unsigned int nlm_get_cpu_frequency(void); 74unsigned int nlm_get_cpu_frequency(void);
75void nlm_node_init(int node);
76extern struct plat_smp_ops nlm_smp_ops;
77extern char nlm_reset_entry[], nlm_reset_entry_end[];
78
79extern unsigned int nlm_threads_per_core;
80extern cpumask_t nlm_cpumask;
81
82struct nlm_soc_info {
83 unsigned long coremask; /* cores enabled on the soc */
84 unsigned long ebase;
85 uint64_t irqmask;
86 uint64_t sysbase; /* only for XLP */
87 uint64_t picbase;
88 spinlock_t piclock;
89};
90
91#define nlm_get_node(i) (&nlm_nodes[i])
92#ifdef CONFIG_CPU_XLR
93#define nlm_current_node() (&nlm_nodes[0])
94#else
95#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
96#endif
97
98struct irq_data;
99uint64_t nlm_pci_irqmask(int node);
100void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
101
102/*
103 * The NR_IRQs is divided between nodes, each of them has a separate irq space
104 */
105static inline int nlm_irq_to_xirq(int node, int irq)
106{
107 return node * NR_IRQS / NLM_NR_NODES + irq;
108}
71 109
72extern unsigned long nlm_common_ebase; 110extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
73extern int nlm_threads_per_core; 111extern int nlm_cpu_ready[];
74extern uint32_t nlm_cpumask, nlm_coremask;
75#endif 112#endif
76#endif /* _NETLOGIC_COMMON_H_ */ 113#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
index a85aadb6cfd7..ed5993d9b7b8 100644
--- a/arch/mips/include/asm/netlogic/interrupt.h
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -39,7 +39,7 @@
39 39
40#define IRQ_IPI_SMP_FUNCTION 3 40#define IRQ_IPI_SMP_FUNCTION 3
41#define IRQ_IPI_SMP_RESCHEDULE 4 41#define IRQ_IPI_SMP_RESCHEDULE 4
42#define IRQ_MSGRING 6 42#define IRQ_FMN 5
43#define IRQ_TIMER 7 43#define IRQ_TIMER 7
44 44
45#endif 45#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 8c53d0ba4bf2..32ba6d95d47c 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -73,4 +73,146 @@ static inline int hard_smp_processor_id(void)
73 return __read_32bit_c0_register($15, 1) & 0x3ff; 73 return __read_32bit_c0_register($15, 1) & 0x3ff;
74} 74}
75 75
76static inline int nlm_nodeid(void)
77{
78 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
79}
80
81static inline unsigned int nlm_core_id(void)
82{
83 return (read_c0_ebase() & 0x1c) >> 2;
84}
85
86static inline unsigned int nlm_thread_id(void)
87{
88 return read_c0_ebase() & 0x3;
89}
90
91#define __read_64bit_c2_split(source, sel) \
92({ \
93 unsigned long long __val; \
94 unsigned long __flags; \
95 \
96 local_irq_save(__flags); \
97 if (sel == 0) \
98 __asm__ __volatile__( \
99 ".set\tmips64\n\t" \
100 "dmfc2\t%M0, " #source "\n\t" \
101 "dsll\t%L0, %M0, 32\n\t" \
102 "dsra\t%M0, %M0, 32\n\t" \
103 "dsra\t%L0, %L0, 32\n\t" \
104 ".set\tmips0\n\t" \
105 : "=r" (__val)); \
106 else \
107 __asm__ __volatile__( \
108 ".set\tmips64\n\t" \
109 "dmfc2\t%M0, " #source ", " #sel "\n\t" \
110 "dsll\t%L0, %M0, 32\n\t" \
111 "dsra\t%M0, %M0, 32\n\t" \
112 "dsra\t%L0, %L0, 32\n\t" \
113 ".set\tmips0\n\t" \
114 : "=r" (__val)); \
115 local_irq_restore(__flags); \
116 \
117 __val; \
118})
119
120#define __write_64bit_c2_split(source, sel, val) \
121do { \
122 unsigned long __flags; \
123 \
124 local_irq_save(__flags); \
125 if (sel == 0) \
126 __asm__ __volatile__( \
127 ".set\tmips64\n\t" \
128 "dsll\t%L0, %L0, 32\n\t" \
129 "dsrl\t%L0, %L0, 32\n\t" \
130 "dsll\t%M0, %M0, 32\n\t" \
131 "or\t%L0, %L0, %M0\n\t" \
132 "dmtc2\t%L0, " #source "\n\t" \
133 ".set\tmips0\n\t" \
134 : : "r" (val)); \
135 else \
136 __asm__ __volatile__( \
137 ".set\tmips64\n\t" \
138 "dsll\t%L0, %L0, 32\n\t" \
139 "dsrl\t%L0, %L0, 32\n\t" \
140 "dsll\t%M0, %M0, 32\n\t" \
141 "or\t%L0, %L0, %M0\n\t" \
142 "dmtc2\t%L0, " #source ", " #sel "\n\t" \
143 ".set\tmips0\n\t" \
144 : : "r" (val)); \
145 local_irq_restore(__flags); \
146} while (0)
147
148#define __read_32bit_c2_register(source, sel) \
149({ uint32_t __res; \
150 if (sel == 0) \
151 __asm__ __volatile__( \
152 ".set\tmips32\n\t" \
153 "mfc2\t%0, " #source "\n\t" \
154 ".set\tmips0\n\t" \
155 : "=r" (__res)); \
156 else \
157 __asm__ __volatile__( \
158 ".set\tmips32\n\t" \
159 "mfc2\t%0, " #source ", " #sel "\n\t" \
160 ".set\tmips0\n\t" \
161 : "=r" (__res)); \
162 __res; \
163})
164
165#define __read_64bit_c2_register(source, sel) \
166({ unsigned long long __res; \
167 if (sizeof(unsigned long) == 4) \
168 __res = __read_64bit_c2_split(source, sel); \
169 else if (sel == 0) \
170 __asm__ __volatile__( \
171 ".set\tmips64\n\t" \
172 "dmfc2\t%0, " #source "\n\t" \
173 ".set\tmips0\n\t" \
174 : "=r" (__res)); \
175 else \
176 __asm__ __volatile__( \
177 ".set\tmips64\n\t" \
178 "dmfc2\t%0, " #source ", " #sel "\n\t" \
179 ".set\tmips0\n\t" \
180 : "=r" (__res)); \
181 __res; \
182})
183
184#define __write_64bit_c2_register(register, sel, value) \
185do { \
186 if (sizeof(unsigned long) == 4) \
187 __write_64bit_c2_split(register, sel, value); \
188 else if (sel == 0) \
189 __asm__ __volatile__( \
190 ".set\tmips64\n\t" \
191 "dmtc2\t%z0, " #register "\n\t" \
192 ".set\tmips0\n\t" \
193 : : "Jr" (value)); \
194 else \
195 __asm__ __volatile__( \
196 ".set\tmips64\n\t" \
197 "dmtc2\t%z0, " #register ", " #sel "\n\t" \
198 ".set\tmips0\n\t" \
199 : : "Jr" (value)); \
200} while (0)
201
202#define __write_32bit_c2_register(reg, sel, value) \
203({ \
204 if (sel == 0) \
205 __asm__ __volatile__( \
206 ".set\tmips32\n\t" \
207 "mtc2\t%z0, " #reg "\n\t" \
208 ".set\tmips0\n\t" \
209 : : "Jr" (value)); \
210 else \
211 __asm__ __volatile__( \
212 ".set\tmips32\n\t" \
213 "mtc2\t%z0, " #reg ", " #sel "\n\t" \
214 ".set\tmips0\n\t" \
215 : : "Jr" (value)); \
216})
217
76#endif /*_ASM_NLM_MIPS_EXTS_H */ 218#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index ad8b80233a63..b2e53a5383ab 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -273,36 +273,16 @@ nlm_pic_read_irt(uint64_t base, int irt_index)
273 return nlm_read_pic_reg(base, PIC_IRT(irt_index)); 273 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
274} 274}
275 275
276static inline uint64_t
277nlm_pic_read_control(uint64_t base)
278{
279 return nlm_read_pic_reg(base, PIC_CTRL);
280}
281
282static inline void
283nlm_pic_write_control(uint64_t base, uint64_t control)
284{
285 nlm_write_pic_reg(base, PIC_CTRL, control);
286}
287
288static inline void
289nlm_pic_update_control(uint64_t base, uint64_t control)
290{
291 uint64_t val;
292
293 val = nlm_read_pic_reg(base, PIC_CTRL);
294 nlm_write_pic_reg(base, PIC_CTRL, control | val);
295}
296
297static inline void 276static inline void
298nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 277nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
299{ 278{
300 uint64_t val; 279 uint64_t val;
301 280
302 val = nlm_read_pic_reg(base, PIC_IRT(irt)); 281 val = nlm_read_pic_reg(base, PIC_IRT(irt));
303 val |= cpu & 0xf; 282 /* clear cpuset and mask */
304 if (cpu > 15) 283 val &= ~((0x7ull << 16) | 0xffff);
305 val |= 1 << 16; 284 /* set DB, cpuset and cpumask */
285 val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
306 nlm_write_pic_reg(base, PIC_IRT(irt), val); 286 nlm_write_pic_reg(base, PIC_IRT(irt), val);
307} 287}
308 288
@@ -369,7 +349,7 @@ nlm_pic_enable_irt(uint64_t base, int irt)
369static inline void 349static inline void
370nlm_pic_disable_irt(uint64_t base, int irt) 350nlm_pic_disable_irt(uint64_t base, int irt)
371{ 351{
372 uint32_t reg; 352 uint64_t reg;
373 353
374 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 354 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
375 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); 355 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
@@ -379,15 +359,9 @@ static inline void
379nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) 359nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
380{ 360{
381 uint64_t ipi; 361 uint64_t ipi;
382 int node, ncpu;
383
384 node = hwt / 32;
385 ncpu = hwt & 0x1f;
386 ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
387 (1 << (ncpu & 0xf));
388 if (ncpu > 15)
389 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
390 362
363 ipi = (nmi << 31) | (irq << 20);
364 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
391 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 365 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
392} 366}
393 367
@@ -404,12 +378,10 @@ nlm_pic_ack(uint64_t base, int irt_num)
404static inline void 378static inline void
405nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) 379nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
406{ 380{
407 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0); 381 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt);
408} 382}
409 383
410extern uint64_t nlm_pic_base;
411int nlm_irq_to_irt(int irq); 384int nlm_irq_to_irt(int irq);
412int nlm_irt_to_irq(int irt);
413 385
414#endif /* __ASSEMBLY__ */ 386#endif /* __ASSEMBLY__ */
415#endif /* _NLM_HAL_PIC_H */ 387#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index 21432f7d89b9..258e8cc00e99 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -124,6 +124,5 @@
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126 126
127extern uint64_t nlm_sys_base;
128#endif 127#endif
129#endif 128#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
new file mode 100644
index 000000000000..68d5167c86bb
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -0,0 +1,363 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_FMN_H_
36#define _NLM_FMN_H_
37
38#include <asm/netlogic/mips-extns.h> /* for COP2 access */
39
40/* Station IDs */
41#define FMN_STNID_CPU0 0x00
42#define FMN_STNID_CPU1 0x08
43#define FMN_STNID_CPU2 0x10
44#define FMN_STNID_CPU3 0x18
45#define FMN_STNID_CPU4 0x20
46#define FMN_STNID_CPU5 0x28
47#define FMN_STNID_CPU6 0x30
48#define FMN_STNID_CPU7 0x38
49
50#define FMN_STNID_XGS0_TX 64
51#define FMN_STNID_XMAC0_00_TX 64
52#define FMN_STNID_XMAC0_01_TX 65
53#define FMN_STNID_XMAC0_02_TX 66
54#define FMN_STNID_XMAC0_03_TX 67
55#define FMN_STNID_XMAC0_04_TX 68
56#define FMN_STNID_XMAC0_05_TX 69
57#define FMN_STNID_XMAC0_06_TX 70
58#define FMN_STNID_XMAC0_07_TX 71
59#define FMN_STNID_XMAC0_08_TX 72
60#define FMN_STNID_XMAC0_09_TX 73
61#define FMN_STNID_XMAC0_10_TX 74
62#define FMN_STNID_XMAC0_11_TX 75
63#define FMN_STNID_XMAC0_12_TX 76
64#define FMN_STNID_XMAC0_13_TX 77
65#define FMN_STNID_XMAC0_14_TX 78
66#define FMN_STNID_XMAC0_15_TX 79
67
68#define FMN_STNID_XGS1_TX 80
69#define FMN_STNID_XMAC1_00_TX 80
70#define FMN_STNID_XMAC1_01_TX 81
71#define FMN_STNID_XMAC1_02_TX 82
72#define FMN_STNID_XMAC1_03_TX 83
73#define FMN_STNID_XMAC1_04_TX 84
74#define FMN_STNID_XMAC1_05_TX 85
75#define FMN_STNID_XMAC1_06_TX 86
76#define FMN_STNID_XMAC1_07_TX 87
77#define FMN_STNID_XMAC1_08_TX 88
78#define FMN_STNID_XMAC1_09_TX 89
79#define FMN_STNID_XMAC1_10_TX 90
80#define FMN_STNID_XMAC1_11_TX 91
81#define FMN_STNID_XMAC1_12_TX 92
82#define FMN_STNID_XMAC1_13_TX 93
83#define FMN_STNID_XMAC1_14_TX 94
84#define FMN_STNID_XMAC1_15_TX 95
85
86#define FMN_STNID_GMAC 96
87#define FMN_STNID_GMACJFR_0 96
88#define FMN_STNID_GMACRFR_0 97
89#define FMN_STNID_GMACTX0 98
90#define FMN_STNID_GMACTX1 99
91#define FMN_STNID_GMACTX2 100
92#define FMN_STNID_GMACTX3 101
93#define FMN_STNID_GMACJFR_1 102
94#define FMN_STNID_GMACRFR_1 103
95
96#define FMN_STNID_DMA 104
97#define FMN_STNID_DMA_0 104
98#define FMN_STNID_DMA_1 105
99#define FMN_STNID_DMA_2 106
100#define FMN_STNID_DMA_3 107
101
102#define FMN_STNID_XGS0FR 112
103#define FMN_STNID_XMAC0JFR 112
104#define FMN_STNID_XMAC0RFR 113
105
106#define FMN_STNID_XGS1FR 114
107#define FMN_STNID_XMAC1JFR 114
108#define FMN_STNID_XMAC1RFR 115
109#define FMN_STNID_SEC 120
110#define FMN_STNID_SEC0 120
111#define FMN_STNID_SEC1 121
112#define FMN_STNID_SEC2 122
113#define FMN_STNID_SEC3 123
114#define FMN_STNID_PK0 124
115#define FMN_STNID_SEC_RSA 124
116#define FMN_STNID_SEC_RSVD0 125
117#define FMN_STNID_SEC_RSVD1 126
118#define FMN_STNID_SEC_RSVD2 127
119
120#define FMN_STNID_GMAC1 80
121#define FMN_STNID_GMAC1_FR_0 81
122#define FMN_STNID_GMAC1_TX0 82
123#define FMN_STNID_GMAC1_TX1 83
124#define FMN_STNID_GMAC1_TX2 84
125#define FMN_STNID_GMAC1_TX3 85
126#define FMN_STNID_GMAC1_FR_1 87
127#define FMN_STNID_GMAC0 96
128#define FMN_STNID_GMAC0_FR_0 97
129#define FMN_STNID_GMAC0_TX0 98
130#define FMN_STNID_GMAC0_TX1 99
131#define FMN_STNID_GMAC0_TX2 100
132#define FMN_STNID_GMAC0_TX3 101
133#define FMN_STNID_GMAC0_FR_1 103
134#define FMN_STNID_CMP_0 108
135#define FMN_STNID_CMP_1 109
136#define FMN_STNID_CMP_2 110
137#define FMN_STNID_CMP_3 111
138#define FMN_STNID_PCIE_0 116
139#define FMN_STNID_PCIE_1 117
140#define FMN_STNID_PCIE_2 118
141#define FMN_STNID_PCIE_3 119
142#define FMN_STNID_XLS_PK0 121
143
144#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s)
145#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s)
146#define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s)
147#define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s)
148#define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s)
149#define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s)
150#define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s)
151#define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s)
152#define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s)
153#define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s)
154#define nlm_read_c2_cc10(s) __read_32bit_c2_register($26, s)
155#define nlm_read_c2_cc11(s) __read_32bit_c2_register($27, s)
156#define nlm_read_c2_cc12(s) __read_32bit_c2_register($28, s)
157#define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s)
158#define nlm_read_c2_cc14(s) __read_32bit_c2_register($30, s)
159#define nlm_read_c2_cc15(s) __read_32bit_c2_register($31, s)
160
161#define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v)
162#define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v)
163#define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v)
164#define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v)
165#define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v)
166#define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v)
167#define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v)
168#define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v)
169#define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v)
170#define nlm_write_c2_cc9(s, v) __write_32bit_c2_register($25, s, v)
171#define nlm_write_c2_cc10(s, v) __write_32bit_c2_register($26, s, v)
172#define nlm_write_c2_cc11(s, v) __write_32bit_c2_register($27, s, v)
173#define nlm_write_c2_cc12(s, v) __write_32bit_c2_register($28, s, v)
174#define nlm_write_c2_cc13(s, v) __write_32bit_c2_register($29, s, v)
175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
177
178#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
179#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
180#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
181#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b)
182#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v)
183
184#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0)
185#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1)
186#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2)
187#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3)
188
189#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v)
190#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v)
191#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v)
192#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v)
193
194#define FMN_STN_RX_QSIZE 256
195#define FMN_NSTATIONS 128
196#define FMN_CORE_NBUCKETS 8
197
198static inline void nlm_msgsnd(unsigned int stid)
199{
200 __asm__ volatile (
201 ".set push\n"
202 ".set noreorder\n"
203 ".set noat\n"
204 "move $1, %0\n"
205 "c2 0x10001\n" /* msgsnd $1 */
206 ".set pop\n"
207 : : "r" (stid) : "$1"
208 );
209}
210
211static inline void nlm_msgld(unsigned int pri)
212{
213 __asm__ volatile (
214 ".set push\n"
215 ".set noreorder\n"
216 ".set noat\n"
217 "move $1, %0\n"
218 "c2 0x10002\n" /* msgld $1 */
219 ".set pop\n"
220 : : "r" (pri) : "$1"
221 );
222}
223
224static inline void nlm_msgwait(unsigned int mask)
225{
226 __asm__ volatile (
227 ".set push\n"
228 ".set noreorder\n"
229 ".set noat\n"
230 "move $8, %0\n"
231 "c2 0x10003\n" /* msgwait $1 */
232 ".set pop\n"
233 : : "r" (mask) : "$1"
234 );
235}
236
237/*
238 * Disable interrupts and enable COP2 access
239 */
240static inline uint32_t nlm_cop2_enable(void)
241{
242 uint32_t sr = read_c0_status();
243
244 write_c0_status((sr & ~ST0_IE) | ST0_CU2);
245 return sr;
246}
247
248static inline void nlm_cop2_restore(uint32_t sr)
249{
250 write_c0_status(sr);
251}
252
253static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask)
254{
255 uint32_t config;
256
257 config = (1 << 24) /* interrupt water mark - 1 msg */
258 | (irq << 16) /* irq */
259 | (tmask << 8) /* thread mask */
260 | 0x2; /* enable watermark intr, disable empty intr */
261 nlm_write_c2_config(config);
262}
263
264struct nlm_fmn_msg {
265 uint64_t msg0;
266 uint64_t msg1;
267 uint64_t msg2;
268 uint64_t msg3;
269};
270
271static inline int nlm_fmn_send(unsigned int size, unsigned int code,
272 unsigned int stid, struct nlm_fmn_msg *msg)
273{
274 unsigned int dest;
275 uint32_t status;
276 int i;
277
278 /*
279 * Make sure that all the writes pending at the cpu are flushed.
280 * Any writes pending on CPU will not be see by devices. L1/L2
281 * caches are coherent with IO, so no cache flush needed.
282 */
283 __asm __volatile("sync");
284
285 /* Load TX message buffers */
286 nlm_write_c2_tx_msg0(msg->msg0);
287 nlm_write_c2_tx_msg1(msg->msg1);
288 nlm_write_c2_tx_msg2(msg->msg2);
289 nlm_write_c2_tx_msg3(msg->msg3);
290 dest = ((size - 1) << 16) | (code << 8) | stid;
291
292 /*
293 * Retry a few times on credit fail, this should be a
294 * transient condition, unless there is a configuration
295 * failure, or the receiver is stuck.
296 */
297 for (i = 0; i < 8; i++) {
298 nlm_msgsnd(dest);
299 status = nlm_read_c2_status(0);
300 if ((status & 0x2) == 1)
301 pr_info("Send pending fail!\n");
302 if ((status & 0x4) == 0)
303 return 0;
304 }
305
306 /* If there is a credit failure, return error */
307 return status & 0x06;
308}
309
310static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
311 struct nlm_fmn_msg *msg)
312{
313 uint32_t status, tmp;
314
315 nlm_msgld(bucket);
316
317 /* wait for load pending to clear */
318 do {
319 status = nlm_read_c2_status(1);
320 } while ((status & 0x08) != 0);
321
322 /* receive error bits */
323 tmp = status & 0x30;
324 if (tmp != 0)
325 return tmp;
326
327 *size = ((status & 0xc0) >> 6) + 1;
328 *code = (status & 0xff00) >> 8;
329 *stid = (status & 0x7f0000) >> 16;
330 msg->msg0 = nlm_read_c2_rx_msg0();
331 msg->msg1 = nlm_read_c2_rx_msg1();
332 msg->msg2 = nlm_read_c2_rx_msg2();
333 msg->msg3 = nlm_read_c2_rx_msg3();
334
335 return 0;
336}
337
338struct xlr_fmn_info {
339 int num_buckets;
340 int start_stn_id;
341 int end_stn_id;
342 int credit_config[128];
343};
344
345struct xlr_board_fmn_config {
346 int bucket_size[128]; /* size of buckets for all stations */
347 struct xlr_fmn_info cpu[8];
348 struct xlr_fmn_info gmac[2];
349 struct xlr_fmn_info dma;
350 struct xlr_fmn_info cmp;
351 struct xlr_fmn_info sae;
352 struct xlr_fmn_info xgmac[2];
353};
354
355extern int nlm_register_fmn_handler(int start, int end,
356 void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *),
357 void *arg);
358extern void xlr_percpu_fmn_init(void);
359extern void nlm_setup_fmn_irq(void);
360extern void xlr_board_info_setup(void);
361
362extern struct xlr_board_fmn_config xlr_board_fmn_config;
363#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 868013e62f32..9a691b1f91ba 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -258,7 +258,5 @@ nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
258 nlm_write_reg(base, PIC_IRT_1(irt), 258 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq); 259 (1 << 30) | (1 << 6) | irq);
260} 260}
261
262extern uint64_t nlm_pic_base;
263#endif 261#endif
264#endif /* _ASM_NLM_XLR_PIC_H */ 262#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index ff4a17b0bf78..c1667e0c272a 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -51,10 +51,8 @@ static inline unsigned int nlm_chip_is_xls_b(void)
51 return ((prid & 0xf000) == 0x4000); 51 return ((prid & 0xf000) == 0x4000);
52} 52}
53 53
54/* 54/* XLR chip types */
55 * XLR chip types 55/* The XLS product line has chip versions 0x[48c]? */
56 */
57 /* The XLS product line has chip versions 0x[48c]? */
58static inline unsigned int nlm_chip_is_xls(void) 56static inline unsigned int nlm_chip_is_xls(void)
59{ 57{
60 uint32_t prid = read_c0_prid(); 58 uint32_t prid = read_c0_prid();
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 877845b84b14..42db2be663f1 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -370,4 +370,6 @@ void cvmx_bootmem_lock(void);
370 */ 370 */
371void cvmx_bootmem_unlock(void); 371void cvmx_bootmem_unlock(void);
372 372
373extern struct cvmx_bootmem_desc *cvmx_bootmem_get_desc(void);
374
373#endif /* __CVMX_BOOTMEM_H__ */ 375#endif /* __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
new file mode 100644
index 000000000000..36f510721141
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
@@ -0,0 +1,3457 @@
1/***********************license start***************
2 * Author: Cavium Inc.
3 *
4 * Contact: support@cavium.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Inc. for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_LMCX_DEFS_H__
29#define __CVMX_LMCX_DEFS_H__
30
31#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
32#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
33#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
34#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
35#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull)
36#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull)
37#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull)
38#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull)
39#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull)
40#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull)
41#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull)
42#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull)
43#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull)
44#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull)
45#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull)
46#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull)
47#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull)
48#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull)
49#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull)
50#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull)
51#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull)
52#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
53#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull)
54#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull)
55#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull)
56#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull)
57static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
58{
59 switch (cvmx_get_octeon_family()) {
60 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
61 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
62 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
63 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
66 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
67 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
68 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
69 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
70 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
71 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull;
72 }
73 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
74}
75
76static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
77{
78 switch (cvmx_get_octeon_family()) {
79 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
80 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
81 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
82 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
83 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
84 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
85 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
86 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
87 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
88 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
89 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
90 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
91 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
92 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
93 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull;
94 }
95 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
96}
97
98static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
99{
100 switch (cvmx_get_octeon_family()) {
101 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
102 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
103 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
104 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
105 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
106 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
107 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
108 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
109 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
110 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
111 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
112 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
113 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
114 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
115 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull;
116 }
117 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
118}
119
120#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull)
121#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull)
122#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull)
123#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull)
124#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull)
125#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull)
126#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull)
127#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull)
128#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull)
129static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
130{
131 switch (cvmx_get_octeon_family()) {
132 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
133 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
134 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
135 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
136 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
137 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
138 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
139 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
140 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
141 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
142 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull;
143 }
144 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
145}
146
147#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull)
148#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull)
149#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull)
150#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull)
151#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull))
152#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull)
153#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull)
154#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull)
155#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull)
156#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8)
157#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull)
158#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull)
159#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull)
160#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
161#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull)
162#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull)
163#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull)
164#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull))
165#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull))
166#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull))
167#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull)
168#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull)
169#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull)
170#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull)
171#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull)
172#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull)
173#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull)
174#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull)
175#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull)
176#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
177#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull)
178#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull)
179#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull)
180
181union cvmx_lmcx_bist_ctl {
182 uint64_t u64;
183 struct cvmx_lmcx_bist_ctl_s {
184#ifdef __BIG_ENDIAN_BITFIELD
185 uint64_t reserved_1_63:63;
186 uint64_t start:1;
187#else
188 uint64_t start:1;
189 uint64_t reserved_1_63:63;
190#endif
191 } s;
192 struct cvmx_lmcx_bist_ctl_s cn50xx;
193 struct cvmx_lmcx_bist_ctl_s cn52xx;
194 struct cvmx_lmcx_bist_ctl_s cn52xxp1;
195 struct cvmx_lmcx_bist_ctl_s cn56xx;
196 struct cvmx_lmcx_bist_ctl_s cn56xxp1;
197};
198
199union cvmx_lmcx_bist_result {
200 uint64_t u64;
201 struct cvmx_lmcx_bist_result_s {
202#ifdef __BIG_ENDIAN_BITFIELD
203 uint64_t reserved_11_63:53;
204 uint64_t csrd2e:1;
205 uint64_t csre2d:1;
206 uint64_t mwf:1;
207 uint64_t mwd:3;
208 uint64_t mwc:1;
209 uint64_t mrf:1;
210 uint64_t mrd:3;
211#else
212 uint64_t mrd:3;
213 uint64_t mrf:1;
214 uint64_t mwc:1;
215 uint64_t mwd:3;
216 uint64_t mwf:1;
217 uint64_t csre2d:1;
218 uint64_t csrd2e:1;
219 uint64_t reserved_11_63:53;
220#endif
221 } s;
222 struct cvmx_lmcx_bist_result_cn50xx {
223#ifdef __BIG_ENDIAN_BITFIELD
224 uint64_t reserved_9_63:55;
225 uint64_t mwf:1;
226 uint64_t mwd:3;
227 uint64_t mwc:1;
228 uint64_t mrf:1;
229 uint64_t mrd:3;
230#else
231 uint64_t mrd:3;
232 uint64_t mrf:1;
233 uint64_t mwc:1;
234 uint64_t mwd:3;
235 uint64_t mwf:1;
236 uint64_t reserved_9_63:55;
237#endif
238 } cn50xx;
239 struct cvmx_lmcx_bist_result_s cn52xx;
240 struct cvmx_lmcx_bist_result_s cn52xxp1;
241 struct cvmx_lmcx_bist_result_s cn56xx;
242 struct cvmx_lmcx_bist_result_s cn56xxp1;
243};
244
245union cvmx_lmcx_char_ctl {
246 uint64_t u64;
247 struct cvmx_lmcx_char_ctl_s {
248#ifdef __BIG_ENDIAN_BITFIELD
249 uint64_t reserved_44_63:20;
250 uint64_t dr:1;
251 uint64_t skew_on:1;
252 uint64_t en:1;
253 uint64_t sel:1;
254 uint64_t prog:8;
255 uint64_t prbs:32;
256#else
257 uint64_t prbs:32;
258 uint64_t prog:8;
259 uint64_t sel:1;
260 uint64_t en:1;
261 uint64_t skew_on:1;
262 uint64_t dr:1;
263 uint64_t reserved_44_63:20;
264#endif
265 } s;
266 struct cvmx_lmcx_char_ctl_s cn61xx;
267 struct cvmx_lmcx_char_ctl_cn63xx {
268#ifdef __BIG_ENDIAN_BITFIELD
269 uint64_t reserved_42_63:22;
270 uint64_t en:1;
271 uint64_t sel:1;
272 uint64_t prog:8;
273 uint64_t prbs:32;
274#else
275 uint64_t prbs:32;
276 uint64_t prog:8;
277 uint64_t sel:1;
278 uint64_t en:1;
279 uint64_t reserved_42_63:22;
280#endif
281 } cn63xx;
282 struct cvmx_lmcx_char_ctl_cn63xx cn63xxp1;
283 struct cvmx_lmcx_char_ctl_s cn66xx;
284 struct cvmx_lmcx_char_ctl_s cn68xx;
285 struct cvmx_lmcx_char_ctl_cn63xx cn68xxp1;
286 struct cvmx_lmcx_char_ctl_s cnf71xx;
287};
288
289union cvmx_lmcx_char_mask0 {
290 uint64_t u64;
291 struct cvmx_lmcx_char_mask0_s {
292#ifdef __BIG_ENDIAN_BITFIELD
293 uint64_t mask:64;
294#else
295 uint64_t mask:64;
296#endif
297 } s;
298 struct cvmx_lmcx_char_mask0_s cn61xx;
299 struct cvmx_lmcx_char_mask0_s cn63xx;
300 struct cvmx_lmcx_char_mask0_s cn63xxp1;
301 struct cvmx_lmcx_char_mask0_s cn66xx;
302 struct cvmx_lmcx_char_mask0_s cn68xx;
303 struct cvmx_lmcx_char_mask0_s cn68xxp1;
304 struct cvmx_lmcx_char_mask0_s cnf71xx;
305};
306
307union cvmx_lmcx_char_mask1 {
308 uint64_t u64;
309 struct cvmx_lmcx_char_mask1_s {
310#ifdef __BIG_ENDIAN_BITFIELD
311 uint64_t reserved_8_63:56;
312 uint64_t mask:8;
313#else
314 uint64_t mask:8;
315 uint64_t reserved_8_63:56;
316#endif
317 } s;
318 struct cvmx_lmcx_char_mask1_s cn61xx;
319 struct cvmx_lmcx_char_mask1_s cn63xx;
320 struct cvmx_lmcx_char_mask1_s cn63xxp1;
321 struct cvmx_lmcx_char_mask1_s cn66xx;
322 struct cvmx_lmcx_char_mask1_s cn68xx;
323 struct cvmx_lmcx_char_mask1_s cn68xxp1;
324 struct cvmx_lmcx_char_mask1_s cnf71xx;
325};
326
327union cvmx_lmcx_char_mask2 {
328 uint64_t u64;
329 struct cvmx_lmcx_char_mask2_s {
330#ifdef __BIG_ENDIAN_BITFIELD
331 uint64_t mask:64;
332#else
333 uint64_t mask:64;
334#endif
335 } s;
336 struct cvmx_lmcx_char_mask2_s cn61xx;
337 struct cvmx_lmcx_char_mask2_s cn63xx;
338 struct cvmx_lmcx_char_mask2_s cn63xxp1;
339 struct cvmx_lmcx_char_mask2_s cn66xx;
340 struct cvmx_lmcx_char_mask2_s cn68xx;
341 struct cvmx_lmcx_char_mask2_s cn68xxp1;
342 struct cvmx_lmcx_char_mask2_s cnf71xx;
343};
344
345union cvmx_lmcx_char_mask3 {
346 uint64_t u64;
347 struct cvmx_lmcx_char_mask3_s {
348#ifdef __BIG_ENDIAN_BITFIELD
349 uint64_t reserved_8_63:56;
350 uint64_t mask:8;
351#else
352 uint64_t mask:8;
353 uint64_t reserved_8_63:56;
354#endif
355 } s;
356 struct cvmx_lmcx_char_mask3_s cn61xx;
357 struct cvmx_lmcx_char_mask3_s cn63xx;
358 struct cvmx_lmcx_char_mask3_s cn63xxp1;
359 struct cvmx_lmcx_char_mask3_s cn66xx;
360 struct cvmx_lmcx_char_mask3_s cn68xx;
361 struct cvmx_lmcx_char_mask3_s cn68xxp1;
362 struct cvmx_lmcx_char_mask3_s cnf71xx;
363};
364
365union cvmx_lmcx_char_mask4 {
366 uint64_t u64;
367 struct cvmx_lmcx_char_mask4_s {
368#ifdef __BIG_ENDIAN_BITFIELD
369 uint64_t reserved_33_63:31;
370 uint64_t reset_n_mask:1;
371 uint64_t a_mask:16;
372 uint64_t ba_mask:3;
373 uint64_t we_n_mask:1;
374 uint64_t cas_n_mask:1;
375 uint64_t ras_n_mask:1;
376 uint64_t odt1_mask:2;
377 uint64_t odt0_mask:2;
378 uint64_t cs1_n_mask:2;
379 uint64_t cs0_n_mask:2;
380 uint64_t cke_mask:2;
381#else
382 uint64_t cke_mask:2;
383 uint64_t cs0_n_mask:2;
384 uint64_t cs1_n_mask:2;
385 uint64_t odt0_mask:2;
386 uint64_t odt1_mask:2;
387 uint64_t ras_n_mask:1;
388 uint64_t cas_n_mask:1;
389 uint64_t we_n_mask:1;
390 uint64_t ba_mask:3;
391 uint64_t a_mask:16;
392 uint64_t reset_n_mask:1;
393 uint64_t reserved_33_63:31;
394#endif
395 } s;
396 struct cvmx_lmcx_char_mask4_s cn61xx;
397 struct cvmx_lmcx_char_mask4_s cn63xx;
398 struct cvmx_lmcx_char_mask4_s cn63xxp1;
399 struct cvmx_lmcx_char_mask4_s cn66xx;
400 struct cvmx_lmcx_char_mask4_s cn68xx;
401 struct cvmx_lmcx_char_mask4_s cn68xxp1;
402 struct cvmx_lmcx_char_mask4_s cnf71xx;
403};
404
405union cvmx_lmcx_comp_ctl {
406 uint64_t u64;
407 struct cvmx_lmcx_comp_ctl_s {
408#ifdef __BIG_ENDIAN_BITFIELD
409 uint64_t reserved_32_63:32;
410 uint64_t nctl_csr:4;
411 uint64_t nctl_clk:4;
412 uint64_t nctl_cmd:4;
413 uint64_t nctl_dat:4;
414 uint64_t pctl_csr:4;
415 uint64_t pctl_clk:4;
416 uint64_t reserved_0_7:8;
417#else
418 uint64_t reserved_0_7:8;
419 uint64_t pctl_clk:4;
420 uint64_t pctl_csr:4;
421 uint64_t nctl_dat:4;
422 uint64_t nctl_cmd:4;
423 uint64_t nctl_clk:4;
424 uint64_t nctl_csr:4;
425 uint64_t reserved_32_63:32;
426#endif
427 } s;
428 struct cvmx_lmcx_comp_ctl_cn30xx {
429#ifdef __BIG_ENDIAN_BITFIELD
430 uint64_t reserved_32_63:32;
431 uint64_t nctl_csr:4;
432 uint64_t nctl_clk:4;
433 uint64_t nctl_cmd:4;
434 uint64_t nctl_dat:4;
435 uint64_t pctl_csr:4;
436 uint64_t pctl_clk:4;
437 uint64_t pctl_cmd:4;
438 uint64_t pctl_dat:4;
439#else
440 uint64_t pctl_dat:4;
441 uint64_t pctl_cmd:4;
442 uint64_t pctl_clk:4;
443 uint64_t pctl_csr:4;
444 uint64_t nctl_dat:4;
445 uint64_t nctl_cmd:4;
446 uint64_t nctl_clk:4;
447 uint64_t nctl_csr:4;
448 uint64_t reserved_32_63:32;
449#endif
450 } cn30xx;
451 struct cvmx_lmcx_comp_ctl_cn30xx cn31xx;
452 struct cvmx_lmcx_comp_ctl_cn30xx cn38xx;
453 struct cvmx_lmcx_comp_ctl_cn30xx cn38xxp2;
454 struct cvmx_lmcx_comp_ctl_cn50xx {
455#ifdef __BIG_ENDIAN_BITFIELD
456 uint64_t reserved_32_63:32;
457 uint64_t nctl_csr:4;
458 uint64_t reserved_20_27:8;
459 uint64_t nctl_dat:4;
460 uint64_t pctl_csr:4;
461 uint64_t reserved_5_11:7;
462 uint64_t pctl_dat:5;
463#else
464 uint64_t pctl_dat:5;
465 uint64_t reserved_5_11:7;
466 uint64_t pctl_csr:4;
467 uint64_t nctl_dat:4;
468 uint64_t reserved_20_27:8;
469 uint64_t nctl_csr:4;
470 uint64_t reserved_32_63:32;
471#endif
472 } cn50xx;
473 struct cvmx_lmcx_comp_ctl_cn50xx cn52xx;
474 struct cvmx_lmcx_comp_ctl_cn50xx cn52xxp1;
475 struct cvmx_lmcx_comp_ctl_cn50xx cn56xx;
476 struct cvmx_lmcx_comp_ctl_cn50xx cn56xxp1;
477 struct cvmx_lmcx_comp_ctl_cn50xx cn58xx;
478 struct cvmx_lmcx_comp_ctl_cn58xxp1 {
479#ifdef __BIG_ENDIAN_BITFIELD
480 uint64_t reserved_32_63:32;
481 uint64_t nctl_csr:4;
482 uint64_t reserved_20_27:8;
483 uint64_t nctl_dat:4;
484 uint64_t pctl_csr:4;
485 uint64_t reserved_4_11:8;
486 uint64_t pctl_dat:4;
487#else
488 uint64_t pctl_dat:4;
489 uint64_t reserved_4_11:8;
490 uint64_t pctl_csr:4;
491 uint64_t nctl_dat:4;
492 uint64_t reserved_20_27:8;
493 uint64_t nctl_csr:4;
494 uint64_t reserved_32_63:32;
495#endif
496 } cn58xxp1;
497};
498
499union cvmx_lmcx_comp_ctl2 {
500 uint64_t u64;
501 struct cvmx_lmcx_comp_ctl2_s {
502#ifdef __BIG_ENDIAN_BITFIELD
503 uint64_t reserved_34_63:30;
504 uint64_t ddr__ptune:4;
505 uint64_t ddr__ntune:4;
506 uint64_t m180:1;
507 uint64_t byp:1;
508 uint64_t ptune:4;
509 uint64_t ntune:4;
510 uint64_t rodt_ctl:4;
511 uint64_t cmd_ctl:4;
512 uint64_t ck_ctl:4;
513 uint64_t dqx_ctl:4;
514#else
515 uint64_t dqx_ctl:4;
516 uint64_t ck_ctl:4;
517 uint64_t cmd_ctl:4;
518 uint64_t rodt_ctl:4;
519 uint64_t ntune:4;
520 uint64_t ptune:4;
521 uint64_t byp:1;
522 uint64_t m180:1;
523 uint64_t ddr__ntune:4;
524 uint64_t ddr__ptune:4;
525 uint64_t reserved_34_63:30;
526#endif
527 } s;
528 struct cvmx_lmcx_comp_ctl2_s cn61xx;
529 struct cvmx_lmcx_comp_ctl2_s cn63xx;
530 struct cvmx_lmcx_comp_ctl2_s cn63xxp1;
531 struct cvmx_lmcx_comp_ctl2_s cn66xx;
532 struct cvmx_lmcx_comp_ctl2_s cn68xx;
533 struct cvmx_lmcx_comp_ctl2_s cn68xxp1;
534 struct cvmx_lmcx_comp_ctl2_s cnf71xx;
535};
536
537union cvmx_lmcx_config {
538 uint64_t u64;
539 struct cvmx_lmcx_config_s {
540#ifdef __BIG_ENDIAN_BITFIELD
541 uint64_t reserved_61_63:3;
542 uint64_t mode32b:1;
543 uint64_t scrz:1;
544 uint64_t early_unload_d1_r1:1;
545 uint64_t early_unload_d1_r0:1;
546 uint64_t early_unload_d0_r1:1;
547 uint64_t early_unload_d0_r0:1;
548 uint64_t init_status:4;
549 uint64_t mirrmask:4;
550 uint64_t rankmask:4;
551 uint64_t rank_ena:1;
552 uint64_t sref_with_dll:1;
553 uint64_t early_dqx:1;
554 uint64_t sequence:3;
555 uint64_t ref_zqcs_int:19;
556 uint64_t reset:1;
557 uint64_t ecc_adr:1;
558 uint64_t forcewrite:4;
559 uint64_t idlepower:3;
560 uint64_t pbank_lsb:4;
561 uint64_t row_lsb:3;
562 uint64_t ecc_ena:1;
563 uint64_t init_start:1;
564#else
565 uint64_t init_start:1;
566 uint64_t ecc_ena:1;
567 uint64_t row_lsb:3;
568 uint64_t pbank_lsb:4;
569 uint64_t idlepower:3;
570 uint64_t forcewrite:4;
571 uint64_t ecc_adr:1;
572 uint64_t reset:1;
573 uint64_t ref_zqcs_int:19;
574 uint64_t sequence:3;
575 uint64_t early_dqx:1;
576 uint64_t sref_with_dll:1;
577 uint64_t rank_ena:1;
578 uint64_t rankmask:4;
579 uint64_t mirrmask:4;
580 uint64_t init_status:4;
581 uint64_t early_unload_d0_r0:1;
582 uint64_t early_unload_d0_r1:1;
583 uint64_t early_unload_d1_r0:1;
584 uint64_t early_unload_d1_r1:1;
585 uint64_t scrz:1;
586 uint64_t mode32b:1;
587 uint64_t reserved_61_63:3;
588#endif
589 } s;
590 struct cvmx_lmcx_config_s cn61xx;
591 struct cvmx_lmcx_config_cn63xx {
592#ifdef __BIG_ENDIAN_BITFIELD
593 uint64_t reserved_59_63:5;
594 uint64_t early_unload_d1_r1:1;
595 uint64_t early_unload_d1_r0:1;
596 uint64_t early_unload_d0_r1:1;
597 uint64_t early_unload_d0_r0:1;
598 uint64_t init_status:4;
599 uint64_t mirrmask:4;
600 uint64_t rankmask:4;
601 uint64_t rank_ena:1;
602 uint64_t sref_with_dll:1;
603 uint64_t early_dqx:1;
604 uint64_t sequence:3;
605 uint64_t ref_zqcs_int:19;
606 uint64_t reset:1;
607 uint64_t ecc_adr:1;
608 uint64_t forcewrite:4;
609 uint64_t idlepower:3;
610 uint64_t pbank_lsb:4;
611 uint64_t row_lsb:3;
612 uint64_t ecc_ena:1;
613 uint64_t init_start:1;
614#else
615 uint64_t init_start:1;
616 uint64_t ecc_ena:1;
617 uint64_t row_lsb:3;
618 uint64_t pbank_lsb:4;
619 uint64_t idlepower:3;
620 uint64_t forcewrite:4;
621 uint64_t ecc_adr:1;
622 uint64_t reset:1;
623 uint64_t ref_zqcs_int:19;
624 uint64_t sequence:3;
625 uint64_t early_dqx:1;
626 uint64_t sref_with_dll:1;
627 uint64_t rank_ena:1;
628 uint64_t rankmask:4;
629 uint64_t mirrmask:4;
630 uint64_t init_status:4;
631 uint64_t early_unload_d0_r0:1;
632 uint64_t early_unload_d0_r1:1;
633 uint64_t early_unload_d1_r0:1;
634 uint64_t early_unload_d1_r1:1;
635 uint64_t reserved_59_63:5;
636#endif
637 } cn63xx;
638 struct cvmx_lmcx_config_cn63xxp1 {
639#ifdef __BIG_ENDIAN_BITFIELD
640 uint64_t reserved_55_63:9;
641 uint64_t init_status:4;
642 uint64_t mirrmask:4;
643 uint64_t rankmask:4;
644 uint64_t rank_ena:1;
645 uint64_t sref_with_dll:1;
646 uint64_t early_dqx:1;
647 uint64_t sequence:3;
648 uint64_t ref_zqcs_int:19;
649 uint64_t reset:1;
650 uint64_t ecc_adr:1;
651 uint64_t forcewrite:4;
652 uint64_t idlepower:3;
653 uint64_t pbank_lsb:4;
654 uint64_t row_lsb:3;
655 uint64_t ecc_ena:1;
656 uint64_t init_start:1;
657#else
658 uint64_t init_start:1;
659 uint64_t ecc_ena:1;
660 uint64_t row_lsb:3;
661 uint64_t pbank_lsb:4;
662 uint64_t idlepower:3;
663 uint64_t forcewrite:4;
664 uint64_t ecc_adr:1;
665 uint64_t reset:1;
666 uint64_t ref_zqcs_int:19;
667 uint64_t sequence:3;
668 uint64_t early_dqx:1;
669 uint64_t sref_with_dll:1;
670 uint64_t rank_ena:1;
671 uint64_t rankmask:4;
672 uint64_t mirrmask:4;
673 uint64_t init_status:4;
674 uint64_t reserved_55_63:9;
675#endif
676 } cn63xxp1;
677 struct cvmx_lmcx_config_cn66xx {
678#ifdef __BIG_ENDIAN_BITFIELD
679 uint64_t reserved_60_63:4;
680 uint64_t scrz:1;
681 uint64_t early_unload_d1_r1:1;
682 uint64_t early_unload_d1_r0:1;
683 uint64_t early_unload_d0_r1:1;
684 uint64_t early_unload_d0_r0:1;
685 uint64_t init_status:4;
686 uint64_t mirrmask:4;
687 uint64_t rankmask:4;
688 uint64_t rank_ena:1;
689 uint64_t sref_with_dll:1;
690 uint64_t early_dqx:1;
691 uint64_t sequence:3;
692 uint64_t ref_zqcs_int:19;
693 uint64_t reset:1;
694 uint64_t ecc_adr:1;
695 uint64_t forcewrite:4;
696 uint64_t idlepower:3;
697 uint64_t pbank_lsb:4;
698 uint64_t row_lsb:3;
699 uint64_t ecc_ena:1;
700 uint64_t init_start:1;
701#else
702 uint64_t init_start:1;
703 uint64_t ecc_ena:1;
704 uint64_t row_lsb:3;
705 uint64_t pbank_lsb:4;
706 uint64_t idlepower:3;
707 uint64_t forcewrite:4;
708 uint64_t ecc_adr:1;
709 uint64_t reset:1;
710 uint64_t ref_zqcs_int:19;
711 uint64_t sequence:3;
712 uint64_t early_dqx:1;
713 uint64_t sref_with_dll:1;
714 uint64_t rank_ena:1;
715 uint64_t rankmask:4;
716 uint64_t mirrmask:4;
717 uint64_t init_status:4;
718 uint64_t early_unload_d0_r0:1;
719 uint64_t early_unload_d0_r1:1;
720 uint64_t early_unload_d1_r0:1;
721 uint64_t early_unload_d1_r1:1;
722 uint64_t scrz:1;
723 uint64_t reserved_60_63:4;
724#endif
725 } cn66xx;
726 struct cvmx_lmcx_config_cn63xx cn68xx;
727 struct cvmx_lmcx_config_cn63xx cn68xxp1;
728 struct cvmx_lmcx_config_s cnf71xx;
729};
730
731union cvmx_lmcx_control {
732 uint64_t u64;
733 struct cvmx_lmcx_control_s {
734#ifdef __BIG_ENDIAN_BITFIELD
735 uint64_t scramble_ena:1;
736 uint64_t thrcnt:12;
737 uint64_t persub:8;
738 uint64_t thrmax:4;
739 uint64_t crm_cnt:5;
740 uint64_t crm_thr:5;
741 uint64_t crm_max:5;
742 uint64_t rodt_bprch:1;
743 uint64_t wodt_bprch:1;
744 uint64_t bprch:2;
745 uint64_t ext_zqcs_dis:1;
746 uint64_t int_zqcs_dis:1;
747 uint64_t auto_dclkdis:1;
748 uint64_t xor_bank:1;
749 uint64_t max_write_batch:4;
750 uint64_t nxm_write_en:1;
751 uint64_t elev_prio_dis:1;
752 uint64_t inorder_wr:1;
753 uint64_t inorder_rd:1;
754 uint64_t throttle_wr:1;
755 uint64_t throttle_rd:1;
756 uint64_t fprch2:2;
757 uint64_t pocas:1;
758 uint64_t ddr2t:1;
759 uint64_t bwcnt:1;
760 uint64_t rdimm_ena:1;
761#else
762 uint64_t rdimm_ena:1;
763 uint64_t bwcnt:1;
764 uint64_t ddr2t:1;
765 uint64_t pocas:1;
766 uint64_t fprch2:2;
767 uint64_t throttle_rd:1;
768 uint64_t throttle_wr:1;
769 uint64_t inorder_rd:1;
770 uint64_t inorder_wr:1;
771 uint64_t elev_prio_dis:1;
772 uint64_t nxm_write_en:1;
773 uint64_t max_write_batch:4;
774 uint64_t xor_bank:1;
775 uint64_t auto_dclkdis:1;
776 uint64_t int_zqcs_dis:1;
777 uint64_t ext_zqcs_dis:1;
778 uint64_t bprch:2;
779 uint64_t wodt_bprch:1;
780 uint64_t rodt_bprch:1;
781 uint64_t crm_max:5;
782 uint64_t crm_thr:5;
783 uint64_t crm_cnt:5;
784 uint64_t thrmax:4;
785 uint64_t persub:8;
786 uint64_t thrcnt:12;
787 uint64_t scramble_ena:1;
788#endif
789 } s;
790 struct cvmx_lmcx_control_s cn61xx;
791 struct cvmx_lmcx_control_cn63xx {
792#ifdef __BIG_ENDIAN_BITFIELD
793 uint64_t reserved_24_63:40;
794 uint64_t rodt_bprch:1;
795 uint64_t wodt_bprch:1;
796 uint64_t bprch:2;
797 uint64_t ext_zqcs_dis:1;
798 uint64_t int_zqcs_dis:1;
799 uint64_t auto_dclkdis:1;
800 uint64_t xor_bank:1;
801 uint64_t max_write_batch:4;
802 uint64_t nxm_write_en:1;
803 uint64_t elev_prio_dis:1;
804 uint64_t inorder_wr:1;
805 uint64_t inorder_rd:1;
806 uint64_t throttle_wr:1;
807 uint64_t throttle_rd:1;
808 uint64_t fprch2:2;
809 uint64_t pocas:1;
810 uint64_t ddr2t:1;
811 uint64_t bwcnt:1;
812 uint64_t rdimm_ena:1;
813#else
814 uint64_t rdimm_ena:1;
815 uint64_t bwcnt:1;
816 uint64_t ddr2t:1;
817 uint64_t pocas:1;
818 uint64_t fprch2:2;
819 uint64_t throttle_rd:1;
820 uint64_t throttle_wr:1;
821 uint64_t inorder_rd:1;
822 uint64_t inorder_wr:1;
823 uint64_t elev_prio_dis:1;
824 uint64_t nxm_write_en:1;
825 uint64_t max_write_batch:4;
826 uint64_t xor_bank:1;
827 uint64_t auto_dclkdis:1;
828 uint64_t int_zqcs_dis:1;
829 uint64_t ext_zqcs_dis:1;
830 uint64_t bprch:2;
831 uint64_t wodt_bprch:1;
832 uint64_t rodt_bprch:1;
833 uint64_t reserved_24_63:40;
834#endif
835 } cn63xx;
836 struct cvmx_lmcx_control_cn63xx cn63xxp1;
837 struct cvmx_lmcx_control_cn66xx {
838#ifdef __BIG_ENDIAN_BITFIELD
839 uint64_t scramble_ena:1;
840 uint64_t reserved_24_62:39;
841 uint64_t rodt_bprch:1;
842 uint64_t wodt_bprch:1;
843 uint64_t bprch:2;
844 uint64_t ext_zqcs_dis:1;
845 uint64_t int_zqcs_dis:1;
846 uint64_t auto_dclkdis:1;
847 uint64_t xor_bank:1;
848 uint64_t max_write_batch:4;
849 uint64_t nxm_write_en:1;
850 uint64_t elev_prio_dis:1;
851 uint64_t inorder_wr:1;
852 uint64_t inorder_rd:1;
853 uint64_t throttle_wr:1;
854 uint64_t throttle_rd:1;
855 uint64_t fprch2:2;
856 uint64_t pocas:1;
857 uint64_t ddr2t:1;
858 uint64_t bwcnt:1;
859 uint64_t rdimm_ena:1;
860#else
861 uint64_t rdimm_ena:1;
862 uint64_t bwcnt:1;
863 uint64_t ddr2t:1;
864 uint64_t pocas:1;
865 uint64_t fprch2:2;
866 uint64_t throttle_rd:1;
867 uint64_t throttle_wr:1;
868 uint64_t inorder_rd:1;
869 uint64_t inorder_wr:1;
870 uint64_t elev_prio_dis:1;
871 uint64_t nxm_write_en:1;
872 uint64_t max_write_batch:4;
873 uint64_t xor_bank:1;
874 uint64_t auto_dclkdis:1;
875 uint64_t int_zqcs_dis:1;
876 uint64_t ext_zqcs_dis:1;
877 uint64_t bprch:2;
878 uint64_t wodt_bprch:1;
879 uint64_t rodt_bprch:1;
880 uint64_t reserved_24_62:39;
881 uint64_t scramble_ena:1;
882#endif
883 } cn66xx;
884 struct cvmx_lmcx_control_cn68xx {
885#ifdef __BIG_ENDIAN_BITFIELD
886 uint64_t reserved_63_63:1;
887 uint64_t thrcnt:12;
888 uint64_t persub:8;
889 uint64_t thrmax:4;
890 uint64_t crm_cnt:5;
891 uint64_t crm_thr:5;
892 uint64_t crm_max:5;
893 uint64_t rodt_bprch:1;
894 uint64_t wodt_bprch:1;
895 uint64_t bprch:2;
896 uint64_t ext_zqcs_dis:1;
897 uint64_t int_zqcs_dis:1;
898 uint64_t auto_dclkdis:1;
899 uint64_t xor_bank:1;
900 uint64_t max_write_batch:4;
901 uint64_t nxm_write_en:1;
902 uint64_t elev_prio_dis:1;
903 uint64_t inorder_wr:1;
904 uint64_t inorder_rd:1;
905 uint64_t throttle_wr:1;
906 uint64_t throttle_rd:1;
907 uint64_t fprch2:2;
908 uint64_t pocas:1;
909 uint64_t ddr2t:1;
910 uint64_t bwcnt:1;
911 uint64_t rdimm_ena:1;
912#else
913 uint64_t rdimm_ena:1;
914 uint64_t bwcnt:1;
915 uint64_t ddr2t:1;
916 uint64_t pocas:1;
917 uint64_t fprch2:2;
918 uint64_t throttle_rd:1;
919 uint64_t throttle_wr:1;
920 uint64_t inorder_rd:1;
921 uint64_t inorder_wr:1;
922 uint64_t elev_prio_dis:1;
923 uint64_t nxm_write_en:1;
924 uint64_t max_write_batch:4;
925 uint64_t xor_bank:1;
926 uint64_t auto_dclkdis:1;
927 uint64_t int_zqcs_dis:1;
928 uint64_t ext_zqcs_dis:1;
929 uint64_t bprch:2;
930 uint64_t wodt_bprch:1;
931 uint64_t rodt_bprch:1;
932 uint64_t crm_max:5;
933 uint64_t crm_thr:5;
934 uint64_t crm_cnt:5;
935 uint64_t thrmax:4;
936 uint64_t persub:8;
937 uint64_t thrcnt:12;
938 uint64_t reserved_63_63:1;
939#endif
940 } cn68xx;
941 struct cvmx_lmcx_control_cn68xx cn68xxp1;
942 struct cvmx_lmcx_control_cn66xx cnf71xx;
943};
944
945union cvmx_lmcx_ctl {
946 uint64_t u64;
947 struct cvmx_lmcx_ctl_s {
948#ifdef __BIG_ENDIAN_BITFIELD
949 uint64_t reserved_32_63:32;
950 uint64_t ddr__nctl:4;
951 uint64_t ddr__pctl:4;
952 uint64_t slow_scf:1;
953 uint64_t xor_bank:1;
954 uint64_t max_write_batch:4;
955 uint64_t pll_div2:1;
956 uint64_t pll_bypass:1;
957 uint64_t rdimm_ena:1;
958 uint64_t r2r_slot:1;
959 uint64_t inorder_mwf:1;
960 uint64_t inorder_mrf:1;
961 uint64_t reserved_10_11:2;
962 uint64_t fprch2:1;
963 uint64_t bprch:1;
964 uint64_t sil_lat:2;
965 uint64_t tskw:2;
966 uint64_t qs_dic:2;
967 uint64_t dic:2;
968#else
969 uint64_t dic:2;
970 uint64_t qs_dic:2;
971 uint64_t tskw:2;
972 uint64_t sil_lat:2;
973 uint64_t bprch:1;
974 uint64_t fprch2:1;
975 uint64_t reserved_10_11:2;
976 uint64_t inorder_mrf:1;
977 uint64_t inorder_mwf:1;
978 uint64_t r2r_slot:1;
979 uint64_t rdimm_ena:1;
980 uint64_t pll_bypass:1;
981 uint64_t pll_div2:1;
982 uint64_t max_write_batch:4;
983 uint64_t xor_bank:1;
984 uint64_t slow_scf:1;
985 uint64_t ddr__pctl:4;
986 uint64_t ddr__nctl:4;
987 uint64_t reserved_32_63:32;
988#endif
989 } s;
990 struct cvmx_lmcx_ctl_cn30xx {
991#ifdef __BIG_ENDIAN_BITFIELD
992 uint64_t reserved_32_63:32;
993 uint64_t ddr__nctl:4;
994 uint64_t ddr__pctl:4;
995 uint64_t slow_scf:1;
996 uint64_t xor_bank:1;
997 uint64_t max_write_batch:4;
998 uint64_t pll_div2:1;
999 uint64_t pll_bypass:1;
1000 uint64_t rdimm_ena:1;
1001 uint64_t r2r_slot:1;
1002 uint64_t inorder_mwf:1;
1003 uint64_t inorder_mrf:1;
1004 uint64_t dreset:1;
1005 uint64_t mode32b:1;
1006 uint64_t fprch2:1;
1007 uint64_t bprch:1;
1008 uint64_t sil_lat:2;
1009 uint64_t tskw:2;
1010 uint64_t qs_dic:2;
1011 uint64_t dic:2;
1012#else
1013 uint64_t dic:2;
1014 uint64_t qs_dic:2;
1015 uint64_t tskw:2;
1016 uint64_t sil_lat:2;
1017 uint64_t bprch:1;
1018 uint64_t fprch2:1;
1019 uint64_t mode32b:1;
1020 uint64_t dreset:1;
1021 uint64_t inorder_mrf:1;
1022 uint64_t inorder_mwf:1;
1023 uint64_t r2r_slot:1;
1024 uint64_t rdimm_ena:1;
1025 uint64_t pll_bypass:1;
1026 uint64_t pll_div2:1;
1027 uint64_t max_write_batch:4;
1028 uint64_t xor_bank:1;
1029 uint64_t slow_scf:1;
1030 uint64_t ddr__pctl:4;
1031 uint64_t ddr__nctl:4;
1032 uint64_t reserved_32_63:32;
1033#endif
1034 } cn30xx;
1035 struct cvmx_lmcx_ctl_cn30xx cn31xx;
1036 struct cvmx_lmcx_ctl_cn38xx {
1037#ifdef __BIG_ENDIAN_BITFIELD
1038 uint64_t reserved_32_63:32;
1039 uint64_t ddr__nctl:4;
1040 uint64_t ddr__pctl:4;
1041 uint64_t slow_scf:1;
1042 uint64_t xor_bank:1;
1043 uint64_t max_write_batch:4;
1044 uint64_t reserved_16_17:2;
1045 uint64_t rdimm_ena:1;
1046 uint64_t r2r_slot:1;
1047 uint64_t inorder_mwf:1;
1048 uint64_t inorder_mrf:1;
1049 uint64_t set_zero:1;
1050 uint64_t mode128b:1;
1051 uint64_t fprch2:1;
1052 uint64_t bprch:1;
1053 uint64_t sil_lat:2;
1054 uint64_t tskw:2;
1055 uint64_t qs_dic:2;
1056 uint64_t dic:2;
1057#else
1058 uint64_t dic:2;
1059 uint64_t qs_dic:2;
1060 uint64_t tskw:2;
1061 uint64_t sil_lat:2;
1062 uint64_t bprch:1;
1063 uint64_t fprch2:1;
1064 uint64_t mode128b:1;
1065 uint64_t set_zero:1;
1066 uint64_t inorder_mrf:1;
1067 uint64_t inorder_mwf:1;
1068 uint64_t r2r_slot:1;
1069 uint64_t rdimm_ena:1;
1070 uint64_t reserved_16_17:2;
1071 uint64_t max_write_batch:4;
1072 uint64_t xor_bank:1;
1073 uint64_t slow_scf:1;
1074 uint64_t ddr__pctl:4;
1075 uint64_t ddr__nctl:4;
1076 uint64_t reserved_32_63:32;
1077#endif
1078 } cn38xx;
1079 struct cvmx_lmcx_ctl_cn38xx cn38xxp2;
1080 struct cvmx_lmcx_ctl_cn50xx {
1081#ifdef __BIG_ENDIAN_BITFIELD
1082 uint64_t reserved_32_63:32;
1083 uint64_t ddr__nctl:4;
1084 uint64_t ddr__pctl:4;
1085 uint64_t slow_scf:1;
1086 uint64_t xor_bank:1;
1087 uint64_t max_write_batch:4;
1088 uint64_t reserved_17_17:1;
1089 uint64_t pll_bypass:1;
1090 uint64_t rdimm_ena:1;
1091 uint64_t r2r_slot:1;
1092 uint64_t inorder_mwf:1;
1093 uint64_t inorder_mrf:1;
1094 uint64_t dreset:1;
1095 uint64_t mode32b:1;
1096 uint64_t fprch2:1;
1097 uint64_t bprch:1;
1098 uint64_t sil_lat:2;
1099 uint64_t tskw:2;
1100 uint64_t qs_dic:2;
1101 uint64_t dic:2;
1102#else
1103 uint64_t dic:2;
1104 uint64_t qs_dic:2;
1105 uint64_t tskw:2;
1106 uint64_t sil_lat:2;
1107 uint64_t bprch:1;
1108 uint64_t fprch2:1;
1109 uint64_t mode32b:1;
1110 uint64_t dreset:1;
1111 uint64_t inorder_mrf:1;
1112 uint64_t inorder_mwf:1;
1113 uint64_t r2r_slot:1;
1114 uint64_t rdimm_ena:1;
1115 uint64_t pll_bypass:1;
1116 uint64_t reserved_17_17:1;
1117 uint64_t max_write_batch:4;
1118 uint64_t xor_bank:1;
1119 uint64_t slow_scf:1;
1120 uint64_t ddr__pctl:4;
1121 uint64_t ddr__nctl:4;
1122 uint64_t reserved_32_63:32;
1123#endif
1124 } cn50xx;
1125 struct cvmx_lmcx_ctl_cn52xx {
1126#ifdef __BIG_ENDIAN_BITFIELD
1127 uint64_t reserved_32_63:32;
1128 uint64_t ddr__nctl:4;
1129 uint64_t ddr__pctl:4;
1130 uint64_t slow_scf:1;
1131 uint64_t xor_bank:1;
1132 uint64_t max_write_batch:4;
1133 uint64_t reserved_16_17:2;
1134 uint64_t rdimm_ena:1;
1135 uint64_t r2r_slot:1;
1136 uint64_t inorder_mwf:1;
1137 uint64_t inorder_mrf:1;
1138 uint64_t dreset:1;
1139 uint64_t mode32b:1;
1140 uint64_t fprch2:1;
1141 uint64_t bprch:1;
1142 uint64_t sil_lat:2;
1143 uint64_t tskw:2;
1144 uint64_t qs_dic:2;
1145 uint64_t dic:2;
1146#else
1147 uint64_t dic:2;
1148 uint64_t qs_dic:2;
1149 uint64_t tskw:2;
1150 uint64_t sil_lat:2;
1151 uint64_t bprch:1;
1152 uint64_t fprch2:1;
1153 uint64_t mode32b:1;
1154 uint64_t dreset:1;
1155 uint64_t inorder_mrf:1;
1156 uint64_t inorder_mwf:1;
1157 uint64_t r2r_slot:1;
1158 uint64_t rdimm_ena:1;
1159 uint64_t reserved_16_17:2;
1160 uint64_t max_write_batch:4;
1161 uint64_t xor_bank:1;
1162 uint64_t slow_scf:1;
1163 uint64_t ddr__pctl:4;
1164 uint64_t ddr__nctl:4;
1165 uint64_t reserved_32_63:32;
1166#endif
1167 } cn52xx;
1168 struct cvmx_lmcx_ctl_cn52xx cn52xxp1;
1169 struct cvmx_lmcx_ctl_cn52xx cn56xx;
1170 struct cvmx_lmcx_ctl_cn52xx cn56xxp1;
1171 struct cvmx_lmcx_ctl_cn58xx {
1172#ifdef __BIG_ENDIAN_BITFIELD
1173 uint64_t reserved_32_63:32;
1174 uint64_t ddr__nctl:4;
1175 uint64_t ddr__pctl:4;
1176 uint64_t slow_scf:1;
1177 uint64_t xor_bank:1;
1178 uint64_t max_write_batch:4;
1179 uint64_t reserved_16_17:2;
1180 uint64_t rdimm_ena:1;
1181 uint64_t r2r_slot:1;
1182 uint64_t inorder_mwf:1;
1183 uint64_t inorder_mrf:1;
1184 uint64_t dreset:1;
1185 uint64_t mode128b:1;
1186 uint64_t fprch2:1;
1187 uint64_t bprch:1;
1188 uint64_t sil_lat:2;
1189 uint64_t tskw:2;
1190 uint64_t qs_dic:2;
1191 uint64_t dic:2;
1192#else
1193 uint64_t dic:2;
1194 uint64_t qs_dic:2;
1195 uint64_t tskw:2;
1196 uint64_t sil_lat:2;
1197 uint64_t bprch:1;
1198 uint64_t fprch2:1;
1199 uint64_t mode128b:1;
1200 uint64_t dreset:1;
1201 uint64_t inorder_mrf:1;
1202 uint64_t inorder_mwf:1;
1203 uint64_t r2r_slot:1;
1204 uint64_t rdimm_ena:1;
1205 uint64_t reserved_16_17:2;
1206 uint64_t max_write_batch:4;
1207 uint64_t xor_bank:1;
1208 uint64_t slow_scf:1;
1209 uint64_t ddr__pctl:4;
1210 uint64_t ddr__nctl:4;
1211 uint64_t reserved_32_63:32;
1212#endif
1213 } cn58xx;
1214 struct cvmx_lmcx_ctl_cn58xx cn58xxp1;
1215};
1216
1217union cvmx_lmcx_ctl1 {
1218 uint64_t u64;
1219 struct cvmx_lmcx_ctl1_s {
1220#ifdef __BIG_ENDIAN_BITFIELD
1221 uint64_t reserved_21_63:43;
1222 uint64_t ecc_adr:1;
1223 uint64_t forcewrite:4;
1224 uint64_t idlepower:3;
1225 uint64_t sequence:3;
1226 uint64_t sil_mode:1;
1227 uint64_t dcc_enable:1;
1228 uint64_t reserved_2_7:6;
1229 uint64_t data_layout:2;
1230#else
1231 uint64_t data_layout:2;
1232 uint64_t reserved_2_7:6;
1233 uint64_t dcc_enable:1;
1234 uint64_t sil_mode:1;
1235 uint64_t sequence:3;
1236 uint64_t idlepower:3;
1237 uint64_t forcewrite:4;
1238 uint64_t ecc_adr:1;
1239 uint64_t reserved_21_63:43;
1240#endif
1241 } s;
1242 struct cvmx_lmcx_ctl1_cn30xx {
1243#ifdef __BIG_ENDIAN_BITFIELD
1244 uint64_t reserved_2_63:62;
1245 uint64_t data_layout:2;
1246#else
1247 uint64_t data_layout:2;
1248 uint64_t reserved_2_63:62;
1249#endif
1250 } cn30xx;
1251 struct cvmx_lmcx_ctl1_cn50xx {
1252#ifdef __BIG_ENDIAN_BITFIELD
1253 uint64_t reserved_10_63:54;
1254 uint64_t sil_mode:1;
1255 uint64_t dcc_enable:1;
1256 uint64_t reserved_2_7:6;
1257 uint64_t data_layout:2;
1258#else
1259 uint64_t data_layout:2;
1260 uint64_t reserved_2_7:6;
1261 uint64_t dcc_enable:1;
1262 uint64_t sil_mode:1;
1263 uint64_t reserved_10_63:54;
1264#endif
1265 } cn50xx;
1266 struct cvmx_lmcx_ctl1_cn52xx {
1267#ifdef __BIG_ENDIAN_BITFIELD
1268 uint64_t reserved_21_63:43;
1269 uint64_t ecc_adr:1;
1270 uint64_t forcewrite:4;
1271 uint64_t idlepower:3;
1272 uint64_t sequence:3;
1273 uint64_t sil_mode:1;
1274 uint64_t dcc_enable:1;
1275 uint64_t reserved_0_7:8;
1276#else
1277 uint64_t reserved_0_7:8;
1278 uint64_t dcc_enable:1;
1279 uint64_t sil_mode:1;
1280 uint64_t sequence:3;
1281 uint64_t idlepower:3;
1282 uint64_t forcewrite:4;
1283 uint64_t ecc_adr:1;
1284 uint64_t reserved_21_63:43;
1285#endif
1286 } cn52xx;
1287 struct cvmx_lmcx_ctl1_cn52xx cn52xxp1;
1288 struct cvmx_lmcx_ctl1_cn52xx cn56xx;
1289 struct cvmx_lmcx_ctl1_cn52xx cn56xxp1;
1290 struct cvmx_lmcx_ctl1_cn58xx {
1291#ifdef __BIG_ENDIAN_BITFIELD
1292 uint64_t reserved_10_63:54;
1293 uint64_t sil_mode:1;
1294 uint64_t dcc_enable:1;
1295 uint64_t reserved_0_7:8;
1296#else
1297 uint64_t reserved_0_7:8;
1298 uint64_t dcc_enable:1;
1299 uint64_t sil_mode:1;
1300 uint64_t reserved_10_63:54;
1301#endif
1302 } cn58xx;
1303 struct cvmx_lmcx_ctl1_cn58xx cn58xxp1;
1304};
1305
1306union cvmx_lmcx_dclk_cnt {
1307 uint64_t u64;
1308 struct cvmx_lmcx_dclk_cnt_s {
1309#ifdef __BIG_ENDIAN_BITFIELD
1310 uint64_t dclkcnt:64;
1311#else
1312 uint64_t dclkcnt:64;
1313#endif
1314 } s;
1315 struct cvmx_lmcx_dclk_cnt_s cn61xx;
1316 struct cvmx_lmcx_dclk_cnt_s cn63xx;
1317 struct cvmx_lmcx_dclk_cnt_s cn63xxp1;
1318 struct cvmx_lmcx_dclk_cnt_s cn66xx;
1319 struct cvmx_lmcx_dclk_cnt_s cn68xx;
1320 struct cvmx_lmcx_dclk_cnt_s cn68xxp1;
1321 struct cvmx_lmcx_dclk_cnt_s cnf71xx;
1322};
1323
1324union cvmx_lmcx_dclk_cnt_hi {
1325 uint64_t u64;
1326 struct cvmx_lmcx_dclk_cnt_hi_s {
1327#ifdef __BIG_ENDIAN_BITFIELD
1328 uint64_t reserved_32_63:32;
1329 uint64_t dclkcnt_hi:32;
1330#else
1331 uint64_t dclkcnt_hi:32;
1332 uint64_t reserved_32_63:32;
1333#endif
1334 } s;
1335 struct cvmx_lmcx_dclk_cnt_hi_s cn30xx;
1336 struct cvmx_lmcx_dclk_cnt_hi_s cn31xx;
1337 struct cvmx_lmcx_dclk_cnt_hi_s cn38xx;
1338 struct cvmx_lmcx_dclk_cnt_hi_s cn38xxp2;
1339 struct cvmx_lmcx_dclk_cnt_hi_s cn50xx;
1340 struct cvmx_lmcx_dclk_cnt_hi_s cn52xx;
1341 struct cvmx_lmcx_dclk_cnt_hi_s cn52xxp1;
1342 struct cvmx_lmcx_dclk_cnt_hi_s cn56xx;
1343 struct cvmx_lmcx_dclk_cnt_hi_s cn56xxp1;
1344 struct cvmx_lmcx_dclk_cnt_hi_s cn58xx;
1345 struct cvmx_lmcx_dclk_cnt_hi_s cn58xxp1;
1346};
1347
1348union cvmx_lmcx_dclk_cnt_lo {
1349 uint64_t u64;
1350 struct cvmx_lmcx_dclk_cnt_lo_s {
1351#ifdef __BIG_ENDIAN_BITFIELD
1352 uint64_t reserved_32_63:32;
1353 uint64_t dclkcnt_lo:32;
1354#else
1355 uint64_t dclkcnt_lo:32;
1356 uint64_t reserved_32_63:32;
1357#endif
1358 } s;
1359 struct cvmx_lmcx_dclk_cnt_lo_s cn30xx;
1360 struct cvmx_lmcx_dclk_cnt_lo_s cn31xx;
1361 struct cvmx_lmcx_dclk_cnt_lo_s cn38xx;
1362 struct cvmx_lmcx_dclk_cnt_lo_s cn38xxp2;
1363 struct cvmx_lmcx_dclk_cnt_lo_s cn50xx;
1364 struct cvmx_lmcx_dclk_cnt_lo_s cn52xx;
1365 struct cvmx_lmcx_dclk_cnt_lo_s cn52xxp1;
1366 struct cvmx_lmcx_dclk_cnt_lo_s cn56xx;
1367 struct cvmx_lmcx_dclk_cnt_lo_s cn56xxp1;
1368 struct cvmx_lmcx_dclk_cnt_lo_s cn58xx;
1369 struct cvmx_lmcx_dclk_cnt_lo_s cn58xxp1;
1370};
1371
1372union cvmx_lmcx_dclk_ctl {
1373 uint64_t u64;
1374 struct cvmx_lmcx_dclk_ctl_s {
1375#ifdef __BIG_ENDIAN_BITFIELD
1376 uint64_t reserved_8_63:56;
1377 uint64_t off90_ena:1;
1378 uint64_t dclk90_byp:1;
1379 uint64_t dclk90_ld:1;
1380 uint64_t dclk90_vlu:5;
1381#else
1382 uint64_t dclk90_vlu:5;
1383 uint64_t dclk90_ld:1;
1384 uint64_t dclk90_byp:1;
1385 uint64_t off90_ena:1;
1386 uint64_t reserved_8_63:56;
1387#endif
1388 } s;
1389 struct cvmx_lmcx_dclk_ctl_s cn56xx;
1390 struct cvmx_lmcx_dclk_ctl_s cn56xxp1;
1391};
1392
1393union cvmx_lmcx_ddr2_ctl {
1394 uint64_t u64;
1395 struct cvmx_lmcx_ddr2_ctl_s {
1396#ifdef __BIG_ENDIAN_BITFIELD
1397 uint64_t reserved_32_63:32;
1398 uint64_t bank8:1;
1399 uint64_t burst8:1;
1400 uint64_t addlat:3;
1401 uint64_t pocas:1;
1402 uint64_t bwcnt:1;
1403 uint64_t twr:3;
1404 uint64_t silo_hc:1;
1405 uint64_t ddr_eof:4;
1406 uint64_t tfaw:5;
1407 uint64_t crip_mode:1;
1408 uint64_t ddr2t:1;
1409 uint64_t odt_ena:1;
1410 uint64_t qdll_ena:1;
1411 uint64_t dll90_vlu:5;
1412 uint64_t dll90_byp:1;
1413 uint64_t rdqs:1;
1414 uint64_t ddr2:1;
1415#else
1416 uint64_t ddr2:1;
1417 uint64_t rdqs:1;
1418 uint64_t dll90_byp:1;
1419 uint64_t dll90_vlu:5;
1420 uint64_t qdll_ena:1;
1421 uint64_t odt_ena:1;
1422 uint64_t ddr2t:1;
1423 uint64_t crip_mode:1;
1424 uint64_t tfaw:5;
1425 uint64_t ddr_eof:4;
1426 uint64_t silo_hc:1;
1427 uint64_t twr:3;
1428 uint64_t bwcnt:1;
1429 uint64_t pocas:1;
1430 uint64_t addlat:3;
1431 uint64_t burst8:1;
1432 uint64_t bank8:1;
1433 uint64_t reserved_32_63:32;
1434#endif
1435 } s;
1436 struct cvmx_lmcx_ddr2_ctl_cn30xx {
1437#ifdef __BIG_ENDIAN_BITFIELD
1438 uint64_t reserved_32_63:32;
1439 uint64_t bank8:1;
1440 uint64_t burst8:1;
1441 uint64_t addlat:3;
1442 uint64_t pocas:1;
1443 uint64_t bwcnt:1;
1444 uint64_t twr:3;
1445 uint64_t silo_hc:1;
1446 uint64_t ddr_eof:4;
1447 uint64_t tfaw:5;
1448 uint64_t crip_mode:1;
1449 uint64_t ddr2t:1;
1450 uint64_t odt_ena:1;
1451 uint64_t qdll_ena:1;
1452 uint64_t dll90_vlu:5;
1453 uint64_t dll90_byp:1;
1454 uint64_t reserved_1_1:1;
1455 uint64_t ddr2:1;
1456#else
1457 uint64_t ddr2:1;
1458 uint64_t reserved_1_1:1;
1459 uint64_t dll90_byp:1;
1460 uint64_t dll90_vlu:5;
1461 uint64_t qdll_ena:1;
1462 uint64_t odt_ena:1;
1463 uint64_t ddr2t:1;
1464 uint64_t crip_mode:1;
1465 uint64_t tfaw:5;
1466 uint64_t ddr_eof:4;
1467 uint64_t silo_hc:1;
1468 uint64_t twr:3;
1469 uint64_t bwcnt:1;
1470 uint64_t pocas:1;
1471 uint64_t addlat:3;
1472 uint64_t burst8:1;
1473 uint64_t bank8:1;
1474 uint64_t reserved_32_63:32;
1475#endif
1476 } cn30xx;
1477 struct cvmx_lmcx_ddr2_ctl_cn30xx cn31xx;
1478 struct cvmx_lmcx_ddr2_ctl_s cn38xx;
1479 struct cvmx_lmcx_ddr2_ctl_s cn38xxp2;
1480 struct cvmx_lmcx_ddr2_ctl_s cn50xx;
1481 struct cvmx_lmcx_ddr2_ctl_s cn52xx;
1482 struct cvmx_lmcx_ddr2_ctl_s cn52xxp1;
1483 struct cvmx_lmcx_ddr2_ctl_s cn56xx;
1484 struct cvmx_lmcx_ddr2_ctl_s cn56xxp1;
1485 struct cvmx_lmcx_ddr2_ctl_s cn58xx;
1486 struct cvmx_lmcx_ddr2_ctl_s cn58xxp1;
1487};
1488
1489union cvmx_lmcx_ddr_pll_ctl {
1490 uint64_t u64;
1491 struct cvmx_lmcx_ddr_pll_ctl_s {
1492#ifdef __BIG_ENDIAN_BITFIELD
1493 uint64_t reserved_27_63:37;
1494 uint64_t jtg_test_mode:1;
1495 uint64_t dfm_div_reset:1;
1496 uint64_t dfm_ps_en:3;
1497 uint64_t ddr_div_reset:1;
1498 uint64_t ddr_ps_en:3;
1499 uint64_t diffamp:4;
1500 uint64_t cps:3;
1501 uint64_t cpb:3;
1502 uint64_t reset_n:1;
1503 uint64_t clkf:7;
1504#else
1505 uint64_t clkf:7;
1506 uint64_t reset_n:1;
1507 uint64_t cpb:3;
1508 uint64_t cps:3;
1509 uint64_t diffamp:4;
1510 uint64_t ddr_ps_en:3;
1511 uint64_t ddr_div_reset:1;
1512 uint64_t dfm_ps_en:3;
1513 uint64_t dfm_div_reset:1;
1514 uint64_t jtg_test_mode:1;
1515 uint64_t reserved_27_63:37;
1516#endif
1517 } s;
1518 struct cvmx_lmcx_ddr_pll_ctl_s cn61xx;
1519 struct cvmx_lmcx_ddr_pll_ctl_s cn63xx;
1520 struct cvmx_lmcx_ddr_pll_ctl_s cn63xxp1;
1521 struct cvmx_lmcx_ddr_pll_ctl_s cn66xx;
1522 struct cvmx_lmcx_ddr_pll_ctl_s cn68xx;
1523 struct cvmx_lmcx_ddr_pll_ctl_s cn68xxp1;
1524 struct cvmx_lmcx_ddr_pll_ctl_s cnf71xx;
1525};
1526
1527union cvmx_lmcx_delay_cfg {
1528 uint64_t u64;
1529 struct cvmx_lmcx_delay_cfg_s {
1530#ifdef __BIG_ENDIAN_BITFIELD
1531 uint64_t reserved_15_63:49;
1532 uint64_t dq:5;
1533 uint64_t cmd:5;
1534 uint64_t clk:5;
1535#else
1536 uint64_t clk:5;
1537 uint64_t cmd:5;
1538 uint64_t dq:5;
1539 uint64_t reserved_15_63:49;
1540#endif
1541 } s;
1542 struct cvmx_lmcx_delay_cfg_s cn30xx;
1543 struct cvmx_lmcx_delay_cfg_cn38xx {
1544#ifdef __BIG_ENDIAN_BITFIELD
1545 uint64_t reserved_14_63:50;
1546 uint64_t dq:4;
1547 uint64_t reserved_9_9:1;
1548 uint64_t cmd:4;
1549 uint64_t reserved_4_4:1;
1550 uint64_t clk:4;
1551#else
1552 uint64_t clk:4;
1553 uint64_t reserved_4_4:1;
1554 uint64_t cmd:4;
1555 uint64_t reserved_9_9:1;
1556 uint64_t dq:4;
1557 uint64_t reserved_14_63:50;
1558#endif
1559 } cn38xx;
1560 struct cvmx_lmcx_delay_cfg_cn38xx cn50xx;
1561 struct cvmx_lmcx_delay_cfg_cn38xx cn52xx;
1562 struct cvmx_lmcx_delay_cfg_cn38xx cn52xxp1;
1563 struct cvmx_lmcx_delay_cfg_cn38xx cn56xx;
1564 struct cvmx_lmcx_delay_cfg_cn38xx cn56xxp1;
1565 struct cvmx_lmcx_delay_cfg_cn38xx cn58xx;
1566 struct cvmx_lmcx_delay_cfg_cn38xx cn58xxp1;
1567};
1568
1569union cvmx_lmcx_dimmx_params {
1570 uint64_t u64;
1571 struct cvmx_lmcx_dimmx_params_s {
1572#ifdef __BIG_ENDIAN_BITFIELD
1573 uint64_t rc15:4;
1574 uint64_t rc14:4;
1575 uint64_t rc13:4;
1576 uint64_t rc12:4;
1577 uint64_t rc11:4;
1578 uint64_t rc10:4;
1579 uint64_t rc9:4;
1580 uint64_t rc8:4;
1581 uint64_t rc7:4;
1582 uint64_t rc6:4;
1583 uint64_t rc5:4;
1584 uint64_t rc4:4;
1585 uint64_t rc3:4;
1586 uint64_t rc2:4;
1587 uint64_t rc1:4;
1588 uint64_t rc0:4;
1589#else
1590 uint64_t rc0:4;
1591 uint64_t rc1:4;
1592 uint64_t rc2:4;
1593 uint64_t rc3:4;
1594 uint64_t rc4:4;
1595 uint64_t rc5:4;
1596 uint64_t rc6:4;
1597 uint64_t rc7:4;
1598 uint64_t rc8:4;
1599 uint64_t rc9:4;
1600 uint64_t rc10:4;
1601 uint64_t rc11:4;
1602 uint64_t rc12:4;
1603 uint64_t rc13:4;
1604 uint64_t rc14:4;
1605 uint64_t rc15:4;
1606#endif
1607 } s;
1608 struct cvmx_lmcx_dimmx_params_s cn61xx;
1609 struct cvmx_lmcx_dimmx_params_s cn63xx;
1610 struct cvmx_lmcx_dimmx_params_s cn63xxp1;
1611 struct cvmx_lmcx_dimmx_params_s cn66xx;
1612 struct cvmx_lmcx_dimmx_params_s cn68xx;
1613 struct cvmx_lmcx_dimmx_params_s cn68xxp1;
1614 struct cvmx_lmcx_dimmx_params_s cnf71xx;
1615};
1616
1617union cvmx_lmcx_dimm_ctl {
1618 uint64_t u64;
1619 struct cvmx_lmcx_dimm_ctl_s {
1620#ifdef __BIG_ENDIAN_BITFIELD
1621 uint64_t reserved_46_63:18;
1622 uint64_t parity:1;
1623 uint64_t tcws:13;
1624 uint64_t dimm1_wmask:16;
1625 uint64_t dimm0_wmask:16;
1626#else
1627 uint64_t dimm0_wmask:16;
1628 uint64_t dimm1_wmask:16;
1629 uint64_t tcws:13;
1630 uint64_t parity:1;
1631 uint64_t reserved_46_63:18;
1632#endif
1633 } s;
1634 struct cvmx_lmcx_dimm_ctl_s cn61xx;
1635 struct cvmx_lmcx_dimm_ctl_s cn63xx;
1636 struct cvmx_lmcx_dimm_ctl_s cn63xxp1;
1637 struct cvmx_lmcx_dimm_ctl_s cn66xx;
1638 struct cvmx_lmcx_dimm_ctl_s cn68xx;
1639 struct cvmx_lmcx_dimm_ctl_s cn68xxp1;
1640 struct cvmx_lmcx_dimm_ctl_s cnf71xx;
1641};
1642
1643union cvmx_lmcx_dll_ctl {
1644 uint64_t u64;
1645 struct cvmx_lmcx_dll_ctl_s {
1646#ifdef __BIG_ENDIAN_BITFIELD
1647 uint64_t reserved_8_63:56;
1648 uint64_t dreset:1;
1649 uint64_t dll90_byp:1;
1650 uint64_t dll90_ena:1;
1651 uint64_t dll90_vlu:5;
1652#else
1653 uint64_t dll90_vlu:5;
1654 uint64_t dll90_ena:1;
1655 uint64_t dll90_byp:1;
1656 uint64_t dreset:1;
1657 uint64_t reserved_8_63:56;
1658#endif
1659 } s;
1660 struct cvmx_lmcx_dll_ctl_s cn52xx;
1661 struct cvmx_lmcx_dll_ctl_s cn52xxp1;
1662 struct cvmx_lmcx_dll_ctl_s cn56xx;
1663 struct cvmx_lmcx_dll_ctl_s cn56xxp1;
1664};
1665
1666union cvmx_lmcx_dll_ctl2 {
1667 uint64_t u64;
1668 struct cvmx_lmcx_dll_ctl2_s {
1669#ifdef __BIG_ENDIAN_BITFIELD
1670 uint64_t reserved_16_63:48;
1671 uint64_t intf_en:1;
1672 uint64_t dll_bringup:1;
1673 uint64_t dreset:1;
1674 uint64_t quad_dll_ena:1;
1675 uint64_t byp_sel:4;
1676 uint64_t byp_setting:8;
1677#else
1678 uint64_t byp_setting:8;
1679 uint64_t byp_sel:4;
1680 uint64_t quad_dll_ena:1;
1681 uint64_t dreset:1;
1682 uint64_t dll_bringup:1;
1683 uint64_t intf_en:1;
1684 uint64_t reserved_16_63:48;
1685#endif
1686 } s;
1687 struct cvmx_lmcx_dll_ctl2_s cn61xx;
1688 struct cvmx_lmcx_dll_ctl2_cn63xx {
1689#ifdef __BIG_ENDIAN_BITFIELD
1690 uint64_t reserved_15_63:49;
1691 uint64_t dll_bringup:1;
1692 uint64_t dreset:1;
1693 uint64_t quad_dll_ena:1;
1694 uint64_t byp_sel:4;
1695 uint64_t byp_setting:8;
1696#else
1697 uint64_t byp_setting:8;
1698 uint64_t byp_sel:4;
1699 uint64_t quad_dll_ena:1;
1700 uint64_t dreset:1;
1701 uint64_t dll_bringup:1;
1702 uint64_t reserved_15_63:49;
1703#endif
1704 } cn63xx;
1705 struct cvmx_lmcx_dll_ctl2_cn63xx cn63xxp1;
1706 struct cvmx_lmcx_dll_ctl2_cn63xx cn66xx;
1707 struct cvmx_lmcx_dll_ctl2_s cn68xx;
1708 struct cvmx_lmcx_dll_ctl2_s cn68xxp1;
1709 struct cvmx_lmcx_dll_ctl2_s cnf71xx;
1710};
1711
1712union cvmx_lmcx_dll_ctl3 {
1713 uint64_t u64;
1714 struct cvmx_lmcx_dll_ctl3_s {
1715#ifdef __BIG_ENDIAN_BITFIELD
1716 uint64_t reserved_41_63:23;
1717 uint64_t dclk90_fwd:1;
1718 uint64_t ddr_90_dly_byp:1;
1719 uint64_t dclk90_recal_dis:1;
1720 uint64_t dclk90_byp_sel:1;
1721 uint64_t dclk90_byp_setting:8;
1722 uint64_t dll_fast:1;
1723 uint64_t dll90_setting:8;
1724 uint64_t fine_tune_mode:1;
1725 uint64_t dll_mode:1;
1726 uint64_t dll90_byte_sel:4;
1727 uint64_t offset_ena:1;
1728 uint64_t load_offset:1;
1729 uint64_t mode_sel:2;
1730 uint64_t byte_sel:4;
1731 uint64_t offset:6;
1732#else
1733 uint64_t offset:6;
1734 uint64_t byte_sel:4;
1735 uint64_t mode_sel:2;
1736 uint64_t load_offset:1;
1737 uint64_t offset_ena:1;
1738 uint64_t dll90_byte_sel:4;
1739 uint64_t dll_mode:1;
1740 uint64_t fine_tune_mode:1;
1741 uint64_t dll90_setting:8;
1742 uint64_t dll_fast:1;
1743 uint64_t dclk90_byp_setting:8;
1744 uint64_t dclk90_byp_sel:1;
1745 uint64_t dclk90_recal_dis:1;
1746 uint64_t ddr_90_dly_byp:1;
1747 uint64_t dclk90_fwd:1;
1748 uint64_t reserved_41_63:23;
1749#endif
1750 } s;
1751 struct cvmx_lmcx_dll_ctl3_s cn61xx;
1752 struct cvmx_lmcx_dll_ctl3_cn63xx {
1753#ifdef __BIG_ENDIAN_BITFIELD
1754 uint64_t reserved_29_63:35;
1755 uint64_t dll_fast:1;
1756 uint64_t dll90_setting:8;
1757 uint64_t fine_tune_mode:1;
1758 uint64_t dll_mode:1;
1759 uint64_t dll90_byte_sel:4;
1760 uint64_t offset_ena:1;
1761 uint64_t load_offset:1;
1762 uint64_t mode_sel:2;
1763 uint64_t byte_sel:4;
1764 uint64_t offset:6;
1765#else
1766 uint64_t offset:6;
1767 uint64_t byte_sel:4;
1768 uint64_t mode_sel:2;
1769 uint64_t load_offset:1;
1770 uint64_t offset_ena:1;
1771 uint64_t dll90_byte_sel:4;
1772 uint64_t dll_mode:1;
1773 uint64_t fine_tune_mode:1;
1774 uint64_t dll90_setting:8;
1775 uint64_t dll_fast:1;
1776 uint64_t reserved_29_63:35;
1777#endif
1778 } cn63xx;
1779 struct cvmx_lmcx_dll_ctl3_cn63xx cn63xxp1;
1780 struct cvmx_lmcx_dll_ctl3_cn63xx cn66xx;
1781 struct cvmx_lmcx_dll_ctl3_s cn68xx;
1782 struct cvmx_lmcx_dll_ctl3_s cn68xxp1;
1783 struct cvmx_lmcx_dll_ctl3_s cnf71xx;
1784};
1785
1786union cvmx_lmcx_dual_memcfg {
1787 uint64_t u64;
1788 struct cvmx_lmcx_dual_memcfg_s {
1789#ifdef __BIG_ENDIAN_BITFIELD
1790 uint64_t reserved_20_63:44;
1791 uint64_t bank8:1;
1792 uint64_t row_lsb:3;
1793 uint64_t reserved_8_15:8;
1794 uint64_t cs_mask:8;
1795#else
1796 uint64_t cs_mask:8;
1797 uint64_t reserved_8_15:8;
1798 uint64_t row_lsb:3;
1799 uint64_t bank8:1;
1800 uint64_t reserved_20_63:44;
1801#endif
1802 } s;
1803 struct cvmx_lmcx_dual_memcfg_s cn50xx;
1804 struct cvmx_lmcx_dual_memcfg_s cn52xx;
1805 struct cvmx_lmcx_dual_memcfg_s cn52xxp1;
1806 struct cvmx_lmcx_dual_memcfg_s cn56xx;
1807 struct cvmx_lmcx_dual_memcfg_s cn56xxp1;
1808 struct cvmx_lmcx_dual_memcfg_s cn58xx;
1809 struct cvmx_lmcx_dual_memcfg_s cn58xxp1;
1810 struct cvmx_lmcx_dual_memcfg_cn61xx {
1811#ifdef __BIG_ENDIAN_BITFIELD
1812 uint64_t reserved_19_63:45;
1813 uint64_t row_lsb:3;
1814 uint64_t reserved_8_15:8;
1815 uint64_t cs_mask:8;
1816#else
1817 uint64_t cs_mask:8;
1818 uint64_t reserved_8_15:8;
1819 uint64_t row_lsb:3;
1820 uint64_t reserved_19_63:45;
1821#endif
1822 } cn61xx;
1823 struct cvmx_lmcx_dual_memcfg_cn61xx cn63xx;
1824 struct cvmx_lmcx_dual_memcfg_cn61xx cn63xxp1;
1825 struct cvmx_lmcx_dual_memcfg_cn61xx cn66xx;
1826 struct cvmx_lmcx_dual_memcfg_cn61xx cn68xx;
1827 struct cvmx_lmcx_dual_memcfg_cn61xx cn68xxp1;
1828 struct cvmx_lmcx_dual_memcfg_cn61xx cnf71xx;
1829};
1830
1831union cvmx_lmcx_ecc_synd {
1832 uint64_t u64;
1833 struct cvmx_lmcx_ecc_synd_s {
1834#ifdef __BIG_ENDIAN_BITFIELD
1835 uint64_t reserved_32_63:32;
1836 uint64_t mrdsyn3:8;
1837 uint64_t mrdsyn2:8;
1838 uint64_t mrdsyn1:8;
1839 uint64_t mrdsyn0:8;
1840#else
1841 uint64_t mrdsyn0:8;
1842 uint64_t mrdsyn1:8;
1843 uint64_t mrdsyn2:8;
1844 uint64_t mrdsyn3:8;
1845 uint64_t reserved_32_63:32;
1846#endif
1847 } s;
1848 struct cvmx_lmcx_ecc_synd_s cn30xx;
1849 struct cvmx_lmcx_ecc_synd_s cn31xx;
1850 struct cvmx_lmcx_ecc_synd_s cn38xx;
1851 struct cvmx_lmcx_ecc_synd_s cn38xxp2;
1852 struct cvmx_lmcx_ecc_synd_s cn50xx;
1853 struct cvmx_lmcx_ecc_synd_s cn52xx;
1854 struct cvmx_lmcx_ecc_synd_s cn52xxp1;
1855 struct cvmx_lmcx_ecc_synd_s cn56xx;
1856 struct cvmx_lmcx_ecc_synd_s cn56xxp1;
1857 struct cvmx_lmcx_ecc_synd_s cn58xx;
1858 struct cvmx_lmcx_ecc_synd_s cn58xxp1;
1859 struct cvmx_lmcx_ecc_synd_s cn61xx;
1860 struct cvmx_lmcx_ecc_synd_s cn63xx;
1861 struct cvmx_lmcx_ecc_synd_s cn63xxp1;
1862 struct cvmx_lmcx_ecc_synd_s cn66xx;
1863 struct cvmx_lmcx_ecc_synd_s cn68xx;
1864 struct cvmx_lmcx_ecc_synd_s cn68xxp1;
1865 struct cvmx_lmcx_ecc_synd_s cnf71xx;
1866};
1867
1868union cvmx_lmcx_fadr {
1869 uint64_t u64;
1870 struct cvmx_lmcx_fadr_s {
1871#ifdef __BIG_ENDIAN_BITFIELD
1872 uint64_t reserved_0_63:64;
1873#else
1874 uint64_t reserved_0_63:64;
1875#endif
1876 } s;
1877 struct cvmx_lmcx_fadr_cn30xx {
1878#ifdef __BIG_ENDIAN_BITFIELD
1879 uint64_t reserved_32_63:32;
1880 uint64_t fdimm:2;
1881 uint64_t fbunk:1;
1882 uint64_t fbank:3;
1883 uint64_t frow:14;
1884 uint64_t fcol:12;
1885#else
1886 uint64_t fcol:12;
1887 uint64_t frow:14;
1888 uint64_t fbank:3;
1889 uint64_t fbunk:1;
1890 uint64_t fdimm:2;
1891 uint64_t reserved_32_63:32;
1892#endif
1893 } cn30xx;
1894 struct cvmx_lmcx_fadr_cn30xx cn31xx;
1895 struct cvmx_lmcx_fadr_cn30xx cn38xx;
1896 struct cvmx_lmcx_fadr_cn30xx cn38xxp2;
1897 struct cvmx_lmcx_fadr_cn30xx cn50xx;
1898 struct cvmx_lmcx_fadr_cn30xx cn52xx;
1899 struct cvmx_lmcx_fadr_cn30xx cn52xxp1;
1900 struct cvmx_lmcx_fadr_cn30xx cn56xx;
1901 struct cvmx_lmcx_fadr_cn30xx cn56xxp1;
1902 struct cvmx_lmcx_fadr_cn30xx cn58xx;
1903 struct cvmx_lmcx_fadr_cn30xx cn58xxp1;
1904 struct cvmx_lmcx_fadr_cn61xx {
1905#ifdef __BIG_ENDIAN_BITFIELD
1906 uint64_t reserved_36_63:28;
1907 uint64_t fdimm:2;
1908 uint64_t fbunk:1;
1909 uint64_t fbank:3;
1910 uint64_t frow:16;
1911 uint64_t fcol:14;
1912#else
1913 uint64_t fcol:14;
1914 uint64_t frow:16;
1915 uint64_t fbank:3;
1916 uint64_t fbunk:1;
1917 uint64_t fdimm:2;
1918 uint64_t reserved_36_63:28;
1919#endif
1920 } cn61xx;
1921 struct cvmx_lmcx_fadr_cn61xx cn63xx;
1922 struct cvmx_lmcx_fadr_cn61xx cn63xxp1;
1923 struct cvmx_lmcx_fadr_cn61xx cn66xx;
1924 struct cvmx_lmcx_fadr_cn61xx cn68xx;
1925 struct cvmx_lmcx_fadr_cn61xx cn68xxp1;
1926 struct cvmx_lmcx_fadr_cn61xx cnf71xx;
1927};
1928
1929union cvmx_lmcx_ifb_cnt {
1930 uint64_t u64;
1931 struct cvmx_lmcx_ifb_cnt_s {
1932#ifdef __BIG_ENDIAN_BITFIELD
1933 uint64_t ifbcnt:64;
1934#else
1935 uint64_t ifbcnt:64;
1936#endif
1937 } s;
1938 struct cvmx_lmcx_ifb_cnt_s cn61xx;
1939 struct cvmx_lmcx_ifb_cnt_s cn63xx;
1940 struct cvmx_lmcx_ifb_cnt_s cn63xxp1;
1941 struct cvmx_lmcx_ifb_cnt_s cn66xx;
1942 struct cvmx_lmcx_ifb_cnt_s cn68xx;
1943 struct cvmx_lmcx_ifb_cnt_s cn68xxp1;
1944 struct cvmx_lmcx_ifb_cnt_s cnf71xx;
1945};
1946
1947union cvmx_lmcx_ifb_cnt_hi {
1948 uint64_t u64;
1949 struct cvmx_lmcx_ifb_cnt_hi_s {
1950#ifdef __BIG_ENDIAN_BITFIELD
1951 uint64_t reserved_32_63:32;
1952 uint64_t ifbcnt_hi:32;
1953#else
1954 uint64_t ifbcnt_hi:32;
1955 uint64_t reserved_32_63:32;
1956#endif
1957 } s;
1958 struct cvmx_lmcx_ifb_cnt_hi_s cn30xx;
1959 struct cvmx_lmcx_ifb_cnt_hi_s cn31xx;
1960 struct cvmx_lmcx_ifb_cnt_hi_s cn38xx;
1961 struct cvmx_lmcx_ifb_cnt_hi_s cn38xxp2;
1962 struct cvmx_lmcx_ifb_cnt_hi_s cn50xx;
1963 struct cvmx_lmcx_ifb_cnt_hi_s cn52xx;
1964 struct cvmx_lmcx_ifb_cnt_hi_s cn52xxp1;
1965 struct cvmx_lmcx_ifb_cnt_hi_s cn56xx;
1966 struct cvmx_lmcx_ifb_cnt_hi_s cn56xxp1;
1967 struct cvmx_lmcx_ifb_cnt_hi_s cn58xx;
1968 struct cvmx_lmcx_ifb_cnt_hi_s cn58xxp1;
1969};
1970
1971union cvmx_lmcx_ifb_cnt_lo {
1972 uint64_t u64;
1973 struct cvmx_lmcx_ifb_cnt_lo_s {
1974#ifdef __BIG_ENDIAN_BITFIELD
1975 uint64_t reserved_32_63:32;
1976 uint64_t ifbcnt_lo:32;
1977#else
1978 uint64_t ifbcnt_lo:32;
1979 uint64_t reserved_32_63:32;
1980#endif
1981 } s;
1982 struct cvmx_lmcx_ifb_cnt_lo_s cn30xx;
1983 struct cvmx_lmcx_ifb_cnt_lo_s cn31xx;
1984 struct cvmx_lmcx_ifb_cnt_lo_s cn38xx;
1985 struct cvmx_lmcx_ifb_cnt_lo_s cn38xxp2;
1986 struct cvmx_lmcx_ifb_cnt_lo_s cn50xx;
1987 struct cvmx_lmcx_ifb_cnt_lo_s cn52xx;
1988 struct cvmx_lmcx_ifb_cnt_lo_s cn52xxp1;
1989 struct cvmx_lmcx_ifb_cnt_lo_s cn56xx;
1990 struct cvmx_lmcx_ifb_cnt_lo_s cn56xxp1;
1991 struct cvmx_lmcx_ifb_cnt_lo_s cn58xx;
1992 struct cvmx_lmcx_ifb_cnt_lo_s cn58xxp1;
1993};
1994
1995union cvmx_lmcx_int {
1996 uint64_t u64;
1997 struct cvmx_lmcx_int_s {
1998#ifdef __BIG_ENDIAN_BITFIELD
1999 uint64_t reserved_9_63:55;
2000 uint64_t ded_err:4;
2001 uint64_t sec_err:4;
2002 uint64_t nxm_wr_err:1;
2003#else
2004 uint64_t nxm_wr_err:1;
2005 uint64_t sec_err:4;
2006 uint64_t ded_err:4;
2007 uint64_t reserved_9_63:55;
2008#endif
2009 } s;
2010 struct cvmx_lmcx_int_s cn61xx;
2011 struct cvmx_lmcx_int_s cn63xx;
2012 struct cvmx_lmcx_int_s cn63xxp1;
2013 struct cvmx_lmcx_int_s cn66xx;
2014 struct cvmx_lmcx_int_s cn68xx;
2015 struct cvmx_lmcx_int_s cn68xxp1;
2016 struct cvmx_lmcx_int_s cnf71xx;
2017};
2018
2019union cvmx_lmcx_int_en {
2020 uint64_t u64;
2021 struct cvmx_lmcx_int_en_s {
2022#ifdef __BIG_ENDIAN_BITFIELD
2023 uint64_t reserved_3_63:61;
2024 uint64_t intr_ded_ena:1;
2025 uint64_t intr_sec_ena:1;
2026 uint64_t intr_nxm_wr_ena:1;
2027#else
2028 uint64_t intr_nxm_wr_ena:1;
2029 uint64_t intr_sec_ena:1;
2030 uint64_t intr_ded_ena:1;
2031 uint64_t reserved_3_63:61;
2032#endif
2033 } s;
2034 struct cvmx_lmcx_int_en_s cn61xx;
2035 struct cvmx_lmcx_int_en_s cn63xx;
2036 struct cvmx_lmcx_int_en_s cn63xxp1;
2037 struct cvmx_lmcx_int_en_s cn66xx;
2038 struct cvmx_lmcx_int_en_s cn68xx;
2039 struct cvmx_lmcx_int_en_s cn68xxp1;
2040 struct cvmx_lmcx_int_en_s cnf71xx;
2041};
2042
2043union cvmx_lmcx_mem_cfg0 {
2044 uint64_t u64;
2045 struct cvmx_lmcx_mem_cfg0_s {
2046#ifdef __BIG_ENDIAN_BITFIELD
2047 uint64_t reserved_32_63:32;
2048 uint64_t reset:1;
2049 uint64_t silo_qc:1;
2050 uint64_t bunk_ena:1;
2051 uint64_t ded_err:4;
2052 uint64_t sec_err:4;
2053 uint64_t intr_ded_ena:1;
2054 uint64_t intr_sec_ena:1;
2055 uint64_t tcl:4;
2056 uint64_t ref_int:6;
2057 uint64_t pbank_lsb:4;
2058 uint64_t row_lsb:3;
2059 uint64_t ecc_ena:1;
2060 uint64_t init_start:1;
2061#else
2062 uint64_t init_start:1;
2063 uint64_t ecc_ena:1;
2064 uint64_t row_lsb:3;
2065 uint64_t pbank_lsb:4;
2066 uint64_t ref_int:6;
2067 uint64_t tcl:4;
2068 uint64_t intr_sec_ena:1;
2069 uint64_t intr_ded_ena:1;
2070 uint64_t sec_err:4;
2071 uint64_t ded_err:4;
2072 uint64_t bunk_ena:1;
2073 uint64_t silo_qc:1;
2074 uint64_t reset:1;
2075 uint64_t reserved_32_63:32;
2076#endif
2077 } s;
2078 struct cvmx_lmcx_mem_cfg0_s cn30xx;
2079 struct cvmx_lmcx_mem_cfg0_s cn31xx;
2080 struct cvmx_lmcx_mem_cfg0_s cn38xx;
2081 struct cvmx_lmcx_mem_cfg0_s cn38xxp2;
2082 struct cvmx_lmcx_mem_cfg0_s cn50xx;
2083 struct cvmx_lmcx_mem_cfg0_s cn52xx;
2084 struct cvmx_lmcx_mem_cfg0_s cn52xxp1;
2085 struct cvmx_lmcx_mem_cfg0_s cn56xx;
2086 struct cvmx_lmcx_mem_cfg0_s cn56xxp1;
2087 struct cvmx_lmcx_mem_cfg0_s cn58xx;
2088 struct cvmx_lmcx_mem_cfg0_s cn58xxp1;
2089};
2090
2091union cvmx_lmcx_mem_cfg1 {
2092 uint64_t u64;
2093 struct cvmx_lmcx_mem_cfg1_s {
2094#ifdef __BIG_ENDIAN_BITFIELD
2095 uint64_t reserved_32_63:32;
2096 uint64_t comp_bypass:1;
2097 uint64_t trrd:3;
2098 uint64_t caslat:3;
2099 uint64_t tmrd:3;
2100 uint64_t trfc:5;
2101 uint64_t trp:4;
2102 uint64_t twtr:4;
2103 uint64_t trcd:4;
2104 uint64_t tras:5;
2105#else
2106 uint64_t tras:5;
2107 uint64_t trcd:4;
2108 uint64_t twtr:4;
2109 uint64_t trp:4;
2110 uint64_t trfc:5;
2111 uint64_t tmrd:3;
2112 uint64_t caslat:3;
2113 uint64_t trrd:3;
2114 uint64_t comp_bypass:1;
2115 uint64_t reserved_32_63:32;
2116#endif
2117 } s;
2118 struct cvmx_lmcx_mem_cfg1_s cn30xx;
2119 struct cvmx_lmcx_mem_cfg1_s cn31xx;
2120 struct cvmx_lmcx_mem_cfg1_cn38xx {
2121#ifdef __BIG_ENDIAN_BITFIELD
2122 uint64_t reserved_31_63:33;
2123 uint64_t trrd:3;
2124 uint64_t caslat:3;
2125 uint64_t tmrd:3;
2126 uint64_t trfc:5;
2127 uint64_t trp:4;
2128 uint64_t twtr:4;
2129 uint64_t trcd:4;
2130 uint64_t tras:5;
2131#else
2132 uint64_t tras:5;
2133 uint64_t trcd:4;
2134 uint64_t twtr:4;
2135 uint64_t trp:4;
2136 uint64_t trfc:5;
2137 uint64_t tmrd:3;
2138 uint64_t caslat:3;
2139 uint64_t trrd:3;
2140 uint64_t reserved_31_63:33;
2141#endif
2142 } cn38xx;
2143 struct cvmx_lmcx_mem_cfg1_cn38xx cn38xxp2;
2144 struct cvmx_lmcx_mem_cfg1_s cn50xx;
2145 struct cvmx_lmcx_mem_cfg1_cn38xx cn52xx;
2146 struct cvmx_lmcx_mem_cfg1_cn38xx cn52xxp1;
2147 struct cvmx_lmcx_mem_cfg1_cn38xx cn56xx;
2148 struct cvmx_lmcx_mem_cfg1_cn38xx cn56xxp1;
2149 struct cvmx_lmcx_mem_cfg1_cn38xx cn58xx;
2150 struct cvmx_lmcx_mem_cfg1_cn38xx cn58xxp1;
2151};
2152
2153union cvmx_lmcx_modereg_params0 {
2154 uint64_t u64;
2155 struct cvmx_lmcx_modereg_params0_s {
2156#ifdef __BIG_ENDIAN_BITFIELD
2157 uint64_t reserved_25_63:39;
2158 uint64_t ppd:1;
2159 uint64_t wrp:3;
2160 uint64_t dllr:1;
2161 uint64_t tm:1;
2162 uint64_t rbt:1;
2163 uint64_t cl:4;
2164 uint64_t bl:2;
2165 uint64_t qoff:1;
2166 uint64_t tdqs:1;
2167 uint64_t wlev:1;
2168 uint64_t al:2;
2169 uint64_t dll:1;
2170 uint64_t mpr:1;
2171 uint64_t mprloc:2;
2172 uint64_t cwl:3;
2173#else
2174 uint64_t cwl:3;
2175 uint64_t mprloc:2;
2176 uint64_t mpr:1;
2177 uint64_t dll:1;
2178 uint64_t al:2;
2179 uint64_t wlev:1;
2180 uint64_t tdqs:1;
2181 uint64_t qoff:1;
2182 uint64_t bl:2;
2183 uint64_t cl:4;
2184 uint64_t rbt:1;
2185 uint64_t tm:1;
2186 uint64_t dllr:1;
2187 uint64_t wrp:3;
2188 uint64_t ppd:1;
2189 uint64_t reserved_25_63:39;
2190#endif
2191 } s;
2192 struct cvmx_lmcx_modereg_params0_s cn61xx;
2193 struct cvmx_lmcx_modereg_params0_s cn63xx;
2194 struct cvmx_lmcx_modereg_params0_s cn63xxp1;
2195 struct cvmx_lmcx_modereg_params0_s cn66xx;
2196 struct cvmx_lmcx_modereg_params0_s cn68xx;
2197 struct cvmx_lmcx_modereg_params0_s cn68xxp1;
2198 struct cvmx_lmcx_modereg_params0_s cnf71xx;
2199};
2200
2201union cvmx_lmcx_modereg_params1 {
2202 uint64_t u64;
2203 struct cvmx_lmcx_modereg_params1_s {
2204#ifdef __BIG_ENDIAN_BITFIELD
2205 uint64_t reserved_48_63:16;
2206 uint64_t rtt_nom_11:3;
2207 uint64_t dic_11:2;
2208 uint64_t rtt_wr_11:2;
2209 uint64_t srt_11:1;
2210 uint64_t asr_11:1;
2211 uint64_t pasr_11:3;
2212 uint64_t rtt_nom_10:3;
2213 uint64_t dic_10:2;
2214 uint64_t rtt_wr_10:2;
2215 uint64_t srt_10:1;
2216 uint64_t asr_10:1;
2217 uint64_t pasr_10:3;
2218 uint64_t rtt_nom_01:3;
2219 uint64_t dic_01:2;
2220 uint64_t rtt_wr_01:2;
2221 uint64_t srt_01:1;
2222 uint64_t asr_01:1;
2223 uint64_t pasr_01:3;
2224 uint64_t rtt_nom_00:3;
2225 uint64_t dic_00:2;
2226 uint64_t rtt_wr_00:2;
2227 uint64_t srt_00:1;
2228 uint64_t asr_00:1;
2229 uint64_t pasr_00:3;
2230#else
2231 uint64_t pasr_00:3;
2232 uint64_t asr_00:1;
2233 uint64_t srt_00:1;
2234 uint64_t rtt_wr_00:2;
2235 uint64_t dic_00:2;
2236 uint64_t rtt_nom_00:3;
2237 uint64_t pasr_01:3;
2238 uint64_t asr_01:1;
2239 uint64_t srt_01:1;
2240 uint64_t rtt_wr_01:2;
2241 uint64_t dic_01:2;
2242 uint64_t rtt_nom_01:3;
2243 uint64_t pasr_10:3;
2244 uint64_t asr_10:1;
2245 uint64_t srt_10:1;
2246 uint64_t rtt_wr_10:2;
2247 uint64_t dic_10:2;
2248 uint64_t rtt_nom_10:3;
2249 uint64_t pasr_11:3;
2250 uint64_t asr_11:1;
2251 uint64_t srt_11:1;
2252 uint64_t rtt_wr_11:2;
2253 uint64_t dic_11:2;
2254 uint64_t rtt_nom_11:3;
2255 uint64_t reserved_48_63:16;
2256#endif
2257 } s;
2258 struct cvmx_lmcx_modereg_params1_s cn61xx;
2259 struct cvmx_lmcx_modereg_params1_s cn63xx;
2260 struct cvmx_lmcx_modereg_params1_s cn63xxp1;
2261 struct cvmx_lmcx_modereg_params1_s cn66xx;
2262 struct cvmx_lmcx_modereg_params1_s cn68xx;
2263 struct cvmx_lmcx_modereg_params1_s cn68xxp1;
2264 struct cvmx_lmcx_modereg_params1_s cnf71xx;
2265};
2266
2267union cvmx_lmcx_nxm {
2268 uint64_t u64;
2269 struct cvmx_lmcx_nxm_s {
2270#ifdef __BIG_ENDIAN_BITFIELD
2271 uint64_t reserved_40_63:24;
2272 uint64_t mem_msb_d3_r1:4;
2273 uint64_t mem_msb_d3_r0:4;
2274 uint64_t mem_msb_d2_r1:4;
2275 uint64_t mem_msb_d2_r0:4;
2276 uint64_t mem_msb_d1_r1:4;
2277 uint64_t mem_msb_d1_r0:4;
2278 uint64_t mem_msb_d0_r1:4;
2279 uint64_t mem_msb_d0_r0:4;
2280 uint64_t cs_mask:8;
2281#else
2282 uint64_t cs_mask:8;
2283 uint64_t mem_msb_d0_r0:4;
2284 uint64_t mem_msb_d0_r1:4;
2285 uint64_t mem_msb_d1_r0:4;
2286 uint64_t mem_msb_d1_r1:4;
2287 uint64_t mem_msb_d2_r0:4;
2288 uint64_t mem_msb_d2_r1:4;
2289 uint64_t mem_msb_d3_r0:4;
2290 uint64_t mem_msb_d3_r1:4;
2291 uint64_t reserved_40_63:24;
2292#endif
2293 } s;
2294 struct cvmx_lmcx_nxm_cn52xx {
2295#ifdef __BIG_ENDIAN_BITFIELD
2296 uint64_t reserved_8_63:56;
2297 uint64_t cs_mask:8;
2298#else
2299 uint64_t cs_mask:8;
2300 uint64_t reserved_8_63:56;
2301#endif
2302 } cn52xx;
2303 struct cvmx_lmcx_nxm_cn52xx cn56xx;
2304 struct cvmx_lmcx_nxm_cn52xx cn58xx;
2305 struct cvmx_lmcx_nxm_s cn61xx;
2306 struct cvmx_lmcx_nxm_s cn63xx;
2307 struct cvmx_lmcx_nxm_s cn63xxp1;
2308 struct cvmx_lmcx_nxm_s cn66xx;
2309 struct cvmx_lmcx_nxm_s cn68xx;
2310 struct cvmx_lmcx_nxm_s cn68xxp1;
2311 struct cvmx_lmcx_nxm_s cnf71xx;
2312};
2313
2314union cvmx_lmcx_ops_cnt {
2315 uint64_t u64;
2316 struct cvmx_lmcx_ops_cnt_s {
2317#ifdef __BIG_ENDIAN_BITFIELD
2318 uint64_t opscnt:64;
2319#else
2320 uint64_t opscnt:64;
2321#endif
2322 } s;
2323 struct cvmx_lmcx_ops_cnt_s cn61xx;
2324 struct cvmx_lmcx_ops_cnt_s cn63xx;
2325 struct cvmx_lmcx_ops_cnt_s cn63xxp1;
2326 struct cvmx_lmcx_ops_cnt_s cn66xx;
2327 struct cvmx_lmcx_ops_cnt_s cn68xx;
2328 struct cvmx_lmcx_ops_cnt_s cn68xxp1;
2329 struct cvmx_lmcx_ops_cnt_s cnf71xx;
2330};
2331
2332union cvmx_lmcx_ops_cnt_hi {
2333 uint64_t u64;
2334 struct cvmx_lmcx_ops_cnt_hi_s {
2335#ifdef __BIG_ENDIAN_BITFIELD
2336 uint64_t reserved_32_63:32;
2337 uint64_t opscnt_hi:32;
2338#else
2339 uint64_t opscnt_hi:32;
2340 uint64_t reserved_32_63:32;
2341#endif
2342 } s;
2343 struct cvmx_lmcx_ops_cnt_hi_s cn30xx;
2344 struct cvmx_lmcx_ops_cnt_hi_s cn31xx;
2345 struct cvmx_lmcx_ops_cnt_hi_s cn38xx;
2346 struct cvmx_lmcx_ops_cnt_hi_s cn38xxp2;
2347 struct cvmx_lmcx_ops_cnt_hi_s cn50xx;
2348 struct cvmx_lmcx_ops_cnt_hi_s cn52xx;
2349 struct cvmx_lmcx_ops_cnt_hi_s cn52xxp1;
2350 struct cvmx_lmcx_ops_cnt_hi_s cn56xx;
2351 struct cvmx_lmcx_ops_cnt_hi_s cn56xxp1;
2352 struct cvmx_lmcx_ops_cnt_hi_s cn58xx;
2353 struct cvmx_lmcx_ops_cnt_hi_s cn58xxp1;
2354};
2355
2356union cvmx_lmcx_ops_cnt_lo {
2357 uint64_t u64;
2358 struct cvmx_lmcx_ops_cnt_lo_s {
2359#ifdef __BIG_ENDIAN_BITFIELD
2360 uint64_t reserved_32_63:32;
2361 uint64_t opscnt_lo:32;
2362#else
2363 uint64_t opscnt_lo:32;
2364 uint64_t reserved_32_63:32;
2365#endif
2366 } s;
2367 struct cvmx_lmcx_ops_cnt_lo_s cn30xx;
2368 struct cvmx_lmcx_ops_cnt_lo_s cn31xx;
2369 struct cvmx_lmcx_ops_cnt_lo_s cn38xx;
2370 struct cvmx_lmcx_ops_cnt_lo_s cn38xxp2;
2371 struct cvmx_lmcx_ops_cnt_lo_s cn50xx;
2372 struct cvmx_lmcx_ops_cnt_lo_s cn52xx;
2373 struct cvmx_lmcx_ops_cnt_lo_s cn52xxp1;
2374 struct cvmx_lmcx_ops_cnt_lo_s cn56xx;
2375 struct cvmx_lmcx_ops_cnt_lo_s cn56xxp1;
2376 struct cvmx_lmcx_ops_cnt_lo_s cn58xx;
2377 struct cvmx_lmcx_ops_cnt_lo_s cn58xxp1;
2378};
2379
2380union cvmx_lmcx_phy_ctl {
2381 uint64_t u64;
2382 struct cvmx_lmcx_phy_ctl_s {
2383#ifdef __BIG_ENDIAN_BITFIELD
2384 uint64_t reserved_15_63:49;
2385 uint64_t rx_always_on:1;
2386 uint64_t lv_mode:1;
2387 uint64_t ck_tune1:1;
2388 uint64_t ck_dlyout1:4;
2389 uint64_t ck_tune0:1;
2390 uint64_t ck_dlyout0:4;
2391 uint64_t loopback:1;
2392 uint64_t loopback_pos:1;
2393 uint64_t ts_stagger:1;
2394#else
2395 uint64_t ts_stagger:1;
2396 uint64_t loopback_pos:1;
2397 uint64_t loopback:1;
2398 uint64_t ck_dlyout0:4;
2399 uint64_t ck_tune0:1;
2400 uint64_t ck_dlyout1:4;
2401 uint64_t ck_tune1:1;
2402 uint64_t lv_mode:1;
2403 uint64_t rx_always_on:1;
2404 uint64_t reserved_15_63:49;
2405#endif
2406 } s;
2407 struct cvmx_lmcx_phy_ctl_s cn61xx;
2408 struct cvmx_lmcx_phy_ctl_s cn63xx;
2409 struct cvmx_lmcx_phy_ctl_cn63xxp1 {
2410#ifdef __BIG_ENDIAN_BITFIELD
2411 uint64_t reserved_14_63:50;
2412 uint64_t lv_mode:1;
2413 uint64_t ck_tune1:1;
2414 uint64_t ck_dlyout1:4;
2415 uint64_t ck_tune0:1;
2416 uint64_t ck_dlyout0:4;
2417 uint64_t loopback:1;
2418 uint64_t loopback_pos:1;
2419 uint64_t ts_stagger:1;
2420#else
2421 uint64_t ts_stagger:1;
2422 uint64_t loopback_pos:1;
2423 uint64_t loopback:1;
2424 uint64_t ck_dlyout0:4;
2425 uint64_t ck_tune0:1;
2426 uint64_t ck_dlyout1:4;
2427 uint64_t ck_tune1:1;
2428 uint64_t lv_mode:1;
2429 uint64_t reserved_14_63:50;
2430#endif
2431 } cn63xxp1;
2432 struct cvmx_lmcx_phy_ctl_s cn66xx;
2433 struct cvmx_lmcx_phy_ctl_s cn68xx;
2434 struct cvmx_lmcx_phy_ctl_s cn68xxp1;
2435 struct cvmx_lmcx_phy_ctl_s cnf71xx;
2436};
2437
2438union cvmx_lmcx_pll_bwctl {
2439 uint64_t u64;
2440 struct cvmx_lmcx_pll_bwctl_s {
2441#ifdef __BIG_ENDIAN_BITFIELD
2442 uint64_t reserved_5_63:59;
2443 uint64_t bwupd:1;
2444 uint64_t bwctl:4;
2445#else
2446 uint64_t bwctl:4;
2447 uint64_t bwupd:1;
2448 uint64_t reserved_5_63:59;
2449#endif
2450 } s;
2451 struct cvmx_lmcx_pll_bwctl_s cn30xx;
2452 struct cvmx_lmcx_pll_bwctl_s cn31xx;
2453 struct cvmx_lmcx_pll_bwctl_s cn38xx;
2454 struct cvmx_lmcx_pll_bwctl_s cn38xxp2;
2455};
2456
2457union cvmx_lmcx_pll_ctl {
2458 uint64_t u64;
2459 struct cvmx_lmcx_pll_ctl_s {
2460#ifdef __BIG_ENDIAN_BITFIELD
2461 uint64_t reserved_30_63:34;
2462 uint64_t bypass:1;
2463 uint64_t fasten_n:1;
2464 uint64_t div_reset:1;
2465 uint64_t reset_n:1;
2466 uint64_t clkf:12;
2467 uint64_t clkr:6;
2468 uint64_t reserved_6_7:2;
2469 uint64_t en16:1;
2470 uint64_t en12:1;
2471 uint64_t en8:1;
2472 uint64_t en6:1;
2473 uint64_t en4:1;
2474 uint64_t en2:1;
2475#else
2476 uint64_t en2:1;
2477 uint64_t en4:1;
2478 uint64_t en6:1;
2479 uint64_t en8:1;
2480 uint64_t en12:1;
2481 uint64_t en16:1;
2482 uint64_t reserved_6_7:2;
2483 uint64_t clkr:6;
2484 uint64_t clkf:12;
2485 uint64_t reset_n:1;
2486 uint64_t div_reset:1;
2487 uint64_t fasten_n:1;
2488 uint64_t bypass:1;
2489 uint64_t reserved_30_63:34;
2490#endif
2491 } s;
2492 struct cvmx_lmcx_pll_ctl_cn50xx {
2493#ifdef __BIG_ENDIAN_BITFIELD
2494 uint64_t reserved_29_63:35;
2495 uint64_t fasten_n:1;
2496 uint64_t div_reset:1;
2497 uint64_t reset_n:1;
2498 uint64_t clkf:12;
2499 uint64_t clkr:6;
2500 uint64_t reserved_6_7:2;
2501 uint64_t en16:1;
2502 uint64_t en12:1;
2503 uint64_t en8:1;
2504 uint64_t en6:1;
2505 uint64_t en4:1;
2506 uint64_t en2:1;
2507#else
2508 uint64_t en2:1;
2509 uint64_t en4:1;
2510 uint64_t en6:1;
2511 uint64_t en8:1;
2512 uint64_t en12:1;
2513 uint64_t en16:1;
2514 uint64_t reserved_6_7:2;
2515 uint64_t clkr:6;
2516 uint64_t clkf:12;
2517 uint64_t reset_n:1;
2518 uint64_t div_reset:1;
2519 uint64_t fasten_n:1;
2520 uint64_t reserved_29_63:35;
2521#endif
2522 } cn50xx;
2523 struct cvmx_lmcx_pll_ctl_s cn52xx;
2524 struct cvmx_lmcx_pll_ctl_s cn52xxp1;
2525 struct cvmx_lmcx_pll_ctl_cn50xx cn56xx;
2526 struct cvmx_lmcx_pll_ctl_cn56xxp1 {
2527#ifdef __BIG_ENDIAN_BITFIELD
2528 uint64_t reserved_28_63:36;
2529 uint64_t div_reset:1;
2530 uint64_t reset_n:1;
2531 uint64_t clkf:12;
2532 uint64_t clkr:6;
2533 uint64_t reserved_6_7:2;
2534 uint64_t en16:1;
2535 uint64_t en12:1;
2536 uint64_t en8:1;
2537 uint64_t en6:1;
2538 uint64_t en4:1;
2539 uint64_t en2:1;
2540#else
2541 uint64_t en2:1;
2542 uint64_t en4:1;
2543 uint64_t en6:1;
2544 uint64_t en8:1;
2545 uint64_t en12:1;
2546 uint64_t en16:1;
2547 uint64_t reserved_6_7:2;
2548 uint64_t clkr:6;
2549 uint64_t clkf:12;
2550 uint64_t reset_n:1;
2551 uint64_t div_reset:1;
2552 uint64_t reserved_28_63:36;
2553#endif
2554 } cn56xxp1;
2555 struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xx;
2556 struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xxp1;
2557};
2558
2559union cvmx_lmcx_pll_status {
2560 uint64_t u64;
2561 struct cvmx_lmcx_pll_status_s {
2562#ifdef __BIG_ENDIAN_BITFIELD
2563 uint64_t reserved_32_63:32;
2564 uint64_t ddr__nctl:5;
2565 uint64_t ddr__pctl:5;
2566 uint64_t reserved_2_21:20;
2567 uint64_t rfslip:1;
2568 uint64_t fbslip:1;
2569#else
2570 uint64_t fbslip:1;
2571 uint64_t rfslip:1;
2572 uint64_t reserved_2_21:20;
2573 uint64_t ddr__pctl:5;
2574 uint64_t ddr__nctl:5;
2575 uint64_t reserved_32_63:32;
2576#endif
2577 } s;
2578 struct cvmx_lmcx_pll_status_s cn50xx;
2579 struct cvmx_lmcx_pll_status_s cn52xx;
2580 struct cvmx_lmcx_pll_status_s cn52xxp1;
2581 struct cvmx_lmcx_pll_status_s cn56xx;
2582 struct cvmx_lmcx_pll_status_s cn56xxp1;
2583 struct cvmx_lmcx_pll_status_s cn58xx;
2584 struct cvmx_lmcx_pll_status_cn58xxp1 {
2585#ifdef __BIG_ENDIAN_BITFIELD
2586 uint64_t reserved_2_63:62;
2587 uint64_t rfslip:1;
2588 uint64_t fbslip:1;
2589#else
2590 uint64_t fbslip:1;
2591 uint64_t rfslip:1;
2592 uint64_t reserved_2_63:62;
2593#endif
2594 } cn58xxp1;
2595};
2596
2597union cvmx_lmcx_read_level_ctl {
2598 uint64_t u64;
2599 struct cvmx_lmcx_read_level_ctl_s {
2600#ifdef __BIG_ENDIAN_BITFIELD
2601 uint64_t reserved_44_63:20;
2602 uint64_t rankmask:4;
2603 uint64_t pattern:8;
2604 uint64_t row:16;
2605 uint64_t col:12;
2606 uint64_t reserved_3_3:1;
2607 uint64_t bnk:3;
2608#else
2609 uint64_t bnk:3;
2610 uint64_t reserved_3_3:1;
2611 uint64_t col:12;
2612 uint64_t row:16;
2613 uint64_t pattern:8;
2614 uint64_t rankmask:4;
2615 uint64_t reserved_44_63:20;
2616#endif
2617 } s;
2618 struct cvmx_lmcx_read_level_ctl_s cn52xx;
2619 struct cvmx_lmcx_read_level_ctl_s cn52xxp1;
2620 struct cvmx_lmcx_read_level_ctl_s cn56xx;
2621 struct cvmx_lmcx_read_level_ctl_s cn56xxp1;
2622};
2623
2624union cvmx_lmcx_read_level_dbg {
2625 uint64_t u64;
2626 struct cvmx_lmcx_read_level_dbg_s {
2627#ifdef __BIG_ENDIAN_BITFIELD
2628 uint64_t reserved_32_63:32;
2629 uint64_t bitmask:16;
2630 uint64_t reserved_4_15:12;
2631 uint64_t byte:4;
2632#else
2633 uint64_t byte:4;
2634 uint64_t reserved_4_15:12;
2635 uint64_t bitmask:16;
2636 uint64_t reserved_32_63:32;
2637#endif
2638 } s;
2639 struct cvmx_lmcx_read_level_dbg_s cn52xx;
2640 struct cvmx_lmcx_read_level_dbg_s cn52xxp1;
2641 struct cvmx_lmcx_read_level_dbg_s cn56xx;
2642 struct cvmx_lmcx_read_level_dbg_s cn56xxp1;
2643};
2644
2645union cvmx_lmcx_read_level_rankx {
2646 uint64_t u64;
2647 struct cvmx_lmcx_read_level_rankx_s {
2648#ifdef __BIG_ENDIAN_BITFIELD
2649 uint64_t reserved_38_63:26;
2650 uint64_t status:2;
2651 uint64_t byte8:4;
2652 uint64_t byte7:4;
2653 uint64_t byte6:4;
2654 uint64_t byte5:4;
2655 uint64_t byte4:4;
2656 uint64_t byte3:4;
2657 uint64_t byte2:4;
2658 uint64_t byte1:4;
2659 uint64_t byte0:4;
2660#else
2661 uint64_t byte0:4;
2662 uint64_t byte1:4;
2663 uint64_t byte2:4;
2664 uint64_t byte3:4;
2665 uint64_t byte4:4;
2666 uint64_t byte5:4;
2667 uint64_t byte6:4;
2668 uint64_t byte7:4;
2669 uint64_t byte8:4;
2670 uint64_t status:2;
2671 uint64_t reserved_38_63:26;
2672#endif
2673 } s;
2674 struct cvmx_lmcx_read_level_rankx_s cn52xx;
2675 struct cvmx_lmcx_read_level_rankx_s cn52xxp1;
2676 struct cvmx_lmcx_read_level_rankx_s cn56xx;
2677 struct cvmx_lmcx_read_level_rankx_s cn56xxp1;
2678};
2679
2680union cvmx_lmcx_reset_ctl {
2681 uint64_t u64;
2682 struct cvmx_lmcx_reset_ctl_s {
2683#ifdef __BIG_ENDIAN_BITFIELD
2684 uint64_t reserved_4_63:60;
2685 uint64_t ddr3psv:1;
2686 uint64_t ddr3psoft:1;
2687 uint64_t ddr3pwarm:1;
2688 uint64_t ddr3rst:1;
2689#else
2690 uint64_t ddr3rst:1;
2691 uint64_t ddr3pwarm:1;
2692 uint64_t ddr3psoft:1;
2693 uint64_t ddr3psv:1;
2694 uint64_t reserved_4_63:60;
2695#endif
2696 } s;
2697 struct cvmx_lmcx_reset_ctl_s cn61xx;
2698 struct cvmx_lmcx_reset_ctl_s cn63xx;
2699 struct cvmx_lmcx_reset_ctl_s cn63xxp1;
2700 struct cvmx_lmcx_reset_ctl_s cn66xx;
2701 struct cvmx_lmcx_reset_ctl_s cn68xx;
2702 struct cvmx_lmcx_reset_ctl_s cn68xxp1;
2703 struct cvmx_lmcx_reset_ctl_s cnf71xx;
2704};
2705
2706union cvmx_lmcx_rlevel_ctl {
2707 uint64_t u64;
2708 struct cvmx_lmcx_rlevel_ctl_s {
2709#ifdef __BIG_ENDIAN_BITFIELD
2710 uint64_t reserved_22_63:42;
2711 uint64_t delay_unload_3:1;
2712 uint64_t delay_unload_2:1;
2713 uint64_t delay_unload_1:1;
2714 uint64_t delay_unload_0:1;
2715 uint64_t bitmask:8;
2716 uint64_t or_dis:1;
2717 uint64_t offset_en:1;
2718 uint64_t offset:4;
2719 uint64_t byte:4;
2720#else
2721 uint64_t byte:4;
2722 uint64_t offset:4;
2723 uint64_t offset_en:1;
2724 uint64_t or_dis:1;
2725 uint64_t bitmask:8;
2726 uint64_t delay_unload_0:1;
2727 uint64_t delay_unload_1:1;
2728 uint64_t delay_unload_2:1;
2729 uint64_t delay_unload_3:1;
2730 uint64_t reserved_22_63:42;
2731#endif
2732 } s;
2733 struct cvmx_lmcx_rlevel_ctl_s cn61xx;
2734 struct cvmx_lmcx_rlevel_ctl_s cn63xx;
2735 struct cvmx_lmcx_rlevel_ctl_cn63xxp1 {
2736#ifdef __BIG_ENDIAN_BITFIELD
2737 uint64_t reserved_9_63:55;
2738 uint64_t offset_en:1;
2739 uint64_t offset:4;
2740 uint64_t byte:4;
2741#else
2742 uint64_t byte:4;
2743 uint64_t offset:4;
2744 uint64_t offset_en:1;
2745 uint64_t reserved_9_63:55;
2746#endif
2747 } cn63xxp1;
2748 struct cvmx_lmcx_rlevel_ctl_s cn66xx;
2749 struct cvmx_lmcx_rlevel_ctl_s cn68xx;
2750 struct cvmx_lmcx_rlevel_ctl_s cn68xxp1;
2751 struct cvmx_lmcx_rlevel_ctl_s cnf71xx;
2752};
2753
2754union cvmx_lmcx_rlevel_dbg {
2755 uint64_t u64;
2756 struct cvmx_lmcx_rlevel_dbg_s {
2757#ifdef __BIG_ENDIAN_BITFIELD
2758 uint64_t bitmask:64;
2759#else
2760 uint64_t bitmask:64;
2761#endif
2762 } s;
2763 struct cvmx_lmcx_rlevel_dbg_s cn61xx;
2764 struct cvmx_lmcx_rlevel_dbg_s cn63xx;
2765 struct cvmx_lmcx_rlevel_dbg_s cn63xxp1;
2766 struct cvmx_lmcx_rlevel_dbg_s cn66xx;
2767 struct cvmx_lmcx_rlevel_dbg_s cn68xx;
2768 struct cvmx_lmcx_rlevel_dbg_s cn68xxp1;
2769 struct cvmx_lmcx_rlevel_dbg_s cnf71xx;
2770};
2771
2772union cvmx_lmcx_rlevel_rankx {
2773 uint64_t u64;
2774 struct cvmx_lmcx_rlevel_rankx_s {
2775#ifdef __BIG_ENDIAN_BITFIELD
2776 uint64_t reserved_56_63:8;
2777 uint64_t status:2;
2778 uint64_t byte8:6;
2779 uint64_t byte7:6;
2780 uint64_t byte6:6;
2781 uint64_t byte5:6;
2782 uint64_t byte4:6;
2783 uint64_t byte3:6;
2784 uint64_t byte2:6;
2785 uint64_t byte1:6;
2786 uint64_t byte0:6;
2787#else
2788 uint64_t byte0:6;
2789 uint64_t byte1:6;
2790 uint64_t byte2:6;
2791 uint64_t byte3:6;
2792 uint64_t byte4:6;
2793 uint64_t byte5:6;
2794 uint64_t byte6:6;
2795 uint64_t byte7:6;
2796 uint64_t byte8:6;
2797 uint64_t status:2;
2798 uint64_t reserved_56_63:8;
2799#endif
2800 } s;
2801 struct cvmx_lmcx_rlevel_rankx_s cn61xx;
2802 struct cvmx_lmcx_rlevel_rankx_s cn63xx;
2803 struct cvmx_lmcx_rlevel_rankx_s cn63xxp1;
2804 struct cvmx_lmcx_rlevel_rankx_s cn66xx;
2805 struct cvmx_lmcx_rlevel_rankx_s cn68xx;
2806 struct cvmx_lmcx_rlevel_rankx_s cn68xxp1;
2807 struct cvmx_lmcx_rlevel_rankx_s cnf71xx;
2808};
2809
2810union cvmx_lmcx_rodt_comp_ctl {
2811 uint64_t u64;
2812 struct cvmx_lmcx_rodt_comp_ctl_s {
2813#ifdef __BIG_ENDIAN_BITFIELD
2814 uint64_t reserved_17_63:47;
2815 uint64_t enable:1;
2816 uint64_t reserved_12_15:4;
2817 uint64_t nctl:4;
2818 uint64_t reserved_5_7:3;
2819 uint64_t pctl:5;
2820#else
2821 uint64_t pctl:5;
2822 uint64_t reserved_5_7:3;
2823 uint64_t nctl:4;
2824 uint64_t reserved_12_15:4;
2825 uint64_t enable:1;
2826 uint64_t reserved_17_63:47;
2827#endif
2828 } s;
2829 struct cvmx_lmcx_rodt_comp_ctl_s cn50xx;
2830 struct cvmx_lmcx_rodt_comp_ctl_s cn52xx;
2831 struct cvmx_lmcx_rodt_comp_ctl_s cn52xxp1;
2832 struct cvmx_lmcx_rodt_comp_ctl_s cn56xx;
2833 struct cvmx_lmcx_rodt_comp_ctl_s cn56xxp1;
2834 struct cvmx_lmcx_rodt_comp_ctl_s cn58xx;
2835 struct cvmx_lmcx_rodt_comp_ctl_s cn58xxp1;
2836};
2837
2838union cvmx_lmcx_rodt_ctl {
2839 uint64_t u64;
2840 struct cvmx_lmcx_rodt_ctl_s {
2841#ifdef __BIG_ENDIAN_BITFIELD
2842 uint64_t reserved_32_63:32;
2843 uint64_t rodt_hi3:4;
2844 uint64_t rodt_hi2:4;
2845 uint64_t rodt_hi1:4;
2846 uint64_t rodt_hi0:4;
2847 uint64_t rodt_lo3:4;
2848 uint64_t rodt_lo2:4;
2849 uint64_t rodt_lo1:4;
2850 uint64_t rodt_lo0:4;
2851#else
2852 uint64_t rodt_lo0:4;
2853 uint64_t rodt_lo1:4;
2854 uint64_t rodt_lo2:4;
2855 uint64_t rodt_lo3:4;
2856 uint64_t rodt_hi0:4;
2857 uint64_t rodt_hi1:4;
2858 uint64_t rodt_hi2:4;
2859 uint64_t rodt_hi3:4;
2860 uint64_t reserved_32_63:32;
2861#endif
2862 } s;
2863 struct cvmx_lmcx_rodt_ctl_s cn30xx;
2864 struct cvmx_lmcx_rodt_ctl_s cn31xx;
2865 struct cvmx_lmcx_rodt_ctl_s cn38xx;
2866 struct cvmx_lmcx_rodt_ctl_s cn38xxp2;
2867 struct cvmx_lmcx_rodt_ctl_s cn50xx;
2868 struct cvmx_lmcx_rodt_ctl_s cn52xx;
2869 struct cvmx_lmcx_rodt_ctl_s cn52xxp1;
2870 struct cvmx_lmcx_rodt_ctl_s cn56xx;
2871 struct cvmx_lmcx_rodt_ctl_s cn56xxp1;
2872 struct cvmx_lmcx_rodt_ctl_s cn58xx;
2873 struct cvmx_lmcx_rodt_ctl_s cn58xxp1;
2874};
2875
2876union cvmx_lmcx_rodt_mask {
2877 uint64_t u64;
2878 struct cvmx_lmcx_rodt_mask_s {
2879#ifdef __BIG_ENDIAN_BITFIELD
2880 uint64_t rodt_d3_r1:8;
2881 uint64_t rodt_d3_r0:8;
2882 uint64_t rodt_d2_r1:8;
2883 uint64_t rodt_d2_r0:8;
2884 uint64_t rodt_d1_r1:8;
2885 uint64_t rodt_d1_r0:8;
2886 uint64_t rodt_d0_r1:8;
2887 uint64_t rodt_d0_r0:8;
2888#else
2889 uint64_t rodt_d0_r0:8;
2890 uint64_t rodt_d0_r1:8;
2891 uint64_t rodt_d1_r0:8;
2892 uint64_t rodt_d1_r1:8;
2893 uint64_t rodt_d2_r0:8;
2894 uint64_t rodt_d2_r1:8;
2895 uint64_t rodt_d3_r0:8;
2896 uint64_t rodt_d3_r1:8;
2897#endif
2898 } s;
2899 struct cvmx_lmcx_rodt_mask_s cn61xx;
2900 struct cvmx_lmcx_rodt_mask_s cn63xx;
2901 struct cvmx_lmcx_rodt_mask_s cn63xxp1;
2902 struct cvmx_lmcx_rodt_mask_s cn66xx;
2903 struct cvmx_lmcx_rodt_mask_s cn68xx;
2904 struct cvmx_lmcx_rodt_mask_s cn68xxp1;
2905 struct cvmx_lmcx_rodt_mask_s cnf71xx;
2906};
2907
2908union cvmx_lmcx_scramble_cfg0 {
2909 uint64_t u64;
2910 struct cvmx_lmcx_scramble_cfg0_s {
2911#ifdef __BIG_ENDIAN_BITFIELD
2912 uint64_t key:64;
2913#else
2914 uint64_t key:64;
2915#endif
2916 } s;
2917 struct cvmx_lmcx_scramble_cfg0_s cn61xx;
2918 struct cvmx_lmcx_scramble_cfg0_s cn66xx;
2919 struct cvmx_lmcx_scramble_cfg0_s cnf71xx;
2920};
2921
2922union cvmx_lmcx_scramble_cfg1 {
2923 uint64_t u64;
2924 struct cvmx_lmcx_scramble_cfg1_s {
2925#ifdef __BIG_ENDIAN_BITFIELD
2926 uint64_t key:64;
2927#else
2928 uint64_t key:64;
2929#endif
2930 } s;
2931 struct cvmx_lmcx_scramble_cfg1_s cn61xx;
2932 struct cvmx_lmcx_scramble_cfg1_s cn66xx;
2933 struct cvmx_lmcx_scramble_cfg1_s cnf71xx;
2934};
2935
2936union cvmx_lmcx_scrambled_fadr {
2937 uint64_t u64;
2938 struct cvmx_lmcx_scrambled_fadr_s {
2939#ifdef __BIG_ENDIAN_BITFIELD
2940 uint64_t reserved_36_63:28;
2941 uint64_t fdimm:2;
2942 uint64_t fbunk:1;
2943 uint64_t fbank:3;
2944 uint64_t frow:16;
2945 uint64_t fcol:14;
2946#else
2947 uint64_t fcol:14;
2948 uint64_t frow:16;
2949 uint64_t fbank:3;
2950 uint64_t fbunk:1;
2951 uint64_t fdimm:2;
2952 uint64_t reserved_36_63:28;
2953#endif
2954 } s;
2955 struct cvmx_lmcx_scrambled_fadr_s cn61xx;
2956 struct cvmx_lmcx_scrambled_fadr_s cn66xx;
2957 struct cvmx_lmcx_scrambled_fadr_s cnf71xx;
2958};
2959
2960union cvmx_lmcx_slot_ctl0 {
2961 uint64_t u64;
2962 struct cvmx_lmcx_slot_ctl0_s {
2963#ifdef __BIG_ENDIAN_BITFIELD
2964 uint64_t reserved_24_63:40;
2965 uint64_t w2w_init:6;
2966 uint64_t w2r_init:6;
2967 uint64_t r2w_init:6;
2968 uint64_t r2r_init:6;
2969#else
2970 uint64_t r2r_init:6;
2971 uint64_t r2w_init:6;
2972 uint64_t w2r_init:6;
2973 uint64_t w2w_init:6;
2974 uint64_t reserved_24_63:40;
2975#endif
2976 } s;
2977 struct cvmx_lmcx_slot_ctl0_s cn61xx;
2978 struct cvmx_lmcx_slot_ctl0_s cn63xx;
2979 struct cvmx_lmcx_slot_ctl0_s cn63xxp1;
2980 struct cvmx_lmcx_slot_ctl0_s cn66xx;
2981 struct cvmx_lmcx_slot_ctl0_s cn68xx;
2982 struct cvmx_lmcx_slot_ctl0_s cn68xxp1;
2983 struct cvmx_lmcx_slot_ctl0_s cnf71xx;
2984};
2985
2986union cvmx_lmcx_slot_ctl1 {
2987 uint64_t u64;
2988 struct cvmx_lmcx_slot_ctl1_s {
2989#ifdef __BIG_ENDIAN_BITFIELD
2990 uint64_t reserved_24_63:40;
2991 uint64_t w2w_xrank_init:6;
2992 uint64_t w2r_xrank_init:6;
2993 uint64_t r2w_xrank_init:6;
2994 uint64_t r2r_xrank_init:6;
2995#else
2996 uint64_t r2r_xrank_init:6;
2997 uint64_t r2w_xrank_init:6;
2998 uint64_t w2r_xrank_init:6;
2999 uint64_t w2w_xrank_init:6;
3000 uint64_t reserved_24_63:40;
3001#endif
3002 } s;
3003 struct cvmx_lmcx_slot_ctl1_s cn61xx;
3004 struct cvmx_lmcx_slot_ctl1_s cn63xx;
3005 struct cvmx_lmcx_slot_ctl1_s cn63xxp1;
3006 struct cvmx_lmcx_slot_ctl1_s cn66xx;
3007 struct cvmx_lmcx_slot_ctl1_s cn68xx;
3008 struct cvmx_lmcx_slot_ctl1_s cn68xxp1;
3009 struct cvmx_lmcx_slot_ctl1_s cnf71xx;
3010};
3011
3012union cvmx_lmcx_slot_ctl2 {
3013 uint64_t u64;
3014 struct cvmx_lmcx_slot_ctl2_s {
3015#ifdef __BIG_ENDIAN_BITFIELD
3016 uint64_t reserved_24_63:40;
3017 uint64_t w2w_xdimm_init:6;
3018 uint64_t w2r_xdimm_init:6;
3019 uint64_t r2w_xdimm_init:6;
3020 uint64_t r2r_xdimm_init:6;
3021#else
3022 uint64_t r2r_xdimm_init:6;
3023 uint64_t r2w_xdimm_init:6;
3024 uint64_t w2r_xdimm_init:6;
3025 uint64_t w2w_xdimm_init:6;
3026 uint64_t reserved_24_63:40;
3027#endif
3028 } s;
3029 struct cvmx_lmcx_slot_ctl2_s cn61xx;
3030 struct cvmx_lmcx_slot_ctl2_s cn63xx;
3031 struct cvmx_lmcx_slot_ctl2_s cn63xxp1;
3032 struct cvmx_lmcx_slot_ctl2_s cn66xx;
3033 struct cvmx_lmcx_slot_ctl2_s cn68xx;
3034 struct cvmx_lmcx_slot_ctl2_s cn68xxp1;
3035 struct cvmx_lmcx_slot_ctl2_s cnf71xx;
3036};
3037
3038union cvmx_lmcx_timing_params0 {
3039 uint64_t u64;
3040 struct cvmx_lmcx_timing_params0_s {
3041#ifdef __BIG_ENDIAN_BITFIELD
3042 uint64_t reserved_47_63:17;
3043 uint64_t trp_ext:1;
3044 uint64_t tcksre:4;
3045 uint64_t trp:4;
3046 uint64_t tzqinit:4;
3047 uint64_t tdllk:4;
3048 uint64_t tmod:4;
3049 uint64_t tmrd:4;
3050 uint64_t txpr:4;
3051 uint64_t tcke:4;
3052 uint64_t tzqcs:4;
3053 uint64_t tckeon:10;
3054#else
3055 uint64_t tckeon:10;
3056 uint64_t tzqcs:4;
3057 uint64_t tcke:4;
3058 uint64_t txpr:4;
3059 uint64_t tmrd:4;
3060 uint64_t tmod:4;
3061 uint64_t tdllk:4;
3062 uint64_t tzqinit:4;
3063 uint64_t trp:4;
3064 uint64_t tcksre:4;
3065 uint64_t trp_ext:1;
3066 uint64_t reserved_47_63:17;
3067#endif
3068 } s;
3069 struct cvmx_lmcx_timing_params0_cn61xx {
3070#ifdef __BIG_ENDIAN_BITFIELD
3071 uint64_t reserved_47_63:17;
3072 uint64_t trp_ext:1;
3073 uint64_t tcksre:4;
3074 uint64_t trp:4;
3075 uint64_t tzqinit:4;
3076 uint64_t tdllk:4;
3077 uint64_t tmod:4;
3078 uint64_t tmrd:4;
3079 uint64_t txpr:4;
3080 uint64_t tcke:4;
3081 uint64_t tzqcs:4;
3082 uint64_t reserved_0_9:10;
3083#else
3084 uint64_t reserved_0_9:10;
3085 uint64_t tzqcs:4;
3086 uint64_t tcke:4;
3087 uint64_t txpr:4;
3088 uint64_t tmrd:4;
3089 uint64_t tmod:4;
3090 uint64_t tdllk:4;
3091 uint64_t tzqinit:4;
3092 uint64_t trp:4;
3093 uint64_t tcksre:4;
3094 uint64_t trp_ext:1;
3095 uint64_t reserved_47_63:17;
3096#endif
3097 } cn61xx;
3098 struct cvmx_lmcx_timing_params0_cn61xx cn63xx;
3099 struct cvmx_lmcx_timing_params0_cn63xxp1 {
3100#ifdef __BIG_ENDIAN_BITFIELD
3101 uint64_t reserved_46_63:18;
3102 uint64_t tcksre:4;
3103 uint64_t trp:4;
3104 uint64_t tzqinit:4;
3105 uint64_t tdllk:4;
3106 uint64_t tmod:4;
3107 uint64_t tmrd:4;
3108 uint64_t txpr:4;
3109 uint64_t tcke:4;
3110 uint64_t tzqcs:4;
3111 uint64_t tckeon:10;
3112#else
3113 uint64_t tckeon:10;
3114 uint64_t tzqcs:4;
3115 uint64_t tcke:4;
3116 uint64_t txpr:4;
3117 uint64_t tmrd:4;
3118 uint64_t tmod:4;
3119 uint64_t tdllk:4;
3120 uint64_t tzqinit:4;
3121 uint64_t trp:4;
3122 uint64_t tcksre:4;
3123 uint64_t reserved_46_63:18;
3124#endif
3125 } cn63xxp1;
3126 struct cvmx_lmcx_timing_params0_cn61xx cn66xx;
3127 struct cvmx_lmcx_timing_params0_cn61xx cn68xx;
3128 struct cvmx_lmcx_timing_params0_cn61xx cn68xxp1;
3129 struct cvmx_lmcx_timing_params0_cn61xx cnf71xx;
3130};
3131
3132union cvmx_lmcx_timing_params1 {
3133 uint64_t u64;
3134 struct cvmx_lmcx_timing_params1_s {
3135#ifdef __BIG_ENDIAN_BITFIELD
3136 uint64_t reserved_47_63:17;
3137 uint64_t tras_ext:1;
3138 uint64_t txpdll:5;
3139 uint64_t tfaw:5;
3140 uint64_t twldqsen:4;
3141 uint64_t twlmrd:4;
3142 uint64_t txp:3;
3143 uint64_t trrd:3;
3144 uint64_t trfc:5;
3145 uint64_t twtr:4;
3146 uint64_t trcd:4;
3147 uint64_t tras:5;
3148 uint64_t tmprr:4;
3149#else
3150 uint64_t tmprr:4;
3151 uint64_t tras:5;
3152 uint64_t trcd:4;
3153 uint64_t twtr:4;
3154 uint64_t trfc:5;
3155 uint64_t trrd:3;
3156 uint64_t txp:3;
3157 uint64_t twlmrd:4;
3158 uint64_t twldqsen:4;
3159 uint64_t tfaw:5;
3160 uint64_t txpdll:5;
3161 uint64_t tras_ext:1;
3162 uint64_t reserved_47_63:17;
3163#endif
3164 } s;
3165 struct cvmx_lmcx_timing_params1_s cn61xx;
3166 struct cvmx_lmcx_timing_params1_s cn63xx;
3167 struct cvmx_lmcx_timing_params1_cn63xxp1 {
3168#ifdef __BIG_ENDIAN_BITFIELD
3169 uint64_t reserved_46_63:18;
3170 uint64_t txpdll:5;
3171 uint64_t tfaw:5;
3172 uint64_t twldqsen:4;
3173 uint64_t twlmrd:4;
3174 uint64_t txp:3;
3175 uint64_t trrd:3;
3176 uint64_t trfc:5;
3177 uint64_t twtr:4;
3178 uint64_t trcd:4;
3179 uint64_t tras:5;
3180 uint64_t tmprr:4;
3181#else
3182 uint64_t tmprr:4;
3183 uint64_t tras:5;
3184 uint64_t trcd:4;
3185 uint64_t twtr:4;
3186 uint64_t trfc:5;
3187 uint64_t trrd:3;
3188 uint64_t txp:3;
3189 uint64_t twlmrd:4;
3190 uint64_t twldqsen:4;
3191 uint64_t tfaw:5;
3192 uint64_t txpdll:5;
3193 uint64_t reserved_46_63:18;
3194#endif
3195 } cn63xxp1;
3196 struct cvmx_lmcx_timing_params1_s cn66xx;
3197 struct cvmx_lmcx_timing_params1_s cn68xx;
3198 struct cvmx_lmcx_timing_params1_s cn68xxp1;
3199 struct cvmx_lmcx_timing_params1_s cnf71xx;
3200};
3201
3202union cvmx_lmcx_tro_ctl {
3203 uint64_t u64;
3204 struct cvmx_lmcx_tro_ctl_s {
3205#ifdef __BIG_ENDIAN_BITFIELD
3206 uint64_t reserved_33_63:31;
3207 uint64_t rclk_cnt:32;
3208 uint64_t treset:1;
3209#else
3210 uint64_t treset:1;
3211 uint64_t rclk_cnt:32;
3212 uint64_t reserved_33_63:31;
3213#endif
3214 } s;
3215 struct cvmx_lmcx_tro_ctl_s cn61xx;
3216 struct cvmx_lmcx_tro_ctl_s cn63xx;
3217 struct cvmx_lmcx_tro_ctl_s cn63xxp1;
3218 struct cvmx_lmcx_tro_ctl_s cn66xx;
3219 struct cvmx_lmcx_tro_ctl_s cn68xx;
3220 struct cvmx_lmcx_tro_ctl_s cn68xxp1;
3221 struct cvmx_lmcx_tro_ctl_s cnf71xx;
3222};
3223
3224union cvmx_lmcx_tro_stat {
3225 uint64_t u64;
3226 struct cvmx_lmcx_tro_stat_s {
3227#ifdef __BIG_ENDIAN_BITFIELD
3228 uint64_t reserved_32_63:32;
3229 uint64_t ring_cnt:32;
3230#else
3231 uint64_t ring_cnt:32;
3232 uint64_t reserved_32_63:32;
3233#endif
3234 } s;
3235 struct cvmx_lmcx_tro_stat_s cn61xx;
3236 struct cvmx_lmcx_tro_stat_s cn63xx;
3237 struct cvmx_lmcx_tro_stat_s cn63xxp1;
3238 struct cvmx_lmcx_tro_stat_s cn66xx;
3239 struct cvmx_lmcx_tro_stat_s cn68xx;
3240 struct cvmx_lmcx_tro_stat_s cn68xxp1;
3241 struct cvmx_lmcx_tro_stat_s cnf71xx;
3242};
3243
3244union cvmx_lmcx_wlevel_ctl {
3245 uint64_t u64;
3246 struct cvmx_lmcx_wlevel_ctl_s {
3247#ifdef __BIG_ENDIAN_BITFIELD
3248 uint64_t reserved_22_63:42;
3249 uint64_t rtt_nom:3;
3250 uint64_t bitmask:8;
3251 uint64_t or_dis:1;
3252 uint64_t sset:1;
3253 uint64_t lanemask:9;
3254#else
3255 uint64_t lanemask:9;
3256 uint64_t sset:1;
3257 uint64_t or_dis:1;
3258 uint64_t bitmask:8;
3259 uint64_t rtt_nom:3;
3260 uint64_t reserved_22_63:42;
3261#endif
3262 } s;
3263 struct cvmx_lmcx_wlevel_ctl_s cn61xx;
3264 struct cvmx_lmcx_wlevel_ctl_s cn63xx;
3265 struct cvmx_lmcx_wlevel_ctl_cn63xxp1 {
3266#ifdef __BIG_ENDIAN_BITFIELD
3267 uint64_t reserved_10_63:54;
3268 uint64_t sset:1;
3269 uint64_t lanemask:9;
3270#else
3271 uint64_t lanemask:9;
3272 uint64_t sset:1;
3273 uint64_t reserved_10_63:54;
3274#endif
3275 } cn63xxp1;
3276 struct cvmx_lmcx_wlevel_ctl_s cn66xx;
3277 struct cvmx_lmcx_wlevel_ctl_s cn68xx;
3278 struct cvmx_lmcx_wlevel_ctl_s cn68xxp1;
3279 struct cvmx_lmcx_wlevel_ctl_s cnf71xx;
3280};
3281
3282union cvmx_lmcx_wlevel_dbg {
3283 uint64_t u64;
3284 struct cvmx_lmcx_wlevel_dbg_s {
3285#ifdef __BIG_ENDIAN_BITFIELD
3286 uint64_t reserved_12_63:52;
3287 uint64_t bitmask:8;
3288 uint64_t byte:4;
3289#else
3290 uint64_t byte:4;
3291 uint64_t bitmask:8;
3292 uint64_t reserved_12_63:52;
3293#endif
3294 } s;
3295 struct cvmx_lmcx_wlevel_dbg_s cn61xx;
3296 struct cvmx_lmcx_wlevel_dbg_s cn63xx;
3297 struct cvmx_lmcx_wlevel_dbg_s cn63xxp1;
3298 struct cvmx_lmcx_wlevel_dbg_s cn66xx;
3299 struct cvmx_lmcx_wlevel_dbg_s cn68xx;
3300 struct cvmx_lmcx_wlevel_dbg_s cn68xxp1;
3301 struct cvmx_lmcx_wlevel_dbg_s cnf71xx;
3302};
3303
3304union cvmx_lmcx_wlevel_rankx {
3305 uint64_t u64;
3306 struct cvmx_lmcx_wlevel_rankx_s {
3307#ifdef __BIG_ENDIAN_BITFIELD
3308 uint64_t reserved_47_63:17;
3309 uint64_t status:2;
3310 uint64_t byte8:5;
3311 uint64_t byte7:5;
3312 uint64_t byte6:5;
3313 uint64_t byte5:5;
3314 uint64_t byte4:5;
3315 uint64_t byte3:5;
3316 uint64_t byte2:5;
3317 uint64_t byte1:5;
3318 uint64_t byte0:5;
3319#else
3320 uint64_t byte0:5;
3321 uint64_t byte1:5;
3322 uint64_t byte2:5;
3323 uint64_t byte3:5;
3324 uint64_t byte4:5;
3325 uint64_t byte5:5;
3326 uint64_t byte6:5;
3327 uint64_t byte7:5;
3328 uint64_t byte8:5;
3329 uint64_t status:2;
3330 uint64_t reserved_47_63:17;
3331#endif
3332 } s;
3333 struct cvmx_lmcx_wlevel_rankx_s cn61xx;
3334 struct cvmx_lmcx_wlevel_rankx_s cn63xx;
3335 struct cvmx_lmcx_wlevel_rankx_s cn63xxp1;
3336 struct cvmx_lmcx_wlevel_rankx_s cn66xx;
3337 struct cvmx_lmcx_wlevel_rankx_s cn68xx;
3338 struct cvmx_lmcx_wlevel_rankx_s cn68xxp1;
3339 struct cvmx_lmcx_wlevel_rankx_s cnf71xx;
3340};
3341
3342union cvmx_lmcx_wodt_ctl0 {
3343 uint64_t u64;
3344 struct cvmx_lmcx_wodt_ctl0_s {
3345#ifdef __BIG_ENDIAN_BITFIELD
3346 uint64_t reserved_0_63:64;
3347#else
3348 uint64_t reserved_0_63:64;
3349#endif
3350 } s;
3351 struct cvmx_lmcx_wodt_ctl0_cn30xx {
3352#ifdef __BIG_ENDIAN_BITFIELD
3353 uint64_t reserved_32_63:32;
3354 uint64_t wodt_d1_r1:8;
3355 uint64_t wodt_d1_r0:8;
3356 uint64_t wodt_d0_r1:8;
3357 uint64_t wodt_d0_r0:8;
3358#else
3359 uint64_t wodt_d0_r0:8;
3360 uint64_t wodt_d0_r1:8;
3361 uint64_t wodt_d1_r0:8;
3362 uint64_t wodt_d1_r1:8;
3363 uint64_t reserved_32_63:32;
3364#endif
3365 } cn30xx;
3366 struct cvmx_lmcx_wodt_ctl0_cn30xx cn31xx;
3367 struct cvmx_lmcx_wodt_ctl0_cn38xx {
3368#ifdef __BIG_ENDIAN_BITFIELD
3369 uint64_t reserved_32_63:32;
3370 uint64_t wodt_hi3:4;
3371 uint64_t wodt_hi2:4;
3372 uint64_t wodt_hi1:4;
3373 uint64_t wodt_hi0:4;
3374 uint64_t wodt_lo3:4;
3375 uint64_t wodt_lo2:4;
3376 uint64_t wodt_lo1:4;
3377 uint64_t wodt_lo0:4;
3378#else
3379 uint64_t wodt_lo0:4;
3380 uint64_t wodt_lo1:4;
3381 uint64_t wodt_lo2:4;
3382 uint64_t wodt_lo3:4;
3383 uint64_t wodt_hi0:4;
3384 uint64_t wodt_hi1:4;
3385 uint64_t wodt_hi2:4;
3386 uint64_t wodt_hi3:4;
3387 uint64_t reserved_32_63:32;
3388#endif
3389 } cn38xx;
3390 struct cvmx_lmcx_wodt_ctl0_cn38xx cn38xxp2;
3391 struct cvmx_lmcx_wodt_ctl0_cn38xx cn50xx;
3392 struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xx;
3393 struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xxp1;
3394 struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xx;
3395 struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xxp1;
3396 struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xx;
3397 struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xxp1;
3398};
3399
3400union cvmx_lmcx_wodt_ctl1 {
3401 uint64_t u64;
3402 struct cvmx_lmcx_wodt_ctl1_s {
3403#ifdef __BIG_ENDIAN_BITFIELD
3404 uint64_t reserved_32_63:32;
3405 uint64_t wodt_d3_r1:8;
3406 uint64_t wodt_d3_r0:8;
3407 uint64_t wodt_d2_r1:8;
3408 uint64_t wodt_d2_r0:8;
3409#else
3410 uint64_t wodt_d2_r0:8;
3411 uint64_t wodt_d2_r1:8;
3412 uint64_t wodt_d3_r0:8;
3413 uint64_t wodt_d3_r1:8;
3414 uint64_t reserved_32_63:32;
3415#endif
3416 } s;
3417 struct cvmx_lmcx_wodt_ctl1_s cn30xx;
3418 struct cvmx_lmcx_wodt_ctl1_s cn31xx;
3419 struct cvmx_lmcx_wodt_ctl1_s cn52xx;
3420 struct cvmx_lmcx_wodt_ctl1_s cn52xxp1;
3421 struct cvmx_lmcx_wodt_ctl1_s cn56xx;
3422 struct cvmx_lmcx_wodt_ctl1_s cn56xxp1;
3423};
3424
3425union cvmx_lmcx_wodt_mask {
3426 uint64_t u64;
3427 struct cvmx_lmcx_wodt_mask_s {
3428#ifdef __BIG_ENDIAN_BITFIELD
3429 uint64_t wodt_d3_r1:8;
3430 uint64_t wodt_d3_r0:8;
3431 uint64_t wodt_d2_r1:8;
3432 uint64_t wodt_d2_r0:8;
3433 uint64_t wodt_d1_r1:8;
3434 uint64_t wodt_d1_r0:8;
3435 uint64_t wodt_d0_r1:8;
3436 uint64_t wodt_d0_r0:8;
3437#else
3438 uint64_t wodt_d0_r0:8;
3439 uint64_t wodt_d0_r1:8;
3440 uint64_t wodt_d1_r0:8;
3441 uint64_t wodt_d1_r1:8;
3442 uint64_t wodt_d2_r0:8;
3443 uint64_t wodt_d2_r1:8;
3444 uint64_t wodt_d3_r0:8;
3445 uint64_t wodt_d3_r1:8;
3446#endif
3447 } s;
3448 struct cvmx_lmcx_wodt_mask_s cn61xx;
3449 struct cvmx_lmcx_wodt_mask_s cn63xx;
3450 struct cvmx_lmcx_wodt_mask_s cn63xxp1;
3451 struct cvmx_lmcx_wodt_mask_s cn66xx;
3452 struct cvmx_lmcx_wodt_mask_s cn68xx;
3453 struct cvmx_lmcx_wodt_mask_s cn68xxp1;
3454 struct cvmx_lmcx_wodt_mask_s cnf71xx;
3455};
3456
3457#endif
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 14dd11f4492a..349bb2ba840c 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -218,6 +218,12 @@
218#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) 218#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
219#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) 219#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
220 220
221/* These are used to cover entire families of OCTEON processors */
222#define OCTEON_FAM_1 (OCTEON_CN3XXX)
223#define OCTEON_FAM_PLUS (OCTEON_CN5XXX)
224#define OCTEON_FAM_1_PLUS (OCTEON_FAM_PLUS | OM_MATCH_PREVIOUS_MODELS)
225#define OCTEON_FAM_2 (OCTEON_CN6XXX)
226
221/* The revision byte (low byte) has two different encodings. 227/* The revision byte (low byte) has two different encodings.
222 * CN3XXX: 228 * CN3XXX:
223 * 229 *
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 790939dd8244..254e9954ed71 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -209,13 +209,6 @@ union octeon_cvmemctl {
209 } s; 209 } s;
210}; 210};
211 211
212struct octeon_cf_data {
213 unsigned long base_region_bias;
214 unsigned int base_region; /* The chip select region used by CF */
215 int is16bit; /* 0 - 8bit, !0 - 16bit */
216 int dma_engine; /* -1 for no DMA */
217};
218
219extern void octeon_write_lcd(const char *s); 212extern void octeon_write_lcd(const char *s);
220extern void octeon_check_cpu_bist(void); 213extern void octeon_check_cpu_bist(void);
221extern int octeon_get_boot_debug_flag(void); 214extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index da9bd7d270d1..dbaec94046da 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -31,21 +31,19 @@
31#define PAGE_SHIFT 16 31#define PAGE_SHIFT 16
32#endif 32#endif
33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
34#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 34#define PAGE_MASK (~(PAGE_SIZE - 1))
35 35
36#ifdef CONFIG_HUGETLB_PAGE 36#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) 37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT) 38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
39#define HPAGE_MASK (~(HPAGE_SIZE - 1)) 39#define HPAGE_MASK (~(HPAGE_SIZE - 1))
40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
41#else /* !CONFIG_HUGETLB_PAGE */ 41#else /* !CONFIG_MIPS_HUGE_TLB_SUPPORT */
42#define HPAGE_SHIFT ({BUILD_BUG(); 0; }) 42#define HPAGE_SHIFT ({BUILD_BUG(); 0; })
43#define HPAGE_SIZE ({BUILD_BUG(); 0; }) 43#define HPAGE_SIZE ({BUILD_BUG(); 0; })
44#define HPAGE_MASK ({BUILD_BUG(); 0; }) 44#define HPAGE_MASK ({BUILD_BUG(); 0; })
45#define HUGETLB_PAGE_ORDER ({BUILD_BUG(); 0; }) 45#define HUGETLB_PAGE_ORDER ({BUILD_BUG(); 0; })
46#endif /* CONFIG_HUGETLB_PAGE */ 46#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
47
48#ifndef __ASSEMBLY__
49 47
50#include <linux/pfn.h> 48#include <linux/pfn.h>
51#include <asm/io.h> 49#include <asm/io.h>
@@ -139,8 +137,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
139 */ 137 */
140#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t))) 138#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
141 139
142#endif /* !__ASSEMBLY__ */
143
144/* 140/*
145 * __pa()/__va() should be used only during mem init. 141 * __pa()/__va() should be used only during mem init.
146 */ 142 */
@@ -202,7 +198,10 @@ typedef struct { unsigned long pgprot; } pgprot_t;
202#endif 198#endif
203 199
204#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr))) 200#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
205#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys(kaddr))) 201
202extern int __virt_addr_valid(const volatile void *kaddr);
203#define virt_addr_valid(kaddr) \
204 __virt_addr_valid((const volatile void *) (kaddr))
206 205
207#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 206#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
208 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 207 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 90bf3b3fce19..d69ea743272b 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -145,7 +145,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
145extern char * (*pcibios_plat_setup)(char *str); 145extern char * (*pcibios_plat_setup)(char *str);
146 146
147/* this function parses memory ranges from a device node */ 147/* this function parses memory ranges from a device node */
148extern void __devinit pci_load_of_ranges(struct pci_controller *hose, 148extern void pci_load_of_ranges(struct pci_controller *hose,
149 struct device_node *node); 149 struct device_node *node);
150 150
151#endif /* _ASM_PCI_H */ 151#endif /* _ASM_PCI_H */
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index f5b521d5a67d..c63191055e69 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -175,7 +175,7 @@ static inline int pmd_none(pmd_t pmd)
175 175
176static inline int pmd_bad(pmd_t pmd) 176static inline int pmd_bad(pmd_t pmd)
177{ 177{
178#ifdef CONFIG_HUGETLB_PAGE 178#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
179 /* pmd_huge(pmd) but inline */ 179 /* pmd_huge(pmd) but inline */
180 if (unlikely(pmd_val(pmd) & _PAGE_HUGE)) 180 if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
181 return 0; 181 return 0;
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index da4ba49adcf6..f6a0439a4085 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -34,38 +34,72 @@
34 */ 34 */
35#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 35#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
36 36
37#define _PAGE_PRESENT (1<<6) /* implemented in software */ 37/*
38#define _PAGE_READ (1<<7) /* implemented in software */ 38 * The following bits are directly used by the TLB hardware
39#define _PAGE_WRITE (1<<8) /* implemented in software */ 39 */
40#define _PAGE_ACCESSED (1<<9) /* implemented in software */ 40#define _PAGE_R4KBUG (1 << 0) /* workaround for r4k bug */
41#define _PAGE_MODIFIED (1<<10) /* implemented in software */ 41#define _PAGE_GLOBAL (1 << 0)
42#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */ 42#define _PAGE_VALID_SHIFT 1
43 43#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
44#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */ 44#define _PAGE_SILENT_READ (1 << 1) /* synonym */
45#define _PAGE_GLOBAL (1<<0) 45#define _PAGE_DIRTY_SHIFT 2
46#define _PAGE_VALID (1<<1) 46#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */
47#define _PAGE_SILENT_READ (1<<1) /* synonym */ 47#define _PAGE_SILENT_WRITE (1 << 2)
48#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */ 48#define _CACHE_SHIFT 3
49#define _PAGE_SILENT_WRITE (1<<2) 49#define _CACHE_MASK (7 << 3)
50#define _CACHE_SHIFT 3 50
51#define _CACHE_MASK (7<<3) 51/*
52 * The following bits are implemented in software
53 *
54 * _PAGE_FILE semantics: set:pagecache unset:swap
55 */
56#define _PAGE_PRESENT_SHIFT 6
57#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
58#define _PAGE_READ_SHIFT 7
59#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
60#define _PAGE_WRITE_SHIFT 8
61#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
62#define _PAGE_ACCESSED_SHIFT 9
63#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
64#define _PAGE_MODIFIED_SHIFT 10
65#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
66
67#define _PAGE_FILE (1 << 10)
52 68
53#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 69#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
54 70
55#define _PAGE_PRESENT (1<<0) /* implemented in software */ 71/*
56#define _PAGE_READ (1<<1) /* implemented in software */ 72 * The following are implemented by software
57#define _PAGE_WRITE (1<<2) /* implemented in software */ 73 *
58#define _PAGE_ACCESSED (1<<3) /* implemented in software */ 74 * _PAGE_FILE semantics: set:pagecache unset:swap
59#define _PAGE_MODIFIED (1<<4) /* implemented in software */ 75 */
60#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ 76#define _PAGE_PRESENT_SHIFT 0
61 77#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
62#define _PAGE_GLOBAL (1<<8) 78#define _PAGE_READ_SHIFT 1
63#define _PAGE_VALID (1<<9) 79#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
64#define _PAGE_SILENT_READ (1<<9) /* synonym */ 80#define _PAGE_WRITE_SHIFT 2
65#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ 81#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
66#define _PAGE_SILENT_WRITE (1<<10) 82#define _PAGE_ACCESSED_SHIFT 3
67#define _CACHE_UNCACHED (1<<11) 83#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
68#define _CACHE_MASK (1<<11) 84#define _PAGE_MODIFIED_SHIFT 4
85#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
86#define _PAGE_FILE_SHIFT 4
87#define _PAGE_FILE (1 << _PAGE_FILE_SHIFT)
88
89/*
90 * And these are the hardware TLB bits
91 */
92#define _PAGE_GLOBAL_SHIFT 8
93#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
94#define _PAGE_VALID_SHIFT 9
95#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
96#define _PAGE_SILENT_READ (1 << _PAGE_VALID_SHIFT) /* synonym */
97#define _PAGE_DIRTY_SHIFT 10
98#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
99#define _PAGE_SILENT_WRITE (1 << _PAGE_DIRTY_SHIFT)
100#define _CACHE_UNCACHED_SHIFT 11
101#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
102#define _CACHE_MASK (1 << _CACHE_UNCACHED_SHIFT)
69 103
70#else /* 'Normal' r4K case */ 104#else /* 'Normal' r4K case */
71/* 105/*
@@ -76,25 +110,25 @@
76 * which is more than we need right now. 110 * which is more than we need right now.
77 */ 111 */
78 112
79/* implemented in software */ 113/*
114 * The following bits are implemented in software
115 *
116 * _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi.
117 * _PAGE_FILE semantics: set:pagecache unset:swap
118 */
80#define _PAGE_PRESENT_SHIFT (0) 119#define _PAGE_PRESENT_SHIFT (0)
81#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 120#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
82/* implemented in software, should be unused if cpu_has_rixi. */
83#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) 121#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
84#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) 122#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
85/* implemented in software */
86#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 123#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
87#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 124#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
88/* implemented in software */
89#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 125#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
90#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 126#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
91/* implemented in software */
92#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 127#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
93#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 128#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
94/* set:pagecache unset:swap */
95#define _PAGE_FILE (_PAGE_MODIFIED) 129#define _PAGE_FILE (_PAGE_MODIFIED)
96 130
97#ifdef CONFIG_HUGETLB_PAGE 131#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
98/* huge tlb page */ 132/* huge tlb page */
99#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 133#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
100#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 134#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
@@ -103,8 +137,17 @@
103#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ 137#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
104#endif 138#endif
105 139
140#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
141/* huge tlb page */
142#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
143#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
144#else
145#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT)
146#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */
147#endif
148
106/* Page cannot be executed */ 149/* Page cannot be executed */
107#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) 150#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT)
108#define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; }) 151#define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })
109 152
110/* Page cannot be read */ 153/* Page cannot be read */
@@ -192,20 +235,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
192#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 235#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
193#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 236#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
194 237
195#elif defined(CONFIG_CPU_RM9000)
196
197#define _CACHE_WT (0<<_CACHE_SHIFT)
198#define _CACHE_WTWA (1<<_CACHE_SHIFT)
199#define _CACHE_UC_B (2<<_CACHE_SHIFT)
200#define _CACHE_WB (3<<_CACHE_SHIFT)
201#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
202#define _CACHE_CWB (5<<_CACHE_SHIFT)
203#define _CACHE_UCNB (6<<_CACHE_SHIFT)
204#define _CACHE_FPC (7<<_CACHE_SHIFT)
205
206#define _CACHE_UNCACHED _CACHE_UC_B
207#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
208
209#else 238#else
210 239
211#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ 240#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index c02158be836c..ec50d52cfb74 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -8,6 +8,7 @@
8#ifndef _ASM_PGTABLE_H 8#ifndef _ASM_PGTABLE_H
9#define _ASM_PGTABLE_H 9#define _ASM_PGTABLE_H
10 10
11#include <linux/mmzone.h>
11#ifdef CONFIG_32BIT 12#ifdef CONFIG_32BIT
12#include <asm/pgtable-32.h> 13#include <asm/pgtable-32.h>
13#endif 14#endif
@@ -76,16 +77,7 @@ extern unsigned long zero_page_mask;
76 77
77#define ZERO_PAGE(vaddr) \ 78#define ZERO_PAGE(vaddr) \
78 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))) 79 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
79 80#define __HAVE_COLOR_ZERO_PAGE
80#define is_zero_pfn is_zero_pfn
81static inline int is_zero_pfn(unsigned long pfn)
82{
83 extern unsigned long zero_pfn;
84 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
85 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
86}
87
88#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
89 81
90extern void paging_init(void); 82extern void paging_init(void);
91 83
@@ -94,7 +86,12 @@ extern void paging_init(void);
94 * and a page entry and page directory to the page they refer to. 86 * and a page entry and page directory to the page they refer to.
95 */ 87 */
96#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd)) 88#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd))
97#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 89
90#define __pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
91#ifndef CONFIG_TRANSPARENT_HUGEPAGE
92#define pmd_page(pmd) __pmd_page(pmd)
93#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
94
98#define pmd_page_vaddr(pmd) pmd_val(pmd) 95#define pmd_page_vaddr(pmd) pmd_val(pmd)
99 96
100#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 97#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
@@ -107,7 +104,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
107 ptep->pte_high = pte.pte_high; 104 ptep->pte_high = pte.pte_high;
108 smp_wmb(); 105 smp_wmb();
109 ptep->pte_low = pte.pte_low; 106 ptep->pte_low = pte.pte_low;
110 //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
111 107
112 if (pte.pte_low & _PAGE_GLOBAL) { 108 if (pte.pte_low & _PAGE_GLOBAL) {
113 pte_t *buddy = ptep_buddy(ptep); 109 pte_t *buddy = ptep_buddy(ptep);
@@ -375,6 +371,14 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
375 __update_cache(vma, address, pte); 371 __update_cache(vma, address, pte);
376} 372}
377 373
374static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
375 unsigned long address, pmd_t *pmdp)
376{
377 pte_t pte = *(pte_t *)pmdp;
378
379 __update_tlb(vma, address, pte);
380}
381
378#define kern_addr_valid(addr) (1) 382#define kern_addr_valid(addr) (1)
379 383
380#ifdef CONFIG_64BIT_PHYS_ADDR 384#ifdef CONFIG_64BIT_PHYS_ADDR
@@ -394,6 +398,157 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
394 remap_pfn_range(vma, vaddr, pfn, size, prot) 398 remap_pfn_range(vma, vaddr, pfn, size, prot)
395#endif 399#endif
396 400
401#ifdef CONFIG_TRANSPARENT_HUGEPAGE
402
403extern int has_transparent_hugepage(void);
404
405static inline int pmd_trans_huge(pmd_t pmd)
406{
407 return !!(pmd_val(pmd) & _PAGE_HUGE);
408}
409
410static inline pmd_t pmd_mkhuge(pmd_t pmd)
411{
412 pmd_val(pmd) |= _PAGE_HUGE;
413
414 return pmd;
415}
416
417static inline int pmd_trans_splitting(pmd_t pmd)
418{
419 return !!(pmd_val(pmd) & _PAGE_SPLITTING);
420}
421
422static inline pmd_t pmd_mksplitting(pmd_t pmd)
423{
424 pmd_val(pmd) |= _PAGE_SPLITTING;
425
426 return pmd;
427}
428
429extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
430 pmd_t *pmdp, pmd_t pmd);
431
432#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
433/* Extern to avoid header file madness */
434extern void pmdp_splitting_flush(struct vm_area_struct *vma,
435 unsigned long address,
436 pmd_t *pmdp);
437
438#define __HAVE_ARCH_PMD_WRITE
439static inline int pmd_write(pmd_t pmd)
440{
441 return !!(pmd_val(pmd) & _PAGE_WRITE);
442}
443
444static inline pmd_t pmd_wrprotect(pmd_t pmd)
445{
446 pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
447 return pmd;
448}
449
450static inline pmd_t pmd_mkwrite(pmd_t pmd)
451{
452 pmd_val(pmd) |= _PAGE_WRITE;
453 if (pmd_val(pmd) & _PAGE_MODIFIED)
454 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
455
456 return pmd;
457}
458
459static inline int pmd_dirty(pmd_t pmd)
460{
461 return !!(pmd_val(pmd) & _PAGE_MODIFIED);
462}
463
464static inline pmd_t pmd_mkclean(pmd_t pmd)
465{
466 pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
467 return pmd;
468}
469
470static inline pmd_t pmd_mkdirty(pmd_t pmd)
471{
472 pmd_val(pmd) |= _PAGE_MODIFIED;
473 if (pmd_val(pmd) & _PAGE_WRITE)
474 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
475
476 return pmd;
477}
478
479static inline int pmd_young(pmd_t pmd)
480{
481 return !!(pmd_val(pmd) & _PAGE_ACCESSED);
482}
483
484static inline pmd_t pmd_mkold(pmd_t pmd)
485{
486 pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
487
488 return pmd;
489}
490
491static inline pmd_t pmd_mkyoung(pmd_t pmd)
492{
493 pmd_val(pmd) |= _PAGE_ACCESSED;
494
495 if (cpu_has_rixi) {
496 if (!(pmd_val(pmd) & _PAGE_NO_READ))
497 pmd_val(pmd) |= _PAGE_SILENT_READ;
498 } else {
499 if (pmd_val(pmd) & _PAGE_READ)
500 pmd_val(pmd) |= _PAGE_SILENT_READ;
501 }
502
503 return pmd;
504}
505
506/* Extern to avoid header file madness */
507extern pmd_t mk_pmd(struct page *page, pgprot_t prot);
508
509static inline unsigned long pmd_pfn(pmd_t pmd)
510{
511 return pmd_val(pmd) >> _PFN_SHIFT;
512}
513
514static inline struct page *pmd_page(pmd_t pmd)
515{
516 if (pmd_trans_huge(pmd))
517 return pfn_to_page(pmd_pfn(pmd));
518
519 return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
520}
521
522static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
523{
524 pmd_val(pmd) = (pmd_val(pmd) & _PAGE_CHG_MASK) | pgprot_val(newprot);
525 return pmd;
526}
527
528static inline pmd_t pmd_mknotpresent(pmd_t pmd)
529{
530 pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
531
532 return pmd;
533}
534
535/*
536 * The generic version pmdp_get_and_clear uses a version of pmd_clear() with a
537 * different prototype.
538 */
539#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
540static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
541 unsigned long address, pmd_t *pmdp)
542{
543 pmd_t old = *pmdp;
544
545 pmd_clear(pmdp);
546
547 return old;
548}
549
550#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
551
397#include <asm-generic/pgtable.h> 552#include <asm-generic/pgtable.h>
398 553
399/* 554/*
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
index 9e2ee429c529..c74eb1657f5f 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ 22#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 5e33fabe354d..bd98b503f04c 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -226,8 +226,6 @@ struct thread_struct {
226 unsigned long cp0_badvaddr; /* Last user fault */ 226 unsigned long cp0_badvaddr; /* Last user fault */
227 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 227 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
228 unsigned long error_code; 228 unsigned long error_code;
229 unsigned long irix_trampoline; /* Wheee... */
230 unsigned long irix_oldctx;
231#ifdef CONFIG_CPU_CAVIUM_OCTEON 229#ifdef CONFIG_CPU_CAVIUM_OCTEON
232 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 230 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
233 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 231 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
@@ -297,8 +295,6 @@ struct thread_struct {
297 .cp0_badvaddr = 0, \ 295 .cp0_badvaddr = 0, \
298 .cp0_baduaddr = 0, \ 296 .cp0_baduaddr = 0, \
299 .error_code = 0, \ 297 .error_code = 0, \
300 .irix_trampoline = 0, \
301 .irix_oldctx = 0, \
302 /* \ 298 /* \
303 * Cavium Octeon specifics (null if not Octeon) \ 299 * Cavium Octeon specifics (null if not Octeon) \
304 */ \ 300 */ \
@@ -310,8 +306,6 @@ struct task_struct;
310/* Free all resources held by a thread. */ 306/* Free all resources held by a thread. */
311#define release_thread(thread) do { } while(0) 307#define release_thread(thread) do { } while(0)
312 308
313extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
314
315extern unsigned long thread_saved_pc(struct task_struct *tsk); 309extern unsigned long thread_saved_pc(struct task_struct *tsk);
316 310
317/* 311/*
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 4f5da948a777..a3186f2bb8a0 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -49,6 +49,7 @@ static inline long regs_return_value(struct pt_regs *regs)
49 49
50#define instruction_pointer(regs) ((regs)->cp0_epc) 50#define instruction_pointer(regs) ((regs)->cp0_epc)
51#define profile_pc(regs) instruction_pointer(regs) 51#define profile_pc(regs) instruction_pointer(regs)
52#define user_stack_pointer(r) ((r)->regs[29])
52 53
53extern asmlinkage void syscall_trace_enter(struct pt_regs *regs); 54extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
54extern asmlinkage void syscall_trace_leave(struct pt_regs *regs); 55extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
@@ -61,4 +62,10 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs)
61 die(str, regs); 62 die(str, regs);
62} 63}
63 64
65#define current_pt_regs() \
66({ \
67 unsigned long sp = (unsigned long)__builtin_frame_address(0); \
68 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \
69})
70
64#endif /* _ASM_PTRACE_H */ 71#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h
index 149342951436..3dce7c788b3e 100644
--- a/arch/mips/include/asm/sgiarcs.h
+++ b/arch/mips/include/asm/sgiarcs.h
@@ -366,7 +366,7 @@ struct linux_smonblock {
366 * Macros for calling a 32-bit ARC implementation from 64-bit code 366 * Macros for calling a 32-bit ARC implementation from 64-bit code
367 */ 367 */
368 368
369#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32) 369#if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
370 370
371#define __arc_clobbers \ 371#define __arc_clobbers \
372 "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \ 372 "$2", "$3" /* ... */, "$8", "$9", "$10", "$11", \
@@ -475,10 +475,10 @@ struct linux_smonblock {
475 __res; \ 475 __res; \
476}) 476})
477 477
478#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */ 478#endif /* defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32) */
479 479
480#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) || \ 480#if (defined(CONFIG_32BIT) && defined(CONFIG_FW_ARC32)) || \
481 (defined(CONFIG_64BIT) && defined(CONFIG_ARC64)) 481 (defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC64))
482 482
483#define ARC_CALL0(dest) \ 483#define ARC_CALL0(dest) \
484({ long __res; \ 484({ long __res; \
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index 880240dff8b7..cf4a08062d1d 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -21,6 +21,4 @@
21#include <asm/sigcontext.h> 21#include <asm/sigcontext.h>
22#include <asm/siginfo.h> 22#include <asm/siginfo.h>
23 23
24#define ptrace_signal_deliver(regs, cookie) do { } while (0)
25
26#endif /* _ASM_SIGNAL_H */ 24#endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index d4fb4d852a6d..f33b5fd6972b 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -40,6 +40,8 @@ extern int __cpu_logical_map[NR_CPUS];
40#define SMP_CALL_FUNCTION 0x2 40#define SMP_CALL_FUNCTION 0x2
41/* Octeon - Tell another core to flush its icache */ 41/* Octeon - Tell another core to flush its icache */
42#define SMP_ICACHE_FLUSH 0x4 42#define SMP_ICACHE_FLUSH 0x4
43/* Used by kexec crashdump to save all cpu's state */
44#define SMP_DUMP 0x8
43 45
44extern volatile cpumask_t cpu_callin_map; 46extern volatile cpumask_t cpu_callin_map;
45 47
@@ -91,4 +93,8 @@ static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
91 mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); 93 mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
92} 94}
93 95
96#if defined(CONFIG_KEXEC)
97extern void (*dump_ipi_function_ptr)(void *);
98void dump_send_ipi(void (*dump_ipi_callback)(void *));
99#endif
94#endif /* __ASM_SMP_H */ 100#endif /* __ASM_SMP_H */
diff --git a/arch/mips/include/asm/smvp.h b/arch/mips/include/asm/smvp.h
deleted file mode 100644
index 0d0e80a39e8a..000000000000
--- a/arch/mips/include/asm/smvp.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _ASM_SMVP_H
2#define _ASM_SMVP_H
3
4/*
5 * Definitions for SMVP multitasking on MIPS MT cores
6 */
7struct task_struct;
8
9extern void smvp_smp_setup(void);
10extern void smvp_smp_finish(void);
11extern void smvp_boot_secondary(int cpu, struct task_struct *t);
12extern void smvp_init_secondary(void);
13extern void smvp_smp_finish(void);
14extern void smvp_cpus_done(void);
15extern void smvp_prepare_cpus(unsigned int max_cpus);
16
17/* This is platform specific */
18extern void smvp_send_ipi(int cpu, unsigned int action);
19#endif /* _ASM_SMVP_H */
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 4461198361c9..65900dab3ad3 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -6,7 +6,7 @@
6 * SECTION_SIZE_BITS 2^N: how big each section will be 6 * SECTION_SIZE_BITS 2^N: how big each section will be
7 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space 7 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
8 */ 8 */
9#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PAGE_SIZE_64KB) 9#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)
10# define SECTION_SIZE_BITS 29 10# define SECTION_SIZE_BITS 29
11#else 11#else
12# define SECTION_SIZE_BITS 28 12# define SECTION_SIZE_BITS 28
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 8debe9e91754..b2050b9e64b1 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -29,10 +29,11 @@ struct thread_info {
29 __u32 cpu; /* current CPU */ 29 __u32 cpu; /* current CPU */
30 int preempt_count; /* 0 => preemptable, <0 => BUG */ 30 int preempt_count; /* 0 => preemptable, <0 => BUG */
31 31
32 mm_segment_t addr_limit; /* thread address space: 32 mm_segment_t addr_limit; /*
33 0-0xBFFFFFFF for user-thead 33 * thread address space limit:
34 0-0xFFFFFFFF for kernel-thread 34 * 0x7fffffff for user-thead
35 */ 35 * 0xffffffff for kernel-thread
36 */
36 struct restart_block restart_block; 37 struct restart_block restart_block;
37 struct pt_regs *regs; 38 struct pt_regs *regs;
38}; 39};
@@ -112,12 +113,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
112#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 113#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
113#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 114#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
114 115
115#ifdef CONFIG_MIPS32_O32
116#define TIF_32BIT TIF_32BIT_REGS
117#elif defined(CONFIG_MIPS32_N32)
118#define TIF_32BIT _TIF_32BIT_ADDR
119#endif /* CONFIG_MIPS32_O32 */
120
121#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 116#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
122#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 117#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
123#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 118#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index bc14447e69b5..761f2e92119e 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -50,10 +50,8 @@ extern int (*perf_irq)(void);
50/* 50/*
51 * Initialize the calling CPU's compare interrupt as clockevent device 51 * Initialize the calling CPU's compare interrupt as clockevent device
52 */ 52 */
53#ifdef CONFIG_CEVT_R4K_LIB
54extern unsigned int __weak get_c0_compare_int(void); 53extern unsigned int __weak get_c0_compare_int(void);
55extern int r4k_clockevent_init(void); 54extern int r4k_clockevent_init(void);
56#endif
57 55
58static inline int mips_clockevent_init(void) 56static inline int mips_clockevent_init(void)
59{ 57{
@@ -71,7 +69,7 @@ static inline int mips_clockevent_init(void)
71/* 69/*
72 * Initialize the count register as a clocksource 70 * Initialize the count register as a clocksource
73 */ 71 */
74#ifdef CONFIG_CSRC_R4K_LIB 72#ifdef CONFIG_CSRC_R4K
75extern int init_r4k_clocksource(void); 73extern int init_r4k_clocksource(void);
76#endif 74#endif
77 75
diff --git a/arch/mips/include/asm/titan_dep.h b/arch/mips/include/asm/titan_dep.h
deleted file mode 100644
index fee1908c65d2..000000000000
--- a/arch/mips/include/asm/titan_dep.h
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * Board specific definititions for the PMC-Sierra Yosemite
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __TITAN_DEP_H__
14#define __TITAN_DEP_H__
15
16#include <asm/addrspace.h> /* for KSEG1ADDR() */
17#include <asm/byteorder.h> /* for cpu_to_le32() */
18
19#define TITAN_READ(ofs) \
20 (*(volatile u32 *)(ocd_base+(ofs)))
21#define TITAN_READ_16(ofs) \
22 (*(volatile u16 *)(ocd_base+(ofs)))
23#define TITAN_READ_8(ofs) \
24 (*(volatile u8 *)(ocd_base+(ofs)))
25
26#define TITAN_WRITE(ofs, data) \
27 do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
28#define TITAN_WRITE_16(ofs, data) \
29 do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
30#define TITAN_WRITE_8(ofs, data) \
31 do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
32
33/*
34 * PCI specific defines
35 */
36#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
37#define TITAN_PCI_0_CONFIG_DATA 0x784
38
39/*
40 * HT specific defines
41 */
42#define RM9000x2_HTLINK_REG 0xbb000644
43#define RM9000x2_BASE_ADDR 0xbb000000
44
45#define OCD_BASE 0xfb000000UL
46#define OCD_SIZE 0x3000UL
47
48extern unsigned long ocd_base;
49
50/*
51 * OCD Registers
52 */
53#define RM9000x2_OCD_LKB5 0x0128 /* Ethernet */
54#define RM9000x2_OCD_LKM5 0x012c
55
56#define RM9000x2_OCD_LKB7 0x0138 /* HT Region 0 */
57#define RM9000x2_OCD_LKM7 0x013c
58#define RM9000x2_OCD_LKB8 0x0140 /* HT Region 1 */
59#define RM9000x2_OCD_LKM8 0x0144
60
61#define RM9000x2_OCD_LKB9 0x0148 /* Local Bus */
62#define RM9000x2_OCD_LKM9 0x014c
63#define RM9000x2_OCD_LKB10 0x0150
64#define RM9000x2_OCD_LKM10 0x0154
65#define RM9000x2_OCD_LKB11 0x0158
66#define RM9000x2_OCD_LKM11 0x015c
67#define RM9000x2_OCD_LKB12 0x0160
68#define RM9000x2_OCD_LKM12 0x0164
69
70#define RM9000x2_OCD_LKB13 0x0168 /* Scratch RAM */
71#define RM9000x2_OCD_LKM13 0x016c
72
73#define RM9000x2_OCD_LPD0 0x0200 /* Local Bus */
74#define RM9000x2_OCD_LPD1 0x0210
75#define RM9000x2_OCD_LPD2 0x0220
76#define RM9000x2_OCD_LPD3 0x0230
77
78#define RM9000x2_OCD_HTDVID 0x0600 /* HT Device Header */
79#define RM9000x2_OCD_HTSC 0x0604
80#define RM9000x2_OCD_HTCCR 0x0608
81#define RM9000x2_OCD_HTBHL 0x060c
82#define RM9000x2_OCD_HTBAR0 0x0610
83#define RM9000x2_OCD_HTBAR1 0x0614
84#define RM9000x2_OCD_HTBAR2 0x0618
85#define RM9000x2_OCD_HTBAR3 0x061c
86#define RM9000x2_OCD_HTBAR4 0x0620
87#define RM9000x2_OCD_HTBAR5 0x0624
88#define RM9000x2_OCD_HTCBCPT 0x0628
89#define RM9000x2_OCD_HTSDVID 0x062c
90#define RM9000x2_OCD_HTXRA 0x0630
91#define RM9000x2_OCD_HTCAP1 0x0634
92#define RM9000x2_OCD_HTIL 0x063c
93
94#define RM9000x2_OCD_HTLCC 0x0640 /* HT Capability Block */
95#define RM9000x2_OCD_HTLINK 0x0644
96#define RM9000x2_OCD_HTFQREV 0x0648
97
98#define RM9000x2_OCD_HTERCTL 0x0668 /* HT Controller */
99#define RM9000x2_OCD_HTRXDB 0x066c
100#define RM9000x2_OCD_HTIMPED 0x0670
101#define RM9000x2_OCD_HTSWIMP 0x0674
102#define RM9000x2_OCD_HTCAL 0x0678
103
104#define RM9000x2_OCD_HTBAA30 0x0680
105#define RM9000x2_OCD_HTBAA54 0x0684
106#define RM9000x2_OCD_HTMASK0 0x0688
107#define RM9000x2_OCD_HTMASK1 0x068c
108#define RM9000x2_OCD_HTMASK2 0x0690
109#define RM9000x2_OCD_HTMASK3 0x0694
110#define RM9000x2_OCD_HTMASK4 0x0698
111#define RM9000x2_OCD_HTMASK5 0x069c
112
113#define RM9000x2_OCD_HTIFCTL 0x06a0
114#define RM9000x2_OCD_HTPLL 0x06a4
115
116#define RM9000x2_OCD_HTSRI 0x06b0
117#define RM9000x2_OCD_HTRXNUM 0x06b4
118#define RM9000x2_OCD_HTTXNUM 0x06b8
119
120#define RM9000x2_OCD_HTTXCNT 0x06c8
121
122#define RM9000x2_OCD_HTERROR 0x06d8
123#define RM9000x2_OCD_HTRCRCE 0x06dc
124#define RM9000x2_OCD_HTEOI 0x06e0
125
126#define RM9000x2_OCD_CRCR 0x06f0
127
128#define RM9000x2_OCD_HTCFGA 0x06f8
129#define RM9000x2_OCD_HTCFGD 0x06fc
130
131#define RM9000x2_OCD_INTMSG 0x0a00
132
133#define RM9000x2_OCD_INTPIN0 0x0a40
134#define RM9000x2_OCD_INTPIN1 0x0a44
135#define RM9000x2_OCD_INTPIN2 0x0a48
136#define RM9000x2_OCD_INTPIN3 0x0a4c
137#define RM9000x2_OCD_INTPIN4 0x0a50
138#define RM9000x2_OCD_INTPIN5 0x0a54
139#define RM9000x2_OCD_INTPIN6 0x0a58
140#define RM9000x2_OCD_INTPIN7 0x0a5c
141#define RM9000x2_OCD_SEM 0x0a60
142#define RM9000x2_OCD_SEMSET 0x0a64
143#define RM9000x2_OCD_SEMCLR 0x0a68
144
145#define RM9000x2_OCD_TKT 0x0a70
146#define RM9000x2_OCD_TKTINC 0x0a74
147
148#define RM9000x2_OCD_NMICONFIG 0x0ac0 /* Interrupts */
149#define RM9000x2_OCD_INTP0PRI 0x1a80
150#define RM9000x2_OCD_INTP1PRI 0x1a80
151#define RM9000x2_OCD_INTP0STATUS0 0x1b00
152#define RM9000x2_OCD_INTP0MASK0 0x1b04
153#define RM9000x2_OCD_INTP0SET0 0x1b08
154#define RM9000x2_OCD_INTP0CLEAR0 0x1b0c
155#define RM9000x2_OCD_INTP0STATUS1 0x1b10
156#define RM9000x2_OCD_INTP0MASK1 0x1b14
157#define RM9000x2_OCD_INTP0SET1 0x1b18
158#define RM9000x2_OCD_INTP0CLEAR1 0x1b1c
159#define RM9000x2_OCD_INTP0STATUS2 0x1b20
160#define RM9000x2_OCD_INTP0MASK2 0x1b24
161#define RM9000x2_OCD_INTP0SET2 0x1b28
162#define RM9000x2_OCD_INTP0CLEAR2 0x1b2c
163#define RM9000x2_OCD_INTP0STATUS3 0x1b30
164#define RM9000x2_OCD_INTP0MASK3 0x1b34
165#define RM9000x2_OCD_INTP0SET3 0x1b38
166#define RM9000x2_OCD_INTP0CLEAR3 0x1b3c
167#define RM9000x2_OCD_INTP0STATUS4 0x1b40
168#define RM9000x2_OCD_INTP0MASK4 0x1b44
169#define RM9000x2_OCD_INTP0SET4 0x1b48
170#define RM9000x2_OCD_INTP0CLEAR4 0x1b4c
171#define RM9000x2_OCD_INTP0STATUS5 0x1b50
172#define RM9000x2_OCD_INTP0MASK5 0x1b54
173#define RM9000x2_OCD_INTP0SET5 0x1b58
174#define RM9000x2_OCD_INTP0CLEAR5 0x1b5c
175#define RM9000x2_OCD_INTP0STATUS6 0x1b60
176#define RM9000x2_OCD_INTP0MASK6 0x1b64
177#define RM9000x2_OCD_INTP0SET6 0x1b68
178#define RM9000x2_OCD_INTP0CLEAR6 0x1b6c
179#define RM9000x2_OCD_INTP0STATUS7 0x1b70
180#define RM9000x2_OCD_INTP0MASK7 0x1b74
181#define RM9000x2_OCD_INTP0SET7 0x1b78
182#define RM9000x2_OCD_INTP0CLEAR7 0x1b7c
183#define RM9000x2_OCD_INTP1STATUS0 0x2b00
184#define RM9000x2_OCD_INTP1MASK0 0x2b04
185#define RM9000x2_OCD_INTP1SET0 0x2b08
186#define RM9000x2_OCD_INTP1CLEAR0 0x2b0c
187#define RM9000x2_OCD_INTP1STATUS1 0x2b10
188#define RM9000x2_OCD_INTP1MASK1 0x2b14
189#define RM9000x2_OCD_INTP1SET1 0x2b18
190#define RM9000x2_OCD_INTP1CLEAR1 0x2b1c
191#define RM9000x2_OCD_INTP1STATUS2 0x2b20
192#define RM9000x2_OCD_INTP1MASK2 0x2b24
193#define RM9000x2_OCD_INTP1SET2 0x2b28
194#define RM9000x2_OCD_INTP1CLEAR2 0x2b2c
195#define RM9000x2_OCD_INTP1STATUS3 0x2b30
196#define RM9000x2_OCD_INTP1MASK3 0x2b34
197#define RM9000x2_OCD_INTP1SET3 0x2b38
198#define RM9000x2_OCD_INTP1CLEAR3 0x2b3c
199#define RM9000x2_OCD_INTP1STATUS4 0x2b40
200#define RM9000x2_OCD_INTP1MASK4 0x2b44
201#define RM9000x2_OCD_INTP1SET4 0x2b48
202#define RM9000x2_OCD_INTP1CLEAR4 0x2b4c
203#define RM9000x2_OCD_INTP1STATUS5 0x2b50
204#define RM9000x2_OCD_INTP1MASK5 0x2b54
205#define RM9000x2_OCD_INTP1SET5 0x2b58
206#define RM9000x2_OCD_INTP1CLEAR5 0x2b5c
207#define RM9000x2_OCD_INTP1STATUS6 0x2b60
208#define RM9000x2_OCD_INTP1MASK6 0x2b64
209#define RM9000x2_OCD_INTP1SET6 0x2b68
210#define RM9000x2_OCD_INTP1CLEAR6 0x2b6c
211#define RM9000x2_OCD_INTP1STATUS7 0x2b70
212#define RM9000x2_OCD_INTP1MASK7 0x2b74
213#define RM9000x2_OCD_INTP1SET7 0x2b78
214#define RM9000x2_OCD_INTP1CLEAR7 0x2b7c
215
216#define OCD_READ(reg) (*(volatile unsigned int *)(ocd_base + (reg)))
217#define OCD_WRITE(reg, val) \
218 do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
219
220/*
221 * Hypertransport specific macros
222 */
223#define RM9K_WRITE(ofs, data) *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
224#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
225#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
226
227#define RM9K_READ(ofs, val) *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
228#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
229#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
230
231#endif
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index fa133c1bc1f9..65e344532ded 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -209,14 +209,6 @@
209#endif 209#endif
210 210
211/* 211/*
212 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
213 * eache operation unusable on SMP systems.
214 */
215#ifndef RM9000_CDEX_SMP_WAR
216#error Check setting of RM9000_CDEX_SMP_WAR for your platform
217#endif
218
219/*
220 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra 212 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
221 * opposes it being called that) where invalid instructions in the same 213 * opposes it being called that) where invalid instructions in the same
222 * I-cache line worth of instructions being fetched may case spurious 214 * I-cache line worth of instructions being fetched may case spurious
diff --git a/arch/mips/include/uapi/asm/ioctls.h b/arch/mips/include/uapi/asm/ioctls.h
index 92403c3d6007..addd56b60694 100644
--- a/arch/mips/include/uapi/asm/ioctls.h
+++ b/arch/mips/include/uapi/asm/ioctls.h
@@ -86,6 +86,9 @@
86#define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */ 86#define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */
87#define TIOCSIG _IOW('T', 0x36, int) /* Generate signal on Pty slave */ 87#define TIOCSIG _IOW('T', 0x36, int) /* Generate signal on Pty slave */
88#define TIOCVHANGUP 0x5437 88#define TIOCVHANGUP 0x5437
89#define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */
90#define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */
91#define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */
89 92
90/* I hope the range from 0x5480 on is free ... */ 93/* I hope the range from 0x5480 on is free ... */
91#define TIOCSCTTY 0x5480 /* become controlling tty */ 94#define TIOCSCTTY 0x5480 /* become controlling tty */
diff --git a/arch/mips/include/uapi/asm/mman.h b/arch/mips/include/uapi/asm/mman.h
index 46d3da0d4b92..9a936ac9a942 100644
--- a/arch/mips/include/uapi/asm/mman.h
+++ b/arch/mips/include/uapi/asm/mman.h
@@ -87,4 +87,15 @@
87/* compatibility flags */ 87/* compatibility flags */
88#define MAP_FILE 0 88#define MAP_FILE 0
89 89
90/*
91 * When MAP_HUGETLB is set bits [26:31] encode the log2 of the huge page size.
92 * This gives us 6 bits, which is enough until someone invents 128 bit address
93 * spaces.
94 *
95 * Assume these are all power of twos.
96 * When 0 use the default page size.
97 */
98#define MAP_HUGE_SHIFT 26
99#define MAP_HUGE_MASK 0x3f
100
90#endif /* _ASM_MMAN_H */ 101#endif /* _ASM_MMAN_H */
diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h
index 3f1237c6c80e..770732cb8d03 100644
--- a/arch/mips/include/uapi/asm/signal.h
+++ b/arch/mips/include/uapi/asm/signal.h
@@ -86,12 +86,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
86 86
87#define SA_RESTORER 0x04000000 /* Only for o32 */ 87#define SA_RESTORER 0x04000000 /* Only for o32 */
88 88
89/*
90 * sigaltstack controls
91 */
92#define SS_ONSTACK 1
93#define SS_DISABLE 2
94
95#define MINSIGSTKSZ 2048 89#define MINSIGSTKSZ 2048
96#define SIGSTKSZ 8192 90#define SIGSTKSZ 8192
97 91
diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h
index c5ed59549cb8..17307ab90474 100644
--- a/arch/mips/include/uapi/asm/socket.h
+++ b/arch/mips/include/uapi/asm/socket.h
@@ -63,6 +63,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
63/* Socket filtering */ 63/* Socket filtering */
64#define SO_ATTACH_FILTER 26 64#define SO_ATTACH_FILTER 26
65#define SO_DETACH_FILTER 27 65#define SO_DETACH_FILTER 27
66#define SO_GET_FILTER SO_ATTACH_FILTER
66 67
67#define SO_PEERNAME 28 68#define SO_PEERNAME 28
68#define SO_TIMESTAMP 29 69#define SO_TIMESTAMP 29
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index cc98a9dcb01b..0eebf3c3e03c 100644
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -368,16 +368,17 @@
368#define __NR_process_vm_readv (__NR_Linux + 345) 368#define __NR_process_vm_readv (__NR_Linux + 345)
369#define __NR_process_vm_writev (__NR_Linux + 346) 369#define __NR_process_vm_writev (__NR_Linux + 346)
370#define __NR_kcmp (__NR_Linux + 347) 370#define __NR_kcmp (__NR_Linux + 347)
371#define __NR_finit_module (__NR_Linux + 348)
371 372
372/* 373/*
373 * Offset of the last Linux o32 flavoured syscall 374 * Offset of the last Linux o32 flavoured syscall
374 */ 375 */
375#define __NR_Linux_syscalls 347 376#define __NR_Linux_syscalls 348
376 377
377#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 378#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
378 379
379#define __NR_O32_Linux 4000 380#define __NR_O32_Linux 4000
380#define __NR_O32_Linux_syscalls 347 381#define __NR_O32_Linux_syscalls 348
381 382
382#if _MIPS_SIM == _MIPS_SIM_ABI64 383#if _MIPS_SIM == _MIPS_SIM_ABI64
383 384
@@ -692,16 +693,17 @@
692#define __NR_process_vm_readv (__NR_Linux + 304) 693#define __NR_process_vm_readv (__NR_Linux + 304)
693#define __NR_process_vm_writev (__NR_Linux + 305) 694#define __NR_process_vm_writev (__NR_Linux + 305)
694#define __NR_kcmp (__NR_Linux + 306) 695#define __NR_kcmp (__NR_Linux + 306)
696#define __NR_finit_module (__NR_Linux + 307)
695 697
696/* 698/*
697 * Offset of the last Linux 64-bit flavoured syscall 699 * Offset of the last Linux 64-bit flavoured syscall
698 */ 700 */
699#define __NR_Linux_syscalls 306 701#define __NR_Linux_syscalls 307
700 702
701#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 703#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
702 704
703#define __NR_64_Linux 5000 705#define __NR_64_Linux 5000
704#define __NR_64_Linux_syscalls 306 706#define __NR_64_Linux_syscalls 307
705 707
706#if _MIPS_SIM == _MIPS_SIM_NABI32 708#if _MIPS_SIM == _MIPS_SIM_NABI32
707 709
@@ -1021,15 +1023,16 @@
1021#define __NR_process_vm_readv (__NR_Linux + 309) 1023#define __NR_process_vm_readv (__NR_Linux + 309)
1022#define __NR_process_vm_writev (__NR_Linux + 310) 1024#define __NR_process_vm_writev (__NR_Linux + 310)
1023#define __NR_kcmp (__NR_Linux + 311) 1025#define __NR_kcmp (__NR_Linux + 311)
1026#define __NR_finit_module (__NR_Linux + 312)
1024 1027
1025/* 1028/*
1026 * Offset of the last N32 flavoured syscall 1029 * Offset of the last N32 flavoured syscall
1027 */ 1030 */
1028#define __NR_Linux_syscalls 311 1031#define __NR_Linux_syscalls 312
1029 1032
1030#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 1033#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1031 1034
1032#define __NR_N32_Linux 6000 1035#define __NR_N32_Linux 6000
1033#define __NR_N32_Linux_syscalls 311 1036#define __NR_N32_Linux_syscalls 312
1034 1037
1035#endif /* _UAPI_ASM_UNISTD_H */ 1038#endif /* _UAPI_ASM_UNISTD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 13:32:21 -0400