diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2013-04-22 11:57:54 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-04-22 12:09:35 -0400 |
| commit | 3b5e50edaf500f392f4a372296afc0b99ffa7e70 (patch) | |
| tree | 494cb0bafa1e787b7e00b6cfa0c2929660f760b1 /arch/mips/include | |
| parent | 41ef2d5678d83af030125550329b6ae8b74618fa (diff) | |
Revert "MIPS: page.h: Provide more readable definition for PAGE_MASK."
This reverts commit c17a6554782ad531f4713b33fd6339ba67ef6391.
Manuel Lauss writes:
lmo commit c17a6554 (MIPS: page.h: Provide more readable definition for
PAGE_MASK) apparently breaks ioremap of 36-bit addresses on my Alchemy
systems (PCI and PCMCIA) The reason is that in arch/mips/mm/ioremap.c
line 157 (phys_addr &= PAGE_MASK) bits 32-35 are cut off. Seems the
new PAGE_MASK is explicitly 32bit, or one could make it signed instead
of unsigned long.
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/page.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index 99fc547af9d3..eab99e536b5c 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #define PAGE_SHIFT 16 | 31 | #define PAGE_SHIFT 16 |
| 32 | #endif | 32 | #endif |
| 33 | #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) | 33 | #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) |
| 34 | #define PAGE_MASK (~(PAGE_SIZE - 1)) | 34 | #define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) |
| 35 | 35 | ||
| 36 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | 36 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
| 37 | #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) | 37 | #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) |