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author | Akira Takeuchi <takeuchi.akr@jp.panasonic.com> | 2010-10-27 12:28:39 -0400 |
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committer | David Howells <dhowells@redhat.com> | 2010-10-27 12:28:39 -0400 |
commit | 06019be31a1b5812eec5bb3e1dbdeced04950e8e (patch) | |
tree | c885748da5ba7232877cb509ba59d5c0aa1bc43a /arch/mips/include | |
parent | a116956423e1cdc4398110bdc66d66ae4c5ba90f (diff) |
MN10300: Don't hard code the cacheline size in register defs
Don't hard code the cacheline size in the cache control register definitions.
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/mips/include')
0 files changed, 0 insertions, 0 deletions