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authorSteven J. Hill <sjhill@mips.com>2012-12-06 22:51:35 -0500
committerJohn Crispin <blogic@openwrt.org>2013-02-16 18:15:23 -0500
commitf8fa4811dbb264aef13f982e963389fd828b1ac0 (patch)
treeed1c9d2d9818671ca78feab63872d10b611ab953 /arch/mips/include/asm
parent127993e561846e889004d7d21a84fb5a6c40b9c3 (diff)
MIPS: Add support for the M14KEc core.
Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/cpu.h3
-rw-r--r--arch/mips/include/asm/mipsregs.h1
3 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c507b931b484..00171cddb6d5 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -98,6 +98,9 @@
98#ifndef cpu_has_rixi 98#ifndef cpu_has_rixi
99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
100#endif 100#endif
101#ifndef cpu_has_mmips
102#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
103#endif
101#ifndef cpu_has_vtag_icache 104#ifndef cpu_has_vtag_icache
102#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 105#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
103#endif 106#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 90112adb1940..2de2fee16cc4 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -96,6 +96,7 @@
96#define PRID_IMP_1004K 0x9900 96#define PRID_IMP_1004K 0x9900
97#define PRID_IMP_1074K 0x9a00 97#define PRID_IMP_1074K 0x9a00
98#define PRID_IMP_M14KC 0x9c00 98#define PRID_IMP_M14KC 0x9c00
99#define PRID_IMP_M14KEC 0x9e00
99 100
100/* 101/*
101 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 102 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -264,6 +265,7 @@ enum cpu_type_enum {
264 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 265 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
265 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 266 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
266 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 267 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
268 CPU_M14KEC,
267 269
268 /* 270 /*
269 * MIPS64 class processors 271 * MIPS64 class processors
@@ -322,6 +324,7 @@ enum cpu_type_enum {
322#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ 324#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
323#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 325#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
324#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 326#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
327#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
325 328
326/* 329/*
327 * CPU ASE encodings 330 * CPU ASE encodings
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7e4e6f8fab37..3e36745670b2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -595,6 +595,7 @@
595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
598 599
599#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 600#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
600#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 601#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)