diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-05-26 22:00:52 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-05-26 22:00:52 -0400 |
| commit | 45f6bc5ff9c3387387f048ec85dcb4e69acf0b03 (patch) | |
| tree | d04952bb05b53a362bcd165fb910c5c1441b4c5d /arch/mips/include/asm | |
| parent | 3138887bd8d18173f3c2baf1e43621c49090cd27 (diff) | |
| parent | e4aa937ec75df0eea0bee03bffa3303ad36c986b (diff) | |
Merge 3.10-rc3 into usb-next
We want these fixes.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/clock.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/idle.h | 23 | ||||
| -rw-r--r-- | arch/mips/include/asm/io.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/kvm.h | 55 | ||||
| -rw-r--r-- | arch/mips/include/asm/kvm_host.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/mmu_context.h | 95 | ||||
| -rw-r--r-- | arch/mips/include/asm/page.h | 17 | ||||
| -rw-r--r-- | arch/mips/include/asm/processor.h | 1 |
8 files changed, 69 insertions, 128 deletions
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h index c9456e7a7283..778e32d817bc 100644 --- a/arch/mips/include/asm/clock.h +++ b/arch/mips/include/asm/clock.h | |||
| @@ -6,8 +6,6 @@ | |||
| 6 | #include <linux/seq_file.h> | 6 | #include <linux/seq_file.h> |
| 7 | #include <linux/clk.h> | 7 | #include <linux/clk.h> |
| 8 | 8 | ||
| 9 | extern void (*cpu_wait) (void); | ||
| 10 | |||
| 11 | struct clk; | 9 | struct clk; |
| 12 | 10 | ||
| 13 | struct clk_ops { | 11 | struct clk_ops { |
diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h new file mode 100644 index 000000000000..d192158886b1 --- /dev/null +++ b/arch/mips/include/asm/idle.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_IDLE_H | ||
| 2 | #define __ASM_IDLE_H | ||
| 3 | |||
| 4 | #include <linux/linkage.h> | ||
| 5 | |||
| 6 | extern void (*cpu_wait)(void); | ||
| 7 | extern void r4k_wait(void); | ||
| 8 | extern asmlinkage void __r4k_wait(void); | ||
| 9 | extern void r4k_wait_irqoff(void); | ||
| 10 | extern void __pastwait(void); | ||
| 11 | |||
| 12 | static inline int using_rollback_handler(void) | ||
| 13 | { | ||
| 14 | return cpu_wait == r4k_wait; | ||
| 15 | } | ||
| 16 | |||
| 17 | static inline int address_is_in_r4k_wait_irqoff(unsigned long addr) | ||
| 18 | { | ||
| 19 | return addr >= (unsigned long)r4k_wait_irqoff && | ||
| 20 | addr < (unsigned long)__pastwait; | ||
| 21 | } | ||
| 22 | |||
| 23 | #endif /* __ASM_IDLE_H */ | ||
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 1be13727323f..b7e59853fd33 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h | |||
| @@ -118,7 +118,7 @@ static inline void set_io_port_base(unsigned long base) | |||
| 118 | */ | 118 | */ |
| 119 | static inline unsigned long virt_to_phys(volatile const void *address) | 119 | static inline unsigned long virt_to_phys(volatile const void *address) |
| 120 | { | 120 | { |
| 121 | return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET; | 121 | return __pa(address); |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | /* | 124 | /* |
diff --git a/arch/mips/include/asm/kvm.h b/arch/mips/include/asm/kvm.h deleted file mode 100644 index 85789eacbf18..000000000000 --- a/arch/mips/include/asm/kvm.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | ||
| 7 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __LINUX_KVM_MIPS_H | ||
| 11 | #define __LINUX_KVM_MIPS_H | ||
| 12 | |||
| 13 | #include <linux/types.h> | ||
| 14 | |||
| 15 | #define __KVM_MIPS | ||
| 16 | |||
| 17 | #define N_MIPS_COPROC_REGS 32 | ||
| 18 | #define N_MIPS_COPROC_SEL 8 | ||
| 19 | |||
| 20 | /* for KVM_GET_REGS and KVM_SET_REGS */ | ||
| 21 | struct kvm_regs { | ||
| 22 | __u32 gprs[32]; | ||
| 23 | __u32 hi; | ||
| 24 | __u32 lo; | ||
| 25 | __u32 pc; | ||
| 26 | |||
| 27 | __u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | ||
| 28 | }; | ||
| 29 | |||
| 30 | /* for KVM_GET_SREGS and KVM_SET_SREGS */ | ||
| 31 | struct kvm_sregs { | ||
| 32 | }; | ||
| 33 | |||
| 34 | /* for KVM_GET_FPU and KVM_SET_FPU */ | ||
| 35 | struct kvm_fpu { | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct kvm_debug_exit_arch { | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* for KVM_SET_GUEST_DEBUG */ | ||
| 42 | struct kvm_guest_debug_arch { | ||
| 43 | }; | ||
| 44 | |||
| 45 | struct kvm_mips_interrupt { | ||
| 46 | /* in */ | ||
| 47 | __u32 cpu; | ||
| 48 | __u32 irq; | ||
| 49 | }; | ||
| 50 | |||
| 51 | /* definition of registers in kvm_run */ | ||
| 52 | struct kvm_sync_regs { | ||
| 53 | }; | ||
| 54 | |||
| 55 | #endif /* __LINUX_KVM_MIPS_H */ | ||
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index e68781e18387..143875c6c95a 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h | |||
| @@ -336,7 +336,7 @@ enum emulation_result { | |||
| 336 | #define VPN2_MASK 0xffffe000 | 336 | #define VPN2_MASK 0xffffe000 |
| 337 | #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G)) | 337 | #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G)) |
| 338 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) | 338 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) |
| 339 | #define TLB_ASID(x) (ASID_MASK((x).tlb_hi)) | 339 | #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK) |
| 340 | #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V)) | 340 | #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V)) |
| 341 | 341 | ||
| 342 | struct kvm_mips_tlb { | 342 | struct kvm_mips_tlb { |
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 1554721e4808..820116067c10 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h | |||
| @@ -67,68 +67,45 @@ extern unsigned long pgd_current[]; | |||
| 67 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) | 67 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
| 68 | #endif | 68 | #endif |
| 69 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ | 69 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ |
| 70 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | ||
| 70 | 71 | ||
| 71 | #define ASID_INC(asid) \ | 72 | #define ASID_INC 0x40 |
| 72 | ({ \ | 73 | #define ASID_MASK 0xfc0 |
| 73 | unsigned long __asid = asid; \ | 74 | |
| 74 | __asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t" \ | 75 | #elif defined(CONFIG_CPU_R8000) |
| 75 | ".section\t__asid_inc,\"a\"\n\t" \ | 76 | |
| 76 | ".word\t1b\n\t" \ | 77 | #define ASID_INC 0x10 |
| 77 | ".previous" \ | 78 | #define ASID_MASK 0xff0 |
| 78 | :"=r" (__asid) \ | 79 | |
| 79 | :"0" (__asid)); \ | 80 | #elif defined(CONFIG_MIPS_MT_SMTC) |
| 80 | __asid; \ | 81 | |
| 81 | }) | 82 | #define ASID_INC 0x1 |
| 82 | #define ASID_MASK(asid) \ | 83 | extern unsigned long smtc_asid_mask; |
| 83 | ({ \ | 84 | #define ASID_MASK (smtc_asid_mask) |
| 84 | unsigned long __asid = asid; \ | 85 | #define HW_ASID_MASK 0xff |
| 85 | __asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t" \ | 86 | /* End SMTC/34K debug hack */ |
| 86 | ".section\t__asid_mask,\"a\"\n\t" \ | 87 | #else /* FIXME: not correct for R6000 */ |
| 87 | ".word\t1b\n\t" \ | 88 | |
| 88 | ".previous" \ | 89 | #define ASID_INC 0x1 |
| 89 | :"=r" (__asid) \ | 90 | #define ASID_MASK 0xff |
| 90 | :"r" (__asid)); \ | ||
| 91 | __asid; \ | ||
| 92 | }) | ||
| 93 | #define ASID_VERSION_MASK \ | ||
| 94 | ({ \ | ||
| 95 | unsigned long __asid; \ | ||
| 96 | __asm__("1:\taddiu\t%0,$0,0xff00\t\t\t\t# patched\n\t" \ | ||
| 97 | ".section\t__asid_version_mask,\"a\"\n\t" \ | ||
| 98 | ".word\t1b\n\t" \ | ||
| 99 | ".previous" \ | ||
| 100 | :"=r" (__asid)); \ | ||
| 101 | __asid; \ | ||
| 102 | }) | ||
| 103 | #define ASID_FIRST_VERSION \ | ||
| 104 | ({ \ | ||
| 105 | unsigned long __asid = asid; \ | ||
| 106 | __asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t" \ | ||
| 107 | ".section\t__asid_first_version,\"a\"\n\t" \ | ||
| 108 | ".word\t1b\n\t" \ | ||
| 109 | ".previous" \ | ||
| 110 | :"=r" (__asid)); \ | ||
| 111 | __asid; \ | ||
| 112 | }) | ||
| 113 | |||
| 114 | #define ASID_FIRST_VERSION_R3000 0x1000 | ||
| 115 | #define ASID_FIRST_VERSION_R4000 0x100 | ||
| 116 | #define ASID_FIRST_VERSION_R8000 0x1000 | ||
| 117 | #define ASID_FIRST_VERSION_RM9000 0x1000 | ||
| 118 | 91 | ||
| 119 | #ifdef CONFIG_MIPS_MT_SMTC | ||
| 120 | #define SMTC_HW_ASID_MASK 0xff | ||
| 121 | extern unsigned int smtc_asid_mask; | ||
| 122 | #endif | 92 | #endif |
| 123 | 93 | ||
| 124 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) | 94 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) |
| 125 | #define cpu_asid(cpu, mm) ASID_MASK(cpu_context((cpu), (mm))) | 95 | #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) |
| 126 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) | 96 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) |
| 127 | 97 | ||
| 128 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | 98 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) |
| 129 | { | 99 | { |
| 130 | } | 100 | } |
| 131 | 101 | ||
| 102 | /* | ||
| 103 | * All unused by hardware upper bits will be considered | ||
| 104 | * as a software asid extension. | ||
| 105 | */ | ||
| 106 | #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) | ||
| 107 | #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) | ||
| 108 | |||
| 132 | #ifndef CONFIG_MIPS_MT_SMTC | 109 | #ifndef CONFIG_MIPS_MT_SMTC |
| 133 | /* Normal, classic MIPS get_new_mmu_context */ | 110 | /* Normal, classic MIPS get_new_mmu_context */ |
| 134 | static inline void | 111 | static inline void |
| @@ -137,7 +114,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |||
| 137 | extern void kvm_local_flush_tlb_all(void); | 114 | extern void kvm_local_flush_tlb_all(void); |
| 138 | unsigned long asid = asid_cache(cpu); | 115 | unsigned long asid = asid_cache(cpu); |
| 139 | 116 | ||
| 140 | if (!ASID_MASK((asid = ASID_INC(asid)))) { | 117 | if (! ((asid += ASID_INC) & ASID_MASK) ) { |
| 141 | if (cpu_has_vtag_icache) | 118 | if (cpu_has_vtag_icache) |
| 142 | flush_icache_all(); | 119 | flush_icache_all(); |
| 143 | #ifdef CONFIG_VIRTUALIZATION | 120 | #ifdef CONFIG_VIRTUALIZATION |
| @@ -200,7 +177,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |||
| 200 | * free up the ASID value for use and flush any old | 177 | * free up the ASID value for use and flush any old |
| 201 | * instances of it from the TLB. | 178 | * instances of it from the TLB. |
| 202 | */ | 179 | */ |
| 203 | oldasid = ASID_MASK(read_c0_entryhi()); | 180 | oldasid = (read_c0_entryhi() & ASID_MASK); |
| 204 | if(smtc_live_asid[mytlb][oldasid]) { | 181 | if(smtc_live_asid[mytlb][oldasid]) { |
| 205 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | 182 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
| 206 | if(smtc_live_asid[mytlb][oldasid] == 0) | 183 | if(smtc_live_asid[mytlb][oldasid] == 0) |
| @@ -211,7 +188,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |||
| 211 | * having ASID_MASK smaller than the hardware maximum, | 188 | * having ASID_MASK smaller than the hardware maximum, |
| 212 | * make sure no "soft" bits become "hard"... | 189 | * make sure no "soft" bits become "hard"... |
| 213 | */ | 190 | */ |
| 214 | write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) | | 191 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
| 215 | cpu_asid(cpu, next)); | 192 | cpu_asid(cpu, next)); |
| 216 | ehb(); /* Make sure it propagates to TCStatus */ | 193 | ehb(); /* Make sure it propagates to TCStatus */ |
| 217 | evpe(mtflags); | 194 | evpe(mtflags); |
| @@ -264,15 +241,15 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) | |||
| 264 | #ifdef CONFIG_MIPS_MT_SMTC | 241 | #ifdef CONFIG_MIPS_MT_SMTC |
| 265 | /* See comments for similar code above */ | 242 | /* See comments for similar code above */ |
| 266 | mtflags = dvpe(); | 243 | mtflags = dvpe(); |
| 267 | oldasid = ASID_MASK(read_c0_entryhi()); | 244 | oldasid = read_c0_entryhi() & ASID_MASK; |
| 268 | if(smtc_live_asid[mytlb][oldasid]) { | 245 | if(smtc_live_asid[mytlb][oldasid]) { |
| 269 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | 246 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
| 270 | if(smtc_live_asid[mytlb][oldasid] == 0) | 247 | if(smtc_live_asid[mytlb][oldasid] == 0) |
| 271 | smtc_flush_tlb_asid(oldasid); | 248 | smtc_flush_tlb_asid(oldasid); |
| 272 | } | 249 | } |
| 273 | /* See comments for similar code above */ | 250 | /* See comments for similar code above */ |
| 274 | write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) | | 251 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
| 275 | cpu_asid(cpu, next)); | 252 | cpu_asid(cpu, next)); |
| 276 | ehb(); /* Make sure it propagates to TCStatus */ | 253 | ehb(); /* Make sure it propagates to TCStatus */ |
| 277 | evpe(mtflags); | 254 | evpe(mtflags); |
| 278 | #else | 255 | #else |
| @@ -309,14 +286,14 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) | |||
| 309 | #ifdef CONFIG_MIPS_MT_SMTC | 286 | #ifdef CONFIG_MIPS_MT_SMTC |
| 310 | /* See comments for similar code above */ | 287 | /* See comments for similar code above */ |
| 311 | prevvpe = dvpe(); | 288 | prevvpe = dvpe(); |
| 312 | oldasid = ASID_MASK(read_c0_entryhi()); | 289 | oldasid = (read_c0_entryhi() & ASID_MASK); |
| 313 | if (smtc_live_asid[mytlb][oldasid]) { | 290 | if (smtc_live_asid[mytlb][oldasid]) { |
| 314 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | 291 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
| 315 | if(smtc_live_asid[mytlb][oldasid] == 0) | 292 | if(smtc_live_asid[mytlb][oldasid] == 0) |
| 316 | smtc_flush_tlb_asid(oldasid); | 293 | smtc_flush_tlb_asid(oldasid); |
| 317 | } | 294 | } |
| 318 | /* See comments for similar code above */ | 295 | /* See comments for similar code above */ |
| 319 | write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) | 296 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
| 320 | | cpu_asid(cpu, mm)); | 297 | | cpu_asid(cpu, mm)); |
| 321 | ehb(); /* Make sure it propagates to TCStatus */ | 298 | ehb(); /* Make sure it propagates to TCStatus */ |
| 322 | evpe(prevvpe); | 299 | evpe(prevvpe); |
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index eab99e536b5c..f59552fae917 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h | |||
| @@ -46,7 +46,6 @@ | |||
| 46 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ | 46 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
| 47 | 47 | ||
| 48 | #include <linux/pfn.h> | 48 | #include <linux/pfn.h> |
| 49 | #include <asm/io.h> | ||
| 50 | 49 | ||
| 51 | extern void build_clear_page(void); | 50 | extern void build_clear_page(void); |
| 52 | extern void build_copy_page(void); | 51 | extern void build_copy_page(void); |
| @@ -151,6 +150,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; | |||
| 151 | ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) | 150 | ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) |
| 152 | #endif | 151 | #endif |
| 153 | #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) | 152 | #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) |
| 153 | #include <asm/io.h> | ||
| 154 | 154 | ||
| 155 | /* | 155 | /* |
| 156 | * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad | 156 | * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad |
| @@ -171,14 +171,13 @@ typedef struct { unsigned long pgprot; } pgprot_t; | |||
| 171 | 171 | ||
| 172 | #ifdef CONFIG_FLATMEM | 172 | #ifdef CONFIG_FLATMEM |
| 173 | 173 | ||
| 174 | #define pfn_valid(pfn) \ | 174 | static inline int pfn_valid(unsigned long pfn) |
| 175 | ({ \ | 175 | { |
| 176 | unsigned long __pfn = (pfn); \ | 176 | /* avoid <linux/mm.h> include hell */ |
| 177 | /* avoid <linux/bootmem.h> include hell */ \ | 177 | extern unsigned long max_mapnr; |
| 178 | extern unsigned long min_low_pfn; \ | 178 | |
| 179 | \ | 179 | return pfn >= ARCH_PFN_OFFSET && pfn < max_mapnr; |
| 180 | __pfn >= min_low_pfn && __pfn < max_mapnr; \ | 180 | } |
| 181 | }) | ||
| 182 | 181 | ||
| 183 | #elif defined(CONFIG_SPARSEMEM) | 182 | #elif defined(CONFIG_SPARSEMEM) |
| 184 | 183 | ||
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 71686c897dea..1470b7b68b0e 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | /* | 28 | /* |
| 29 | * System setup and hardware flags.. | 29 | * System setup and hardware flags.. |
| 30 | */ | 30 | */ |
| 31 | extern void (*cpu_wait)(void); | ||
| 32 | 31 | ||
| 33 | extern unsigned int vced_count, vcei_count; | 32 | extern unsigned int vced_count, vcei_count; |
| 34 | 33 | ||
