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| author | Felix Blyakher <felixb@sgi.com> | 2009-03-16 10:15:13 -0400 |
|---|---|---|
| committer | Felix Blyakher <felixb@sgi.com> | 2009-03-16 10:15:13 -0400 |
| commit | cb1b77804091cc3491da4338a3599e318f358b25 (patch) | |
| tree | 481372e91d926b566d7e59c08a97bd3c16c5026a /arch/mips/include/asm/prefetch.h | |
| parent | da5309cd28ffda6ed8a4147bd14f1e4fbbd6503d (diff) | |
| parent | 5bee17f18b595937e6beafeee5197868a3f74a06 (diff) | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/mips/include/asm/prefetch.h')
| -rw-r--r-- | arch/mips/include/asm/prefetch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 17850834ccb0..a56594f360ee 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in | 26 | * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in |
| 27 | * current versions due to erratum G105. | 27 | * current versions due to erratum G105. |
| 28 | * | 28 | * |
| 29 | * VR7701 only implements the Load prefetch. | 29 | * VR5500 (including VR5701 and VR7701) only implement load prefetch. |
| 30 | * | 30 | * |
| 31 | * Finally MIPS32 and MIPS64 implement all of the following hints. | 31 | * Finally MIPS32 and MIPS64 implement all of the following hints. |
| 32 | */ | 32 | */ |