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authorLinus Torvalds <torvalds@linux-foundation.org>2015-06-14 21:38:57 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-06-14 21:38:57 -0400
commit1f1e34f7231c7284f3acae37096a603f19bcd8b7 (patch)
treecbc9a61bc3a1055b7868134adea32b41af733c95 /arch/mips/include/asm/pgtable-bits.h
parentbaaae1921088079bdb8e71317b06d071511d74b1 (diff)
parent36f58113423f4588d7cf7535644fbb214414193b (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull more MIPS fixes from Ralf Baechle: "Another round of 4.1 MIPS fixes, one fix to a MIPS-specific #if condition in lib/mpi, one fix to the MIPS GIC irqchip driver and one SSB fix. Details: - fix handling of clock in chipco SSB driver. - fix two MIPS-specific #if conditions to correctly work for GCC 5.1. - fix damage to R6 pgtable bits done by XPA support. - fix possible crash due to unloading modules that contain statically defined platform devices. - fix disabling of the MSA ASE on context switch to also work correctly when a new thread/process has the CPU for the very first time. This is part of linux-next and has been beaten to death on Imagination's test farm. While things are not looking too grim this pull request also means the rate of fixes for 4.1 remains nearly constant so I'd not be unhappy if you'd delay the release" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MPI: MIPS: Fix compilation error with GCC 5.1 IRQCHIP: mips-gic: Don't nest calls to do_IRQ() MIPS: MSA: bugfix - disable MSA correctly for new threads/processes. MIPS: Loongson: Do not register 8250 platform device from module. MIPS: Cobalt: Do not build MTD platform device registration code as module. SSB: Fix handling of ssb_pmu_get_alp_clock() MIPS: pgtable-bits: Fix XPA damage to R6 definitions.
Diffstat (limited to 'arch/mips/include/asm/pgtable-bits.h')
-rw-r--r--arch/mips/include/asm/pgtable-bits.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 18ae5ddef118..c28a8499aec7 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -113,7 +113,7 @@
113#define _PAGE_PRESENT_SHIFT 0 113#define _PAGE_PRESENT_SHIFT 0
114#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 114#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
115/* R2 or later cores check for RI/XI support to determine _PAGE_READ */ 115/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
116#ifdef CONFIG_CPU_MIPSR2 116#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
117#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) 117#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
118#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 118#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
119#else 119#else
@@ -135,16 +135,16 @@
135#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 135#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
136 136
137/* Only R2 or newer cores have the XI bit */ 137/* Only R2 or newer cores have the XI bit */
138#ifdef CONFIG_CPU_MIPSR2 138#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
139#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 139#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
140#else 140#else
141#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 141#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
142#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 142#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
143#endif /* CONFIG_CPU_MIPSR2 */ 143#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
144 144
145#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ 145#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
146 146
147#ifdef CONFIG_CPU_MIPSR2 147#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
148/* XI - page cannot be executed */ 148/* XI - page cannot be executed */
149#ifndef _PAGE_NO_EXEC_SHIFT 149#ifndef _PAGE_NO_EXEC_SHIFT
150#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 150#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
@@ -160,10 +160,10 @@
160#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 160#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
161#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 161#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
162 162
163#else /* !CONFIG_CPU_MIPSR2 */ 163#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */
164#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 164#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
165#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 165#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
166#endif /* CONFIG_CPU_MIPSR2 */ 166#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
167 167
168#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 168#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
169#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 169#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
@@ -205,7 +205,7 @@
205 */ 205 */
206static inline uint64_t pte_to_entrylo(unsigned long pte_val) 206static inline uint64_t pte_to_entrylo(unsigned long pte_val)
207{ 207{
208#ifdef CONFIG_CPU_MIPSR2 208#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
209 if (cpu_has_rixi) { 209 if (cpu_has_rixi) {
210 int sa; 210 int sa;
211#ifdef CONFIG_32BIT 211#ifdef CONFIG_32BIT