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authorRalf Baechle <ralf@linux-mips.org>2012-09-27 12:00:07 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-09-27 12:00:07 -0400
commit9b11d4370c3a425e18ffccc1e93062864eca7337 (patch)
tree8d47c82a6a612e3b1ff56e2fa40af44223e676ed /arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
parent1e2038b770e73095e045d5fee7b276c4482f3cfe (diff)
parentc9f0f0c0e139f84dbfdfa51a66dbfd35f9b7d5b0 (diff)
Merge branch 'cn68xx-ciu2' of git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-uctlx-defs.h')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-uctlx-defs.h268
1 files changed, 241 insertions, 27 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
index 594f1b68cd62..bc5b80c6bbe2 100644
--- a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2012 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -25,8 +25,8 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27 27
28#ifndef __CVMX_UCTLX_TYPEDEFS_H__ 28#ifndef __CVMX_UCTLX_DEFS_H__
29#define __CVMX_UCTLX_TYPEDEFS_H__ 29#define __CVMX_UCTLX_DEFS_H__
30 30
31#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) 31#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
32#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) 32#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
@@ -45,6 +45,7 @@
45union cvmx_uctlx_bist_status { 45union cvmx_uctlx_bist_status {
46 uint64_t u64; 46 uint64_t u64;
47 struct cvmx_uctlx_bist_status_s { 47 struct cvmx_uctlx_bist_status_s {
48#ifdef __BIG_ENDIAN_BITFIELD
48 uint64_t reserved_6_63:58; 49 uint64_t reserved_6_63:58;
49 uint64_t data_bis:1; 50 uint64_t data_bis:1;
50 uint64_t desc_bis:1; 51 uint64_t desc_bis:1;
@@ -52,14 +53,29 @@ union cvmx_uctlx_bist_status {
52 uint64_t orbm_bis:1; 53 uint64_t orbm_bis:1;
53 uint64_t wrbm_bis:1; 54 uint64_t wrbm_bis:1;
54 uint64_t ppaf_bis:1; 55 uint64_t ppaf_bis:1;
56#else
57 uint64_t ppaf_bis:1;
58 uint64_t wrbm_bis:1;
59 uint64_t orbm_bis:1;
60 uint64_t erbm_bis:1;
61 uint64_t desc_bis:1;
62 uint64_t data_bis:1;
63 uint64_t reserved_6_63:58;
64#endif
55 } s; 65 } s;
56 struct cvmx_uctlx_bist_status_s cn63xx; 66 struct cvmx_uctlx_bist_status_s cn61xx;
57 struct cvmx_uctlx_bist_status_s cn63xxp1; 67 struct cvmx_uctlx_bist_status_s cn63xx;
68 struct cvmx_uctlx_bist_status_s cn63xxp1;
69 struct cvmx_uctlx_bist_status_s cn66xx;
70 struct cvmx_uctlx_bist_status_s cn68xx;
71 struct cvmx_uctlx_bist_status_s cn68xxp1;
72 struct cvmx_uctlx_bist_status_s cnf71xx;
58}; 73};
59 74
60union cvmx_uctlx_clk_rst_ctl { 75union cvmx_uctlx_clk_rst_ctl {
61 uint64_t u64; 76 uint64_t u64;
62 struct cvmx_uctlx_clk_rst_ctl_s { 77 struct cvmx_uctlx_clk_rst_ctl_s {
78#ifdef __BIG_ENDIAN_BITFIELD
63 uint64_t reserved_25_63:39; 79 uint64_t reserved_25_63:39;
64 uint64_t clear_bist:1; 80 uint64_t clear_bist:1;
65 uint64_t start_bist:1; 81 uint64_t start_bist:1;
@@ -81,14 +97,43 @@ union cvmx_uctlx_clk_rst_ctl {
81 uint64_t p_por:1; 97 uint64_t p_por:1;
82 uint64_t p_prst:1; 98 uint64_t p_prst:1;
83 uint64_t hrst:1; 99 uint64_t hrst:1;
100#else
101 uint64_t hrst:1;
102 uint64_t p_prst:1;
103 uint64_t p_por:1;
104 uint64_t p_com_on:1;
105 uint64_t reserved_4_4:1;
106 uint64_t p_refclk_div:2;
107 uint64_t p_refclk_sel:2;
108 uint64_t h_div:4;
109 uint64_t o_clkdiv_en:1;
110 uint64_t h_clkdiv_en:1;
111 uint64_t h_clkdiv_rst:1;
112 uint64_t h_clkdiv_byp:1;
113 uint64_t o_clkdiv_rst:1;
114 uint64_t app_start_clk:1;
115 uint64_t ohci_susp_lgcy:1;
116 uint64_t ohci_sm:1;
117 uint64_t ohci_clkcktrst:1;
118 uint64_t ehci_sm:1;
119 uint64_t start_bist:1;
120 uint64_t clear_bist:1;
121 uint64_t reserved_25_63:39;
122#endif
84 } s; 123 } s;
85 struct cvmx_uctlx_clk_rst_ctl_s cn63xx; 124 struct cvmx_uctlx_clk_rst_ctl_s cn61xx;
86 struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; 125 struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
126 struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
127 struct cvmx_uctlx_clk_rst_ctl_s cn66xx;
128 struct cvmx_uctlx_clk_rst_ctl_s cn68xx;
129 struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1;
130 struct cvmx_uctlx_clk_rst_ctl_s cnf71xx;
87}; 131};
88 132
89union cvmx_uctlx_ehci_ctl { 133union cvmx_uctlx_ehci_ctl {
90 uint64_t u64; 134 uint64_t u64;
91 struct cvmx_uctlx_ehci_ctl_s { 135 struct cvmx_uctlx_ehci_ctl_s {
136#ifdef __BIG_ENDIAN_BITFIELD
92 uint64_t reserved_20_63:44; 137 uint64_t reserved_20_63:44;
93 uint64_t desc_rbm:1; 138 uint64_t desc_rbm:1;
94 uint64_t reg_nb:1; 139 uint64_t reg_nb:1;
@@ -101,45 +146,96 @@ union cvmx_uctlx_ehci_ctl {
101 uint64_t inv_reg_a2:1; 146 uint64_t inv_reg_a2:1;
102 uint64_t ehci_64b_addr_en:1; 147 uint64_t ehci_64b_addr_en:1;
103 uint64_t l2c_addr_msb:8; 148 uint64_t l2c_addr_msb:8;
149#else
150 uint64_t l2c_addr_msb:8;
151 uint64_t ehci_64b_addr_en:1;
152 uint64_t inv_reg_a2:1;
153 uint64_t l2c_desc_emod:2;
154 uint64_t l2c_buff_emod:2;
155 uint64_t l2c_stt:1;
156 uint64_t l2c_0pag:1;
157 uint64_t l2c_bc:1;
158 uint64_t l2c_dc:1;
159 uint64_t reg_nb:1;
160 uint64_t desc_rbm:1;
161 uint64_t reserved_20_63:44;
162#endif
104 } s; 163 } s;
105 struct cvmx_uctlx_ehci_ctl_s cn63xx; 164 struct cvmx_uctlx_ehci_ctl_s cn61xx;
106 struct cvmx_uctlx_ehci_ctl_s cn63xxp1; 165 struct cvmx_uctlx_ehci_ctl_s cn63xx;
166 struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
167 struct cvmx_uctlx_ehci_ctl_s cn66xx;
168 struct cvmx_uctlx_ehci_ctl_s cn68xx;
169 struct cvmx_uctlx_ehci_ctl_s cn68xxp1;
170 struct cvmx_uctlx_ehci_ctl_s cnf71xx;
107}; 171};
108 172
109union cvmx_uctlx_ehci_fla { 173union cvmx_uctlx_ehci_fla {
110 uint64_t u64; 174 uint64_t u64;
111 struct cvmx_uctlx_ehci_fla_s { 175 struct cvmx_uctlx_ehci_fla_s {
176#ifdef __BIG_ENDIAN_BITFIELD
112 uint64_t reserved_6_63:58; 177 uint64_t reserved_6_63:58;
113 uint64_t fla:6; 178 uint64_t fla:6;
179#else
180 uint64_t fla:6;
181 uint64_t reserved_6_63:58;
182#endif
114 } s; 183 } s;
115 struct cvmx_uctlx_ehci_fla_s cn63xx; 184 struct cvmx_uctlx_ehci_fla_s cn61xx;
116 struct cvmx_uctlx_ehci_fla_s cn63xxp1; 185 struct cvmx_uctlx_ehci_fla_s cn63xx;
186 struct cvmx_uctlx_ehci_fla_s cn63xxp1;
187 struct cvmx_uctlx_ehci_fla_s cn66xx;
188 struct cvmx_uctlx_ehci_fla_s cn68xx;
189 struct cvmx_uctlx_ehci_fla_s cn68xxp1;
190 struct cvmx_uctlx_ehci_fla_s cnf71xx;
117}; 191};
118 192
119union cvmx_uctlx_erto_ctl { 193union cvmx_uctlx_erto_ctl {
120 uint64_t u64; 194 uint64_t u64;
121 struct cvmx_uctlx_erto_ctl_s { 195 struct cvmx_uctlx_erto_ctl_s {
196#ifdef __BIG_ENDIAN_BITFIELD
122 uint64_t reserved_32_63:32; 197 uint64_t reserved_32_63:32;
123 uint64_t to_val:27; 198 uint64_t to_val:27;
124 uint64_t reserved_0_4:5; 199 uint64_t reserved_0_4:5;
200#else
201 uint64_t reserved_0_4:5;
202 uint64_t to_val:27;
203 uint64_t reserved_32_63:32;
204#endif
125 } s; 205 } s;
126 struct cvmx_uctlx_erto_ctl_s cn63xx; 206 struct cvmx_uctlx_erto_ctl_s cn61xx;
127 struct cvmx_uctlx_erto_ctl_s cn63xxp1; 207 struct cvmx_uctlx_erto_ctl_s cn63xx;
208 struct cvmx_uctlx_erto_ctl_s cn63xxp1;
209 struct cvmx_uctlx_erto_ctl_s cn66xx;
210 struct cvmx_uctlx_erto_ctl_s cn68xx;
211 struct cvmx_uctlx_erto_ctl_s cn68xxp1;
212 struct cvmx_uctlx_erto_ctl_s cnf71xx;
128}; 213};
129 214
130union cvmx_uctlx_if_ena { 215union cvmx_uctlx_if_ena {
131 uint64_t u64; 216 uint64_t u64;
132 struct cvmx_uctlx_if_ena_s { 217 struct cvmx_uctlx_if_ena_s {
218#ifdef __BIG_ENDIAN_BITFIELD
133 uint64_t reserved_1_63:63; 219 uint64_t reserved_1_63:63;
134 uint64_t en:1; 220 uint64_t en:1;
221#else
222 uint64_t en:1;
223 uint64_t reserved_1_63:63;
224#endif
135 } s; 225 } s;
136 struct cvmx_uctlx_if_ena_s cn63xx; 226 struct cvmx_uctlx_if_ena_s cn61xx;
137 struct cvmx_uctlx_if_ena_s cn63xxp1; 227 struct cvmx_uctlx_if_ena_s cn63xx;
228 struct cvmx_uctlx_if_ena_s cn63xxp1;
229 struct cvmx_uctlx_if_ena_s cn66xx;
230 struct cvmx_uctlx_if_ena_s cn68xx;
231 struct cvmx_uctlx_if_ena_s cn68xxp1;
232 struct cvmx_uctlx_if_ena_s cnf71xx;
138}; 233};
139 234
140union cvmx_uctlx_int_ena { 235union cvmx_uctlx_int_ena {
141 uint64_t u64; 236 uint64_t u64;
142 struct cvmx_uctlx_int_ena_s { 237 struct cvmx_uctlx_int_ena_s {
238#ifdef __BIG_ENDIAN_BITFIELD
143 uint64_t reserved_8_63:56; 239 uint64_t reserved_8_63:56;
144 uint64_t ec_ovf_e:1; 240 uint64_t ec_ovf_e:1;
145 uint64_t oc_ovf_e:1; 241 uint64_t oc_ovf_e:1;
@@ -149,14 +245,31 @@ union cvmx_uctlx_int_ena {
149 uint64_t or_psh_f:1; 245 uint64_t or_psh_f:1;
150 uint64_t er_psh_f:1; 246 uint64_t er_psh_f:1;
151 uint64_t pp_psh_f:1; 247 uint64_t pp_psh_f:1;
248#else
249 uint64_t pp_psh_f:1;
250 uint64_t er_psh_f:1;
251 uint64_t or_psh_f:1;
252 uint64_t cf_psh_f:1;
253 uint64_t wb_psh_f:1;
254 uint64_t wb_pop_e:1;
255 uint64_t oc_ovf_e:1;
256 uint64_t ec_ovf_e:1;
257 uint64_t reserved_8_63:56;
258#endif
152 } s; 259 } s;
153 struct cvmx_uctlx_int_ena_s cn63xx; 260 struct cvmx_uctlx_int_ena_s cn61xx;
154 struct cvmx_uctlx_int_ena_s cn63xxp1; 261 struct cvmx_uctlx_int_ena_s cn63xx;
262 struct cvmx_uctlx_int_ena_s cn63xxp1;
263 struct cvmx_uctlx_int_ena_s cn66xx;
264 struct cvmx_uctlx_int_ena_s cn68xx;
265 struct cvmx_uctlx_int_ena_s cn68xxp1;
266 struct cvmx_uctlx_int_ena_s cnf71xx;
155}; 267};
156 268
157union cvmx_uctlx_int_reg { 269union cvmx_uctlx_int_reg {
158 uint64_t u64; 270 uint64_t u64;
159 struct cvmx_uctlx_int_reg_s { 271 struct cvmx_uctlx_int_reg_s {
272#ifdef __BIG_ENDIAN_BITFIELD
160 uint64_t reserved_8_63:56; 273 uint64_t reserved_8_63:56;
161 uint64_t ec_ovf_e:1; 274 uint64_t ec_ovf_e:1;
162 uint64_t oc_ovf_e:1; 275 uint64_t oc_ovf_e:1;
@@ -166,14 +279,31 @@ union cvmx_uctlx_int_reg {
166 uint64_t or_psh_f:1; 279 uint64_t or_psh_f:1;
167 uint64_t er_psh_f:1; 280 uint64_t er_psh_f:1;
168 uint64_t pp_psh_f:1; 281 uint64_t pp_psh_f:1;
282#else
283 uint64_t pp_psh_f:1;
284 uint64_t er_psh_f:1;
285 uint64_t or_psh_f:1;
286 uint64_t cf_psh_f:1;
287 uint64_t wb_psh_f:1;
288 uint64_t wb_pop_e:1;
289 uint64_t oc_ovf_e:1;
290 uint64_t ec_ovf_e:1;
291 uint64_t reserved_8_63:56;
292#endif
169 } s; 293 } s;
170 struct cvmx_uctlx_int_reg_s cn63xx; 294 struct cvmx_uctlx_int_reg_s cn61xx;
171 struct cvmx_uctlx_int_reg_s cn63xxp1; 295 struct cvmx_uctlx_int_reg_s cn63xx;
296 struct cvmx_uctlx_int_reg_s cn63xxp1;
297 struct cvmx_uctlx_int_reg_s cn66xx;
298 struct cvmx_uctlx_int_reg_s cn68xx;
299 struct cvmx_uctlx_int_reg_s cn68xxp1;
300 struct cvmx_uctlx_int_reg_s cnf71xx;
172}; 301};
173 302
174union cvmx_uctlx_ohci_ctl { 303union cvmx_uctlx_ohci_ctl {
175 uint64_t u64; 304 uint64_t u64;
176 struct cvmx_uctlx_ohci_ctl_s { 305 struct cvmx_uctlx_ohci_ctl_s {
306#ifdef __BIG_ENDIAN_BITFIELD
177 uint64_t reserved_19_63:45; 307 uint64_t reserved_19_63:45;
178 uint64_t reg_nb:1; 308 uint64_t reg_nb:1;
179 uint64_t l2c_dc:1; 309 uint64_t l2c_dc:1;
@@ -185,35 +315,73 @@ union cvmx_uctlx_ohci_ctl {
185 uint64_t inv_reg_a2:1; 315 uint64_t inv_reg_a2:1;
186 uint64_t reserved_8_8:1; 316 uint64_t reserved_8_8:1;
187 uint64_t l2c_addr_msb:8; 317 uint64_t l2c_addr_msb:8;
318#else
319 uint64_t l2c_addr_msb:8;
320 uint64_t reserved_8_8:1;
321 uint64_t inv_reg_a2:1;
322 uint64_t l2c_desc_emod:2;
323 uint64_t l2c_buff_emod:2;
324 uint64_t l2c_stt:1;
325 uint64_t l2c_0pag:1;
326 uint64_t l2c_bc:1;
327 uint64_t l2c_dc:1;
328 uint64_t reg_nb:1;
329 uint64_t reserved_19_63:45;
330#endif
188 } s; 331 } s;
189 struct cvmx_uctlx_ohci_ctl_s cn63xx; 332 struct cvmx_uctlx_ohci_ctl_s cn61xx;
190 struct cvmx_uctlx_ohci_ctl_s cn63xxp1; 333 struct cvmx_uctlx_ohci_ctl_s cn63xx;
334 struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
335 struct cvmx_uctlx_ohci_ctl_s cn66xx;
336 struct cvmx_uctlx_ohci_ctl_s cn68xx;
337 struct cvmx_uctlx_ohci_ctl_s cn68xxp1;
338 struct cvmx_uctlx_ohci_ctl_s cnf71xx;
191}; 339};
192 340
193union cvmx_uctlx_orto_ctl { 341union cvmx_uctlx_orto_ctl {
194 uint64_t u64; 342 uint64_t u64;
195 struct cvmx_uctlx_orto_ctl_s { 343 struct cvmx_uctlx_orto_ctl_s {
344#ifdef __BIG_ENDIAN_BITFIELD
196 uint64_t reserved_32_63:32; 345 uint64_t reserved_32_63:32;
197 uint64_t to_val:24; 346 uint64_t to_val:24;
198 uint64_t reserved_0_7:8; 347 uint64_t reserved_0_7:8;
348#else
349 uint64_t reserved_0_7:8;
350 uint64_t to_val:24;
351 uint64_t reserved_32_63:32;
352#endif
199 } s; 353 } s;
200 struct cvmx_uctlx_orto_ctl_s cn63xx; 354 struct cvmx_uctlx_orto_ctl_s cn61xx;
201 struct cvmx_uctlx_orto_ctl_s cn63xxp1; 355 struct cvmx_uctlx_orto_ctl_s cn63xx;
356 struct cvmx_uctlx_orto_ctl_s cn63xxp1;
357 struct cvmx_uctlx_orto_ctl_s cn66xx;
358 struct cvmx_uctlx_orto_ctl_s cn68xx;
359 struct cvmx_uctlx_orto_ctl_s cn68xxp1;
360 struct cvmx_uctlx_orto_ctl_s cnf71xx;
202}; 361};
203 362
204union cvmx_uctlx_ppaf_wm { 363union cvmx_uctlx_ppaf_wm {
205 uint64_t u64; 364 uint64_t u64;
206 struct cvmx_uctlx_ppaf_wm_s { 365 struct cvmx_uctlx_ppaf_wm_s {
366#ifdef __BIG_ENDIAN_BITFIELD
207 uint64_t reserved_5_63:59; 367 uint64_t reserved_5_63:59;
208 uint64_t wm:5; 368 uint64_t wm:5;
369#else
370 uint64_t wm:5;
371 uint64_t reserved_5_63:59;
372#endif
209 } s; 373 } s;
210 struct cvmx_uctlx_ppaf_wm_s cn63xx; 374 struct cvmx_uctlx_ppaf_wm_s cn61xx;
211 struct cvmx_uctlx_ppaf_wm_s cn63xxp1; 375 struct cvmx_uctlx_ppaf_wm_s cn63xx;
376 struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
377 struct cvmx_uctlx_ppaf_wm_s cn66xx;
378 struct cvmx_uctlx_ppaf_wm_s cnf71xx;
212}; 379};
213 380
214union cvmx_uctlx_uphy_ctl_status { 381union cvmx_uctlx_uphy_ctl_status {
215 uint64_t u64; 382 uint64_t u64;
216 struct cvmx_uctlx_uphy_ctl_status_s { 383 struct cvmx_uctlx_uphy_ctl_status_s {
384#ifdef __BIG_ENDIAN_BITFIELD
217 uint64_t reserved_10_63:54; 385 uint64_t reserved_10_63:54;
218 uint64_t bist_done:1; 386 uint64_t bist_done:1;
219 uint64_t bist_err:1; 387 uint64_t bist_err:1;
@@ -225,14 +393,33 @@ union cvmx_uctlx_uphy_ctl_status {
225 uint64_t uphy_bist:1; 393 uint64_t uphy_bist:1;
226 uint64_t bist_en:1; 394 uint64_t bist_en:1;
227 uint64_t ate_reset:1; 395 uint64_t ate_reset:1;
396#else
397 uint64_t ate_reset:1;
398 uint64_t bist_en:1;
399 uint64_t uphy_bist:1;
400 uint64_t vtest_en:1;
401 uint64_t siddq:1;
402 uint64_t lsbist:1;
403 uint64_t fsbist:1;
404 uint64_t hsbist:1;
405 uint64_t bist_err:1;
406 uint64_t bist_done:1;
407 uint64_t reserved_10_63:54;
408#endif
228 } s; 409 } s;
229 struct cvmx_uctlx_uphy_ctl_status_s cn63xx; 410 struct cvmx_uctlx_uphy_ctl_status_s cn61xx;
230 struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; 411 struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
412 struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
413 struct cvmx_uctlx_uphy_ctl_status_s cn66xx;
414 struct cvmx_uctlx_uphy_ctl_status_s cn68xx;
415 struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1;
416 struct cvmx_uctlx_uphy_ctl_status_s cnf71xx;
231}; 417};
232 418
233union cvmx_uctlx_uphy_portx_ctl_status { 419union cvmx_uctlx_uphy_portx_ctl_status {
234 uint64_t u64; 420 uint64_t u64;
235 struct cvmx_uctlx_uphy_portx_ctl_status_s { 421 struct cvmx_uctlx_uphy_portx_ctl_status_s {
422#ifdef __BIG_ENDIAN_BITFIELD
236 uint64_t reserved_43_63:21; 423 uint64_t reserved_43_63:21;
237 uint64_t tdata_out:4; 424 uint64_t tdata_out:4;
238 uint64_t txbiststuffenh:1; 425 uint64_t txbiststuffenh:1;
@@ -253,9 +440,36 @@ union cvmx_uctlx_uphy_portx_ctl_status {
253 uint64_t tdata_sel:1; 440 uint64_t tdata_sel:1;
254 uint64_t taddr_in:4; 441 uint64_t taddr_in:4;
255 uint64_t tdata_in:8; 442 uint64_t tdata_in:8;
443#else
444 uint64_t tdata_in:8;
445 uint64_t taddr_in:4;
446 uint64_t tdata_sel:1;
447 uint64_t tclk:1;
448 uint64_t loop_en:1;
449 uint64_t compdistune:3;
450 uint64_t sqrxtune:3;
451 uint64_t txfslstune:4;
452 uint64_t txpreemphasistune:1;
453 uint64_t txrisetune:1;
454 uint64_t txvreftune:4;
455 uint64_t txhsvxtune:2;
456 uint64_t portreset:1;
457 uint64_t vbusvldext:1;
458 uint64_t dppulldown:1;
459 uint64_t dmpulldown:1;
460 uint64_t txbiststuffen:1;
461 uint64_t txbiststuffenh:1;
462 uint64_t tdata_out:4;
463 uint64_t reserved_43_63:21;
464#endif
256 } s; 465 } s;
466 struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx;
257 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; 467 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
258 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; 468 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
469 struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx;
470 struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx;
471 struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1;
472 struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx;
259}; 473};
260 474
261#endif 475#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 02:41:31 -0500