MIPS: OCTEON: Update register definitions.

Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.

Add little-endian register layouts.

Patch cvmx-interrupt-rsl.c for changed definition.

Signed-off-by: David Daney <david.daney@cavium.com>

1 files changed, 410 insertions, 1 deletions

diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
index c34ad04789ce..dd5b0428de35 100644
--- a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2011 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -55,52 +55,107 @@
 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
+static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
+{
+        switch (cvmx_get_octeon_family()) {
+        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
+                        return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
+
+                if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
+                        return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+                return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
+        }
+        return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
+}
+
 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
 
 union cvmx_dpi_bist_status {
         uint64_t u64;
         struct cvmx_dpi_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_47_63:17;
                 uint64_t bist:47;
+#else
+                uint64_t bist:47;
+                uint64_t reserved_47_63:17;
+#endif
         } s;
         struct cvmx_dpi_bist_status_s cn61xx;
         struct cvmx_dpi_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_45_63:19;
                 uint64_t bist:45;
+#else
+                uint64_t bist:45;
+                uint64_t reserved_45_63:19;
+#endif
         } cn63xx;
         struct cvmx_dpi_bist_status_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_37_63:27;
                 uint64_t bist:37;
+#else
+                uint64_t bist:37;
+                uint64_t reserved_37_63:27;
+#endif
         } cn63xxp1;
         struct cvmx_dpi_bist_status_s cn66xx;
         struct cvmx_dpi_bist_status_cn63xx cn68xx;
         struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
+        struct cvmx_dpi_bist_status_s cnf71xx;
 };
 
 union cvmx_dpi_ctl {
         uint64_t u64;
         struct cvmx_dpi_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t clk:1;
                 uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t clk:1;
+                uint64_t reserved_2_63:62;
+#endif
         } s;
         struct cvmx_dpi_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t en:1;
+#else
+                uint64_t en:1;
+                uint64_t reserved_1_63:63;
+#endif
         } cn61xx;
         struct cvmx_dpi_ctl_s cn63xx;
         struct cvmx_dpi_ctl_s cn63xxp1;
         struct cvmx_dpi_ctl_s cn66xx;
         struct cvmx_dpi_ctl_s cn68xx;
         struct cvmx_dpi_ctl_s cn68xxp1;
+        struct cvmx_dpi_ctl_cn61xx cnf71xx;
 };
 
 union cvmx_dpi_dmax_counts {
         uint64_t u64;
         struct cvmx_dpi_dmax_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_39_63:25;
                 uint64_t fcnt:7;
                 uint64_t dbell:32;
+#else
+                uint64_t dbell:32;
+                uint64_t fcnt:7;
+                uint64_t reserved_39_63:25;
+#endif
         } s;
         struct cvmx_dpi_dmax_counts_s cn61xx;
         struct cvmx_dpi_dmax_counts_s cn63xx;
@@ -108,13 +163,19 @@ union cvmx_dpi_dmax_counts {
         struct cvmx_dpi_dmax_counts_s cn66xx;
         struct cvmx_dpi_dmax_counts_s cn68xx;
         struct cvmx_dpi_dmax_counts_s cn68xxp1;
+        struct cvmx_dpi_dmax_counts_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_dbell {
         uint64_t u64;
         struct cvmx_dpi_dmax_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t dbell:16;
+#else
+                uint64_t dbell:16;
+                uint64_t reserved_16_63:48;
+#endif
         } s;
         struct cvmx_dpi_dmax_dbell_s cn61xx;
         struct cvmx_dpi_dmax_dbell_s cn63xx;
@@ -122,31 +183,48 @@ union cvmx_dpi_dmax_dbell {
         struct cvmx_dpi_dmax_dbell_s cn66xx;
         struct cvmx_dpi_dmax_dbell_s cn68xx;
         struct cvmx_dpi_dmax_dbell_s cn68xxp1;
+        struct cvmx_dpi_dmax_dbell_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_err_rsp_status {
         uint64_t u64;
         struct cvmx_dpi_dmax_err_rsp_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t status:6;
+#else
+                uint64_t status:6;
+                uint64_t reserved_6_63:58;
+#endif
         } s;
         struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
         struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
         struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
         struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
+        struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_ibuff_saddr {
         uint64_t u64;
         struct cvmx_dpi_dmax_ibuff_saddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t csize:14;
                 uint64_t reserved_41_47:7;
                 uint64_t idle:1;
                 uint64_t saddr:33;
                 uint64_t reserved_0_6:7;
+#else
+                uint64_t reserved_0_6:7;
+                uint64_t saddr:33;
+                uint64_t idle:1;
+                uint64_t reserved_41_47:7;
+                uint64_t csize:14;
+                uint64_t reserved_62_63:2;
+#endif
         } s;
         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t csize:14;
                 uint64_t reserved_41_47:7;
@@ -154,47 +232,78 @@ union cvmx_dpi_dmax_ibuff_saddr {
                 uint64_t reserved_36_39:4;
                 uint64_t saddr:29;
                 uint64_t reserved_0_6:7;
+#else
+                uint64_t reserved_0_6:7;
+                uint64_t saddr:29;
+                uint64_t reserved_36_39:4;
+                uint64_t idle:1;
+                uint64_t reserved_41_47:7;
+                uint64_t csize:14;
+                uint64_t reserved_62_63:2;
+#endif
         } cn61xx;
         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
         struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
         struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
 };
 
 union cvmx_dpi_dmax_iflight {
         uint64_t u64;
         struct cvmx_dpi_dmax_iflight_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t cnt:3;
+#else
+                uint64_t cnt:3;
+                uint64_t reserved_3_63:61;
+#endif
         } s;
         struct cvmx_dpi_dmax_iflight_s cn61xx;
         struct cvmx_dpi_dmax_iflight_s cn66xx;
         struct cvmx_dpi_dmax_iflight_s cn68xx;
         struct cvmx_dpi_dmax_iflight_s cn68xxp1;
+        struct cvmx_dpi_dmax_iflight_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_naddr {
         uint64_t u64;
         struct cvmx_dpi_dmax_naddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t reserved_40_63:24;
+#endif
         } s;
         struct cvmx_dpi_dmax_naddr_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t addr:36;
+#else
+                uint64_t addr:36;
+                uint64_t reserved_36_63:28;
+#endif
         } cn61xx;
         struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
         struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
         struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
         struct cvmx_dpi_dmax_naddr_s cn68xx;
         struct cvmx_dpi_dmax_naddr_s cn68xxp1;
+        struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
 };
 
 union cvmx_dpi_dmax_reqbnk0 {
         uint64_t u64;
         struct cvmx_dpi_dmax_reqbnk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t state:64;
+#else
+                uint64_t state:64;
+#endif
         } s;
         struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
         struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
@@ -202,12 +311,17 @@ union cvmx_dpi_dmax_reqbnk0 {
         struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
         struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
         struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
+        struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
 };
 
 union cvmx_dpi_dmax_reqbnk1 {
         uint64_t u64;
         struct cvmx_dpi_dmax_reqbnk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+                uint64_t state:64;
+#else
                 uint64_t state:64;
+#endif
         } s;
         struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
         struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
@@ -215,11 +329,13 @@ union cvmx_dpi_dmax_reqbnk1 {
         struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
         struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
         struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
+        struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
 };
 
 union cvmx_dpi_dma_control {
         uint64_t u64;
         struct cvmx_dpi_dma_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t dici_mode:1;
                 uint64_t pkt_en1:1;
@@ -240,9 +356,32 @@ union cvmx_dpi_dma_control {
                 uint64_t o_es:2;
                 uint64_t o_mode:1;
                 uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t reserved_34_47:14;
+                uint64_t dma_enb:6;
+                uint64_t reserved_54_55:2;
+                uint64_t pkt_en:1;
+                uint64_t pkt_hp:1;
+                uint64_t commit_mode:1;
+                uint64_t ffp_dis:1;
+                uint64_t pkt_en1:1;
+                uint64_t dici_mode:1;
+                uint64_t reserved_62_63:2;
+#endif
         } s;
         struct cvmx_dpi_dma_control_s cn61xx;
         struct cvmx_dpi_dma_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_61_63:3;
                 uint64_t pkt_en1:1;
                 uint64_t ffp_dis:1;
@@ -262,8 +401,30 @@ union cvmx_dpi_dma_control {
                 uint64_t o_es:2;
                 uint64_t o_mode:1;
                 uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t reserved_34_47:14;
+                uint64_t dma_enb:6;
+                uint64_t reserved_54_55:2;
+                uint64_t pkt_en:1;
+                uint64_t pkt_hp:1;
+                uint64_t commit_mode:1;
+                uint64_t ffp_dis:1;
+                uint64_t pkt_en1:1;
+                uint64_t reserved_61_63:3;
+#endif
         } cn63xx;
         struct cvmx_dpi_dma_control_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t commit_mode:1;
                 uint64_t pkt_hp:1;
@@ -281,17 +442,42 @@ union cvmx_dpi_dma_control {
                 uint64_t o_es:2;
                 uint64_t o_mode:1;
                 uint64_t reserved_0_13:14;
+#else
+                uint64_t reserved_0_13:14;
+                uint64_t o_mode:1;
+                uint64_t o_es:2;
+                uint64_t o_ns:1;
+                uint64_t o_ro:1;
+                uint64_t o_add1:1;
+                uint64_t fpa_que:3;
+                uint64_t dwb_ichk:9;
+                uint64_t dwb_denb:1;
+                uint64_t b0_lend:1;
+                uint64_t reserved_34_47:14;
+                uint64_t dma_enb:6;
+                uint64_t reserved_54_55:2;
+                uint64_t pkt_en:1;
+                uint64_t pkt_hp:1;
+                uint64_t commit_mode:1;
+                uint64_t reserved_59_63:5;
+#endif
         } cn63xxp1;
         struct cvmx_dpi_dma_control_cn63xx cn66xx;
         struct cvmx_dpi_dma_control_s cn68xx;
         struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
+        struct cvmx_dpi_dma_control_s cnf71xx;
 };
 
 union cvmx_dpi_dma_engx_en {
         uint64_t u64;
         struct cvmx_dpi_dma_engx_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t qen:8;
+#else
+                uint64_t qen:8;
+                uint64_t reserved_8_63:56;
+#endif
         } s;
         struct cvmx_dpi_dma_engx_en_s cn61xx;
         struct cvmx_dpi_dma_engx_en_s cn63xx;
@@ -299,63 +485,101 @@ union cvmx_dpi_dma_engx_en {
         struct cvmx_dpi_dma_engx_en_s cn66xx;
         struct cvmx_dpi_dma_engx_en_s cn68xx;
         struct cvmx_dpi_dma_engx_en_s cn68xxp1;
+        struct cvmx_dpi_dma_engx_en_s cnf71xx;
 };
 
 union cvmx_dpi_dma_ppx_cnt {
         uint64_t u64;
         struct cvmx_dpi_dma_ppx_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt:16;
+#else
+                uint64_t cnt:16;
+                uint64_t reserved_16_63:48;
+#endif
         } s;
         struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
         struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
+        struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
 };
 
 union cvmx_dpi_engx_buf {
         uint64_t u64;
         struct cvmx_dpi_engx_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_37_63:27;
                 uint64_t compblks:5;
                 uint64_t reserved_9_31:23;
                 uint64_t base:5;
                 uint64_t blks:4;
+#else
+                uint64_t blks:4;
+                uint64_t base:5;
+                uint64_t reserved_9_31:23;
+                uint64_t compblks:5;
+                uint64_t reserved_37_63:27;
+#endif
         } s;
         struct cvmx_dpi_engx_buf_s cn61xx;
         struct cvmx_dpi_engx_buf_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t base:4;
                 uint64_t blks:4;
+#else
+                uint64_t blks:4;
+                uint64_t base:4;
+                uint64_t reserved_8_63:56;
+#endif
         } cn63xx;
         struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
         struct cvmx_dpi_engx_buf_s cn66xx;
         struct cvmx_dpi_engx_buf_s cn68xx;
         struct cvmx_dpi_engx_buf_s cn68xxp1;
+        struct cvmx_dpi_engx_buf_s cnf71xx;
 };
 
 union cvmx_dpi_info_reg {
         uint64_t u64;
         struct cvmx_dpi_info_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ffp:4;
                 uint64_t reserved_2_3:2;
                 uint64_t ncb:1;
                 uint64_t rsl:1;
+#else
+                uint64_t rsl:1;
+                uint64_t ncb:1;
+                uint64_t reserved_2_3:2;
+                uint64_t ffp:4;
+                uint64_t reserved_8_63:56;
+#endif
         } s;
         struct cvmx_dpi_info_reg_s cn61xx;
         struct cvmx_dpi_info_reg_s cn63xx;
         struct cvmx_dpi_info_reg_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t ncb:1;
                 uint64_t rsl:1;
+#else
+                uint64_t rsl:1;
+                uint64_t ncb:1;
+                uint64_t reserved_2_63:62;
+#endif
         } cn63xxp1;
         struct cvmx_dpi_info_reg_s cn66xx;
         struct cvmx_dpi_info_reg_s cn68xx;
         struct cvmx_dpi_info_reg_s cn68xxp1;
+        struct cvmx_dpi_info_reg_s cnf71xx;
 };
 
 union cvmx_dpi_int_en {
         uint64_t u64;
         struct cvmx_dpi_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t sprt3_rst:1;
                 uint64_t sprt2_rst:1;
@@ -373,9 +597,29 @@ union cvmx_dpi_int_en {
                 uint64_t reserved_2_7:6;
                 uint64_t nfovr:1;
                 uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt3_rst:1;
+                uint64_t reserved_28_63:36;
+#endif
         } s;
         struct cvmx_dpi_int_en_s cn61xx;
         struct cvmx_dpi_int_en_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_26_63:38;
                 uint64_t sprt1_rst:1;
                 uint64_t sprt0_rst:1;
@@ -391,16 +635,35 @@ union cvmx_dpi_int_en {
                 uint64_t reserved_2_7:6;
                 uint64_t nfovr:1;
                 uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t reserved_26_63:38;
+#endif
         } cn63xx;
         struct cvmx_dpi_int_en_cn63xx cn63xxp1;
         struct cvmx_dpi_int_en_s cn66xx;
         struct cvmx_dpi_int_en_cn63xx cn68xx;
         struct cvmx_dpi_int_en_cn63xx cn68xxp1;
+        struct cvmx_dpi_int_en_s cnf71xx;
 };
 
 union cvmx_dpi_int_reg {
         uint64_t u64;
         struct cvmx_dpi_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t sprt3_rst:1;
                 uint64_t sprt2_rst:1;
@@ -418,9 +681,29 @@ union cvmx_dpi_int_reg {
                 uint64_t reserved_2_7:6;
                 uint64_t nfovr:1;
                 uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt3_rst:1;
+                uint64_t reserved_28_63:36;
+#endif
         } s;
         struct cvmx_dpi_int_reg_s cn61xx;
         struct cvmx_dpi_int_reg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_26_63:38;
                 uint64_t sprt1_rst:1;
                 uint64_t sprt0_rst:1;
@@ -436,31 +719,62 @@ union cvmx_dpi_int_reg {
                 uint64_t reserved_2_7:6;
                 uint64_t nfovr:1;
                 uint64_t nderr:1;
+#else
+                uint64_t nderr:1;
+                uint64_t nfovr:1;
+                uint64_t reserved_2_7:6;
+                uint64_t dmadbo:8;
+                uint64_t req_badadr:1;
+                uint64_t req_badlen:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_undflw:1;
+                uint64_t req_anull:1;
+                uint64_t req_inull:1;
+                uint64_t req_badfil:1;
+                uint64_t reserved_23_23:1;
+                uint64_t sprt0_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t reserved_26_63:38;
+#endif
         } cn63xx;
         struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
         struct cvmx_dpi_int_reg_s cn66xx;
         struct cvmx_dpi_int_reg_cn63xx cn68xx;
         struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
+        struct cvmx_dpi_int_reg_s cnf71xx;
 };
 
 union cvmx_dpi_ncbx_cfg {
         uint64_t u64;
         struct cvmx_dpi_ncbx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t molr:6;
+#else
+                uint64_t molr:6;
+                uint64_t reserved_6_63:58;
+#endif
         } s;
         struct cvmx_dpi_ncbx_cfg_s cn61xx;
         struct cvmx_dpi_ncbx_cfg_s cn66xx;
         struct cvmx_dpi_ncbx_cfg_s cn68xx;
+        struct cvmx_dpi_ncbx_cfg_s cnf71xx;
 };
 
 union cvmx_dpi_pint_info {
         uint64_t u64;
         struct cvmx_dpi_pint_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t iinfo:6;
                 uint64_t reserved_6_7:2;
                 uint64_t sinfo:6;
+#else
+                uint64_t sinfo:6;
+                uint64_t reserved_6_7:2;
+                uint64_t iinfo:6;
+                uint64_t reserved_14_63:50;
+#endif
         } s;
         struct cvmx_dpi_pint_info_s cn61xx;
         struct cvmx_dpi_pint_info_s cn63xx;
@@ -468,13 +782,19 @@ union cvmx_dpi_pint_info {
         struct cvmx_dpi_pint_info_s cn66xx;
         struct cvmx_dpi_pint_info_s cn68xx;
         struct cvmx_dpi_pint_info_s cn68xxp1;
+        struct cvmx_dpi_pint_info_s cnf71xx;
 };
 
 union cvmx_dpi_pkt_err_rsp {
         uint64_t u64;
         struct cvmx_dpi_pkt_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t pkterr:1;
+#else
+                uint64_t pkterr:1;
+                uint64_t reserved_1_63:63;
+#endif
         } s;
         struct cvmx_dpi_pkt_err_rsp_s cn61xx;
         struct cvmx_dpi_pkt_err_rsp_s cn63xx;
@@ -482,13 +802,19 @@ union cvmx_dpi_pkt_err_rsp {
         struct cvmx_dpi_pkt_err_rsp_s cn66xx;
         struct cvmx_dpi_pkt_err_rsp_s cn68xx;
         struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
+        struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rsp {
         uint64_t u64;
         struct cvmx_dpi_req_err_rsp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t qerr:8;
+#else
+                uint64_t qerr:8;
+                uint64_t reserved_8_63:56;
+#endif
         } s;
         struct cvmx_dpi_req_err_rsp_s cn61xx;
         struct cvmx_dpi_req_err_rsp_s cn63xx;
@@ -496,13 +822,19 @@ union cvmx_dpi_req_err_rsp {
         struct cvmx_dpi_req_err_rsp_s cn66xx;
         struct cvmx_dpi_req_err_rsp_s cn68xx;
         struct cvmx_dpi_req_err_rsp_s cn68xxp1;
+        struct cvmx_dpi_req_err_rsp_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rsp_en {
         uint64_t u64;
         struct cvmx_dpi_req_err_rsp_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t en:8;
+#else
+                uint64_t en:8;
+                uint64_t reserved_8_63:56;
+#endif
         } s;
         struct cvmx_dpi_req_err_rsp_en_s cn61xx;
         struct cvmx_dpi_req_err_rsp_en_s cn63xx;
@@ -510,13 +842,19 @@ union cvmx_dpi_req_err_rsp_en {
         struct cvmx_dpi_req_err_rsp_en_s cn66xx;
         struct cvmx_dpi_req_err_rsp_en_s cn68xx;
         struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
+        struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rst {
         uint64_t u64;
         struct cvmx_dpi_req_err_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t qerr:8;
+#else
+                uint64_t qerr:8;
+                uint64_t reserved_8_63:56;
+#endif
         } s;
         struct cvmx_dpi_req_err_rst_s cn61xx;
         struct cvmx_dpi_req_err_rst_s cn63xx;
@@ -524,13 +862,19 @@ union cvmx_dpi_req_err_rst {
         struct cvmx_dpi_req_err_rst_s cn66xx;
         struct cvmx_dpi_req_err_rst_s cn68xx;
         struct cvmx_dpi_req_err_rst_s cn68xxp1;
+        struct cvmx_dpi_req_err_rst_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_rst_en {
         uint64_t u64;
         struct cvmx_dpi_req_err_rst_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t en:8;
+#else
+                uint64_t en:8;
+                uint64_t reserved_8_63:56;
+#endif
         } s;
         struct cvmx_dpi_req_err_rst_en_s cn61xx;
         struct cvmx_dpi_req_err_rst_en_s cn63xx;
@@ -538,27 +882,41 @@ union cvmx_dpi_req_err_rst_en {
         struct cvmx_dpi_req_err_rst_en_s cn66xx;
         struct cvmx_dpi_req_err_rst_en_s cn68xx;
         struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
+        struct cvmx_dpi_req_err_rst_en_s cnf71xx;
 };
 
 union cvmx_dpi_req_err_skip_comp {
         uint64_t u64;
         struct cvmx_dpi_req_err_skip_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t en_rst:8;
                 uint64_t reserved_8_15:8;
                 uint64_t en_rsp:8;
+#else
+                uint64_t en_rsp:8;
+                uint64_t reserved_8_15:8;
+                uint64_t en_rst:8;
+                uint64_t reserved_24_63:40;
+#endif
         } s;
         struct cvmx_dpi_req_err_skip_comp_s cn61xx;
         struct cvmx_dpi_req_err_skip_comp_s cn66xx;
         struct cvmx_dpi_req_err_skip_comp_s cn68xx;
         struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
+        struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
 };
 
 union cvmx_dpi_req_gbl_en {
         uint64_t u64;
         struct cvmx_dpi_req_gbl_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t qen:8;
+#else
+                uint64_t qen:8;
+                uint64_t reserved_8_63:56;
+#endif
         } s;
         struct cvmx_dpi_req_gbl_en_s cn61xx;
         struct cvmx_dpi_req_gbl_en_s cn63xx;
@@ -566,11 +924,13 @@ union cvmx_dpi_req_gbl_en {
         struct cvmx_dpi_req_gbl_en_s cn66xx;
         struct cvmx_dpi_req_gbl_en_s cn68xx;
         struct cvmx_dpi_req_gbl_en_s cn68xxp1;
+        struct cvmx_dpi_req_gbl_en_s cnf71xx;
 };
 
 union cvmx_dpi_sli_prtx_cfg {
         uint64_t u64;
         struct cvmx_dpi_sli_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t halt:1;
                 uint64_t qlm_cfg:4;
@@ -584,9 +944,25 @@ union cvmx_dpi_sli_prtx_cfg {
                 uint64_t mrrs_lim:1;
                 uint64_t reserved_2_2:1;
                 uint64_t mrrs:2;
+#else
+                uint64_t mrrs:2;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs_lim:1;
+                uint64_t mps:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps_lim:1;
+                uint64_t molr:6;
+                uint64_t reserved_14_15:2;
+                uint64_t rd_mode:1;
+                uint64_t reserved_17_19:3;
+                uint64_t qlm_cfg:4;
+                uint64_t halt:1;
+                uint64_t reserved_25_63:39;
+#endif
         } s;
         struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
         struct cvmx_dpi_sli_prtx_cfg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t halt:1;
                 uint64_t reserved_21_23:3;
@@ -601,18 +977,40 @@ union cvmx_dpi_sli_prtx_cfg {
                 uint64_t mrrs_lim:1;
                 uint64_t reserved_2_2:1;
                 uint64_t mrrs:2;
+#else
+                uint64_t mrrs:2;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs_lim:1;
+                uint64_t mps:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps_lim:1;
+                uint64_t molr:6;
+                uint64_t reserved_14_15:2;
+                uint64_t rd_mode:1;
+                uint64_t reserved_17_19:3;
+                uint64_t qlm_cfg:1;
+                uint64_t reserved_21_23:3;
+                uint64_t halt:1;
+                uint64_t reserved_25_63:39;
+#endif
         } cn63xx;
         struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
         struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
         struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
         struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
+        struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
 };
 
 union cvmx_dpi_sli_prtx_err {
         uint64_t u64;
         struct cvmx_dpi_sli_prtx_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:61;
                 uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t addr:61;
+#endif
         } s;
         struct cvmx_dpi_sli_prtx_err_s cn61xx;
         struct cvmx_dpi_sli_prtx_err_s cn63xx;
@@ -620,17 +1018,27 @@ union cvmx_dpi_sli_prtx_err {
         struct cvmx_dpi_sli_prtx_err_s cn66xx;
         struct cvmx_dpi_sli_prtx_err_s cn68xx;
         struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
+        struct cvmx_dpi_sli_prtx_err_s cnf71xx;
 };
 
 union cvmx_dpi_sli_prtx_err_info {
         uint64_t u64;
         struct cvmx_dpi_sli_prtx_err_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t lock:1;
                 uint64_t reserved_5_7:3;
                 uint64_t type:1;
                 uint64_t reserved_3_3:1;
                 uint64_t reqq:3;
+#else
+                uint64_t reqq:3;
+                uint64_t reserved_3_3:1;
+                uint64_t type:1;
+                uint64_t reserved_5_7:3;
+                uint64_t lock:1;
+                uint64_t reserved_9_63:55;
+#endif
         } s;
         struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
         struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
@@ -638,6 +1046,7 @@ union cvmx_dpi_sli_prtx_err_info {
         struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
         struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
         struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
+        struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;
 };
 
 #endif