diff options
author | David Daney <david.daney@cavium.com> | 2011-11-22 09:47:03 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-12-07 17:03:29 -0500 |
commit | 412394d10447d585ded3eab85da34381c117d782 (patch) | |
tree | 41fd5819ef18974eb0b29bba614d7cd620d281fa /arch/mips/include/asm/octeon/cvmx-dpi-defs.h | |
parent | 37d3bfd9927a8c509d31eac1036b2c3c905f8241 (diff) |
MIPS: Octeon: Update SOC PCI related register definitions for new chips.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2986/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-dpi-defs.h')
-rw-r--r-- | arch/mips/include/asm/octeon/cvmx-dpi-defs.h | 643 |
1 files changed, 643 insertions, 0 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h new file mode 100644 index 000000000000..c34ad04789ce --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h | |||
@@ -0,0 +1,643 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2011 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_DPI_DEFS_H__ | ||
29 | #define __CVMX_DPI_DEFS_H__ | ||
30 | |||
31 | #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull)) | ||
32 | #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull)) | ||
33 | #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8) | ||
34 | #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8) | ||
35 | #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8) | ||
36 | #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8) | ||
37 | #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8) | ||
38 | #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8) | ||
39 | #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8) | ||
40 | #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8) | ||
41 | #define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull)) | ||
42 | #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8) | ||
43 | #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8) | ||
44 | #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8) | ||
45 | #define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull)) | ||
46 | #define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull)) | ||
47 | #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull)) | ||
48 | #define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull)) | ||
49 | #define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull)) | ||
50 | #define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull)) | ||
51 | #define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull)) | ||
52 | #define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull)) | ||
53 | #define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull)) | ||
54 | #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull)) | ||
55 | #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) | ||
56 | #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) | ||
57 | #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) | ||
58 | #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) | ||
59 | |||
60 | union cvmx_dpi_bist_status { | ||
61 | uint64_t u64; | ||
62 | struct cvmx_dpi_bist_status_s { | ||
63 | uint64_t reserved_47_63:17; | ||
64 | uint64_t bist:47; | ||
65 | } s; | ||
66 | struct cvmx_dpi_bist_status_s cn61xx; | ||
67 | struct cvmx_dpi_bist_status_cn63xx { | ||
68 | uint64_t reserved_45_63:19; | ||
69 | uint64_t bist:45; | ||
70 | } cn63xx; | ||
71 | struct cvmx_dpi_bist_status_cn63xxp1 { | ||
72 | uint64_t reserved_37_63:27; | ||
73 | uint64_t bist:37; | ||
74 | } cn63xxp1; | ||
75 | struct cvmx_dpi_bist_status_s cn66xx; | ||
76 | struct cvmx_dpi_bist_status_cn63xx cn68xx; | ||
77 | struct cvmx_dpi_bist_status_cn63xx cn68xxp1; | ||
78 | }; | ||
79 | |||
80 | union cvmx_dpi_ctl { | ||
81 | uint64_t u64; | ||
82 | struct cvmx_dpi_ctl_s { | ||
83 | uint64_t reserved_2_63:62; | ||
84 | uint64_t clk:1; | ||
85 | uint64_t en:1; | ||
86 | } s; | ||
87 | struct cvmx_dpi_ctl_cn61xx { | ||
88 | uint64_t reserved_1_63:63; | ||
89 | uint64_t en:1; | ||
90 | } cn61xx; | ||
91 | struct cvmx_dpi_ctl_s cn63xx; | ||
92 | struct cvmx_dpi_ctl_s cn63xxp1; | ||
93 | struct cvmx_dpi_ctl_s cn66xx; | ||
94 | struct cvmx_dpi_ctl_s cn68xx; | ||
95 | struct cvmx_dpi_ctl_s cn68xxp1; | ||
96 | }; | ||
97 | |||
98 | union cvmx_dpi_dmax_counts { | ||
99 | uint64_t u64; | ||
100 | struct cvmx_dpi_dmax_counts_s { | ||
101 | uint64_t reserved_39_63:25; | ||
102 | uint64_t fcnt:7; | ||
103 | uint64_t dbell:32; | ||
104 | } s; | ||
105 | struct cvmx_dpi_dmax_counts_s cn61xx; | ||
106 | struct cvmx_dpi_dmax_counts_s cn63xx; | ||
107 | struct cvmx_dpi_dmax_counts_s cn63xxp1; | ||
108 | struct cvmx_dpi_dmax_counts_s cn66xx; | ||
109 | struct cvmx_dpi_dmax_counts_s cn68xx; | ||
110 | struct cvmx_dpi_dmax_counts_s cn68xxp1; | ||
111 | }; | ||
112 | |||
113 | union cvmx_dpi_dmax_dbell { | ||
114 | uint64_t u64; | ||
115 | struct cvmx_dpi_dmax_dbell_s { | ||
116 | uint64_t reserved_16_63:48; | ||
117 | uint64_t dbell:16; | ||
118 | } s; | ||
119 | struct cvmx_dpi_dmax_dbell_s cn61xx; | ||
120 | struct cvmx_dpi_dmax_dbell_s cn63xx; | ||
121 | struct cvmx_dpi_dmax_dbell_s cn63xxp1; | ||
122 | struct cvmx_dpi_dmax_dbell_s cn66xx; | ||
123 | struct cvmx_dpi_dmax_dbell_s cn68xx; | ||
124 | struct cvmx_dpi_dmax_dbell_s cn68xxp1; | ||
125 | }; | ||
126 | |||
127 | union cvmx_dpi_dmax_err_rsp_status { | ||
128 | uint64_t u64; | ||
129 | struct cvmx_dpi_dmax_err_rsp_status_s { | ||
130 | uint64_t reserved_6_63:58; | ||
131 | uint64_t status:6; | ||
132 | } s; | ||
133 | struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; | ||
134 | struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; | ||
135 | struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; | ||
136 | struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; | ||
137 | }; | ||
138 | |||
139 | union cvmx_dpi_dmax_ibuff_saddr { | ||
140 | uint64_t u64; | ||
141 | struct cvmx_dpi_dmax_ibuff_saddr_s { | ||
142 | uint64_t reserved_62_63:2; | ||
143 | uint64_t csize:14; | ||
144 | uint64_t reserved_41_47:7; | ||
145 | uint64_t idle:1; | ||
146 | uint64_t saddr:33; | ||
147 | uint64_t reserved_0_6:7; | ||
148 | } s; | ||
149 | struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { | ||
150 | uint64_t reserved_62_63:2; | ||
151 | uint64_t csize:14; | ||
152 | uint64_t reserved_41_47:7; | ||
153 | uint64_t idle:1; | ||
154 | uint64_t reserved_36_39:4; | ||
155 | uint64_t saddr:29; | ||
156 | uint64_t reserved_0_6:7; | ||
157 | } cn61xx; | ||
158 | struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; | ||
159 | struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; | ||
160 | struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; | ||
161 | struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx; | ||
162 | struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1; | ||
163 | }; | ||
164 | |||
165 | union cvmx_dpi_dmax_iflight { | ||
166 | uint64_t u64; | ||
167 | struct cvmx_dpi_dmax_iflight_s { | ||
168 | uint64_t reserved_3_63:61; | ||
169 | uint64_t cnt:3; | ||
170 | } s; | ||
171 | struct cvmx_dpi_dmax_iflight_s cn61xx; | ||
172 | struct cvmx_dpi_dmax_iflight_s cn66xx; | ||
173 | struct cvmx_dpi_dmax_iflight_s cn68xx; | ||
174 | struct cvmx_dpi_dmax_iflight_s cn68xxp1; | ||
175 | }; | ||
176 | |||
177 | union cvmx_dpi_dmax_naddr { | ||
178 | uint64_t u64; | ||
179 | struct cvmx_dpi_dmax_naddr_s { | ||
180 | uint64_t reserved_40_63:24; | ||
181 | uint64_t addr:40; | ||
182 | } s; | ||
183 | struct cvmx_dpi_dmax_naddr_cn61xx { | ||
184 | uint64_t reserved_36_63:28; | ||
185 | uint64_t addr:36; | ||
186 | } cn61xx; | ||
187 | struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; | ||
188 | struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; | ||
189 | struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; | ||
190 | struct cvmx_dpi_dmax_naddr_s cn68xx; | ||
191 | struct cvmx_dpi_dmax_naddr_s cn68xxp1; | ||
192 | }; | ||
193 | |||
194 | union cvmx_dpi_dmax_reqbnk0 { | ||
195 | uint64_t u64; | ||
196 | struct cvmx_dpi_dmax_reqbnk0_s { | ||
197 | uint64_t state:64; | ||
198 | } s; | ||
199 | struct cvmx_dpi_dmax_reqbnk0_s cn61xx; | ||
200 | struct cvmx_dpi_dmax_reqbnk0_s cn63xx; | ||
201 | struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1; | ||
202 | struct cvmx_dpi_dmax_reqbnk0_s cn66xx; | ||
203 | struct cvmx_dpi_dmax_reqbnk0_s cn68xx; | ||
204 | struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; | ||
205 | }; | ||
206 | |||
207 | union cvmx_dpi_dmax_reqbnk1 { | ||
208 | uint64_t u64; | ||
209 | struct cvmx_dpi_dmax_reqbnk1_s { | ||
210 | uint64_t state:64; | ||
211 | } s; | ||
212 | struct cvmx_dpi_dmax_reqbnk1_s cn61xx; | ||
213 | struct cvmx_dpi_dmax_reqbnk1_s cn63xx; | ||
214 | struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1; | ||
215 | struct cvmx_dpi_dmax_reqbnk1_s cn66xx; | ||
216 | struct cvmx_dpi_dmax_reqbnk1_s cn68xx; | ||
217 | struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; | ||
218 | }; | ||
219 | |||
220 | union cvmx_dpi_dma_control { | ||
221 | uint64_t u64; | ||
222 | struct cvmx_dpi_dma_control_s { | ||
223 | uint64_t reserved_62_63:2; | ||
224 | uint64_t dici_mode:1; | ||
225 | uint64_t pkt_en1:1; | ||
226 | uint64_t ffp_dis:1; | ||
227 | uint64_t commit_mode:1; | ||
228 | uint64_t pkt_hp:1; | ||
229 | uint64_t pkt_en:1; | ||
230 | uint64_t reserved_54_55:2; | ||
231 | uint64_t dma_enb:6; | ||
232 | uint64_t reserved_34_47:14; | ||
233 | uint64_t b0_lend:1; | ||
234 | uint64_t dwb_denb:1; | ||
235 | uint64_t dwb_ichk:9; | ||
236 | uint64_t fpa_que:3; | ||
237 | uint64_t o_add1:1; | ||
238 | uint64_t o_ro:1; | ||
239 | uint64_t o_ns:1; | ||
240 | uint64_t o_es:2; | ||
241 | uint64_t o_mode:1; | ||
242 | uint64_t reserved_0_13:14; | ||
243 | } s; | ||
244 | struct cvmx_dpi_dma_control_s cn61xx; | ||
245 | struct cvmx_dpi_dma_control_cn63xx { | ||
246 | uint64_t reserved_61_63:3; | ||
247 | uint64_t pkt_en1:1; | ||
248 | uint64_t ffp_dis:1; | ||
249 | uint64_t commit_mode:1; | ||
250 | uint64_t pkt_hp:1; | ||
251 | uint64_t pkt_en:1; | ||
252 | uint64_t reserved_54_55:2; | ||
253 | uint64_t dma_enb:6; | ||
254 | uint64_t reserved_34_47:14; | ||
255 | uint64_t b0_lend:1; | ||
256 | uint64_t dwb_denb:1; | ||
257 | uint64_t dwb_ichk:9; | ||
258 | uint64_t fpa_que:3; | ||
259 | uint64_t o_add1:1; | ||
260 | uint64_t o_ro:1; | ||
261 | uint64_t o_ns:1; | ||
262 | uint64_t o_es:2; | ||
263 | uint64_t o_mode:1; | ||
264 | uint64_t reserved_0_13:14; | ||
265 | } cn63xx; | ||
266 | struct cvmx_dpi_dma_control_cn63xxp1 { | ||
267 | uint64_t reserved_59_63:5; | ||
268 | uint64_t commit_mode:1; | ||
269 | uint64_t pkt_hp:1; | ||
270 | uint64_t pkt_en:1; | ||
271 | uint64_t reserved_54_55:2; | ||
272 | uint64_t dma_enb:6; | ||
273 | uint64_t reserved_34_47:14; | ||
274 | uint64_t b0_lend:1; | ||
275 | uint64_t dwb_denb:1; | ||
276 | uint64_t dwb_ichk:9; | ||
277 | uint64_t fpa_que:3; | ||
278 | uint64_t o_add1:1; | ||
279 | uint64_t o_ro:1; | ||
280 | uint64_t o_ns:1; | ||
281 | uint64_t o_es:2; | ||
282 | uint64_t o_mode:1; | ||
283 | uint64_t reserved_0_13:14; | ||
284 | } cn63xxp1; | ||
285 | struct cvmx_dpi_dma_control_cn63xx cn66xx; | ||
286 | struct cvmx_dpi_dma_control_s cn68xx; | ||
287 | struct cvmx_dpi_dma_control_cn63xx cn68xxp1; | ||
288 | }; | ||
289 | |||
290 | union cvmx_dpi_dma_engx_en { | ||
291 | uint64_t u64; | ||
292 | struct cvmx_dpi_dma_engx_en_s { | ||
293 | uint64_t reserved_8_63:56; | ||
294 | uint64_t qen:8; | ||
295 | } s; | ||
296 | struct cvmx_dpi_dma_engx_en_s cn61xx; | ||
297 | struct cvmx_dpi_dma_engx_en_s cn63xx; | ||
298 | struct cvmx_dpi_dma_engx_en_s cn63xxp1; | ||
299 | struct cvmx_dpi_dma_engx_en_s cn66xx; | ||
300 | struct cvmx_dpi_dma_engx_en_s cn68xx; | ||
301 | struct cvmx_dpi_dma_engx_en_s cn68xxp1; | ||
302 | }; | ||
303 | |||
304 | union cvmx_dpi_dma_ppx_cnt { | ||
305 | uint64_t u64; | ||
306 | struct cvmx_dpi_dma_ppx_cnt_s { | ||
307 | uint64_t reserved_16_63:48; | ||
308 | uint64_t cnt:16; | ||
309 | } s; | ||
310 | struct cvmx_dpi_dma_ppx_cnt_s cn61xx; | ||
311 | struct cvmx_dpi_dma_ppx_cnt_s cn68xx; | ||
312 | }; | ||
313 | |||
314 | union cvmx_dpi_engx_buf { | ||
315 | uint64_t u64; | ||
316 | struct cvmx_dpi_engx_buf_s { | ||
317 | uint64_t reserved_37_63:27; | ||
318 | uint64_t compblks:5; | ||
319 | uint64_t reserved_9_31:23; | ||
320 | uint64_t base:5; | ||
321 | uint64_t blks:4; | ||
322 | } s; | ||
323 | struct cvmx_dpi_engx_buf_s cn61xx; | ||
324 | struct cvmx_dpi_engx_buf_cn63xx { | ||
325 | uint64_t reserved_8_63:56; | ||
326 | uint64_t base:4; | ||
327 | uint64_t blks:4; | ||
328 | } cn63xx; | ||
329 | struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; | ||
330 | struct cvmx_dpi_engx_buf_s cn66xx; | ||
331 | struct cvmx_dpi_engx_buf_s cn68xx; | ||
332 | struct cvmx_dpi_engx_buf_s cn68xxp1; | ||
333 | }; | ||
334 | |||
335 | union cvmx_dpi_info_reg { | ||
336 | uint64_t u64; | ||
337 | struct cvmx_dpi_info_reg_s { | ||
338 | uint64_t reserved_8_63:56; | ||
339 | uint64_t ffp:4; | ||
340 | uint64_t reserved_2_3:2; | ||
341 | uint64_t ncb:1; | ||
342 | uint64_t rsl:1; | ||
343 | } s; | ||
344 | struct cvmx_dpi_info_reg_s cn61xx; | ||
345 | struct cvmx_dpi_info_reg_s cn63xx; | ||
346 | struct cvmx_dpi_info_reg_cn63xxp1 { | ||
347 | uint64_t reserved_2_63:62; | ||
348 | uint64_t ncb:1; | ||
349 | uint64_t rsl:1; | ||
350 | } cn63xxp1; | ||
351 | struct cvmx_dpi_info_reg_s cn66xx; | ||
352 | struct cvmx_dpi_info_reg_s cn68xx; | ||
353 | struct cvmx_dpi_info_reg_s cn68xxp1; | ||
354 | }; | ||
355 | |||
356 | union cvmx_dpi_int_en { | ||
357 | uint64_t u64; | ||
358 | struct cvmx_dpi_int_en_s { | ||
359 | uint64_t reserved_28_63:36; | ||
360 | uint64_t sprt3_rst:1; | ||
361 | uint64_t sprt2_rst:1; | ||
362 | uint64_t sprt1_rst:1; | ||
363 | uint64_t sprt0_rst:1; | ||
364 | uint64_t reserved_23_23:1; | ||
365 | uint64_t req_badfil:1; | ||
366 | uint64_t req_inull:1; | ||
367 | uint64_t req_anull:1; | ||
368 | uint64_t req_undflw:1; | ||
369 | uint64_t req_ovrflw:1; | ||
370 | uint64_t req_badlen:1; | ||
371 | uint64_t req_badadr:1; | ||
372 | uint64_t dmadbo:8; | ||
373 | uint64_t reserved_2_7:6; | ||
374 | uint64_t nfovr:1; | ||
375 | uint64_t nderr:1; | ||
376 | } s; | ||
377 | struct cvmx_dpi_int_en_s cn61xx; | ||
378 | struct cvmx_dpi_int_en_cn63xx { | ||
379 | uint64_t reserved_26_63:38; | ||
380 | uint64_t sprt1_rst:1; | ||
381 | uint64_t sprt0_rst:1; | ||
382 | uint64_t reserved_23_23:1; | ||
383 | uint64_t req_badfil:1; | ||
384 | uint64_t req_inull:1; | ||
385 | uint64_t req_anull:1; | ||
386 | uint64_t req_undflw:1; | ||
387 | uint64_t req_ovrflw:1; | ||
388 | uint64_t req_badlen:1; | ||
389 | uint64_t req_badadr:1; | ||
390 | uint64_t dmadbo:8; | ||
391 | uint64_t reserved_2_7:6; | ||
392 | uint64_t nfovr:1; | ||
393 | uint64_t nderr:1; | ||
394 | } cn63xx; | ||
395 | struct cvmx_dpi_int_en_cn63xx cn63xxp1; | ||
396 | struct cvmx_dpi_int_en_s cn66xx; | ||
397 | struct cvmx_dpi_int_en_cn63xx cn68xx; | ||
398 | struct cvmx_dpi_int_en_cn63xx cn68xxp1; | ||
399 | }; | ||
400 | |||
401 | union cvmx_dpi_int_reg { | ||
402 | uint64_t u64; | ||
403 | struct cvmx_dpi_int_reg_s { | ||
404 | uint64_t reserved_28_63:36; | ||
405 | uint64_t sprt3_rst:1; | ||
406 | uint64_t sprt2_rst:1; | ||
407 | uint64_t sprt1_rst:1; | ||
408 | uint64_t sprt0_rst:1; | ||
409 | uint64_t reserved_23_23:1; | ||
410 | uint64_t req_badfil:1; | ||
411 | uint64_t req_inull:1; | ||
412 | uint64_t req_anull:1; | ||
413 | uint64_t req_undflw:1; | ||
414 | uint64_t req_ovrflw:1; | ||
415 | uint64_t req_badlen:1; | ||
416 | uint64_t req_badadr:1; | ||
417 | uint64_t dmadbo:8; | ||
418 | uint64_t reserved_2_7:6; | ||
419 | uint64_t nfovr:1; | ||
420 | uint64_t nderr:1; | ||
421 | } s; | ||
422 | struct cvmx_dpi_int_reg_s cn61xx; | ||
423 | struct cvmx_dpi_int_reg_cn63xx { | ||
424 | uint64_t reserved_26_63:38; | ||
425 | uint64_t sprt1_rst:1; | ||
426 | uint64_t sprt0_rst:1; | ||
427 | uint64_t reserved_23_23:1; | ||
428 | uint64_t req_badfil:1; | ||
429 | uint64_t req_inull:1; | ||
430 | uint64_t req_anull:1; | ||
431 | uint64_t req_undflw:1; | ||
432 | uint64_t req_ovrflw:1; | ||
433 | uint64_t req_badlen:1; | ||
434 | uint64_t req_badadr:1; | ||
435 | uint64_t dmadbo:8; | ||
436 | uint64_t reserved_2_7:6; | ||
437 | uint64_t nfovr:1; | ||
438 | uint64_t nderr:1; | ||
439 | } cn63xx; | ||
440 | struct cvmx_dpi_int_reg_cn63xx cn63xxp1; | ||
441 | struct cvmx_dpi_int_reg_s cn66xx; | ||
442 | struct cvmx_dpi_int_reg_cn63xx cn68xx; | ||
443 | struct cvmx_dpi_int_reg_cn63xx cn68xxp1; | ||
444 | }; | ||
445 | |||
446 | union cvmx_dpi_ncbx_cfg { | ||
447 | uint64_t u64; | ||
448 | struct cvmx_dpi_ncbx_cfg_s { | ||
449 | uint64_t reserved_6_63:58; | ||
450 | uint64_t molr:6; | ||
451 | } s; | ||
452 | struct cvmx_dpi_ncbx_cfg_s cn61xx; | ||
453 | struct cvmx_dpi_ncbx_cfg_s cn66xx; | ||
454 | struct cvmx_dpi_ncbx_cfg_s cn68xx; | ||
455 | }; | ||
456 | |||
457 | union cvmx_dpi_pint_info { | ||
458 | uint64_t u64; | ||
459 | struct cvmx_dpi_pint_info_s { | ||
460 | uint64_t reserved_14_63:50; | ||
461 | uint64_t iinfo:6; | ||
462 | uint64_t reserved_6_7:2; | ||
463 | uint64_t sinfo:6; | ||
464 | } s; | ||
465 | struct cvmx_dpi_pint_info_s cn61xx; | ||
466 | struct cvmx_dpi_pint_info_s cn63xx; | ||
467 | struct cvmx_dpi_pint_info_s cn63xxp1; | ||
468 | struct cvmx_dpi_pint_info_s cn66xx; | ||
469 | struct cvmx_dpi_pint_info_s cn68xx; | ||
470 | struct cvmx_dpi_pint_info_s cn68xxp1; | ||
471 | }; | ||
472 | |||
473 | union cvmx_dpi_pkt_err_rsp { | ||
474 | uint64_t u64; | ||
475 | struct cvmx_dpi_pkt_err_rsp_s { | ||
476 | uint64_t reserved_1_63:63; | ||
477 | uint64_t pkterr:1; | ||
478 | } s; | ||
479 | struct cvmx_dpi_pkt_err_rsp_s cn61xx; | ||
480 | struct cvmx_dpi_pkt_err_rsp_s cn63xx; | ||
481 | struct cvmx_dpi_pkt_err_rsp_s cn63xxp1; | ||
482 | struct cvmx_dpi_pkt_err_rsp_s cn66xx; | ||
483 | struct cvmx_dpi_pkt_err_rsp_s cn68xx; | ||
484 | struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; | ||
485 | }; | ||
486 | |||
487 | union cvmx_dpi_req_err_rsp { | ||
488 | uint64_t u64; | ||
489 | struct cvmx_dpi_req_err_rsp_s { | ||
490 | uint64_t reserved_8_63:56; | ||
491 | uint64_t qerr:8; | ||
492 | } s; | ||
493 | struct cvmx_dpi_req_err_rsp_s cn61xx; | ||
494 | struct cvmx_dpi_req_err_rsp_s cn63xx; | ||
495 | struct cvmx_dpi_req_err_rsp_s cn63xxp1; | ||
496 | struct cvmx_dpi_req_err_rsp_s cn66xx; | ||
497 | struct cvmx_dpi_req_err_rsp_s cn68xx; | ||
498 | struct cvmx_dpi_req_err_rsp_s cn68xxp1; | ||
499 | }; | ||
500 | |||
501 | union cvmx_dpi_req_err_rsp_en { | ||
502 | uint64_t u64; | ||
503 | struct cvmx_dpi_req_err_rsp_en_s { | ||
504 | uint64_t reserved_8_63:56; | ||
505 | uint64_t en:8; | ||
506 | } s; | ||
507 | struct cvmx_dpi_req_err_rsp_en_s cn61xx; | ||
508 | struct cvmx_dpi_req_err_rsp_en_s cn63xx; | ||
509 | struct cvmx_dpi_req_err_rsp_en_s cn63xxp1; | ||
510 | struct cvmx_dpi_req_err_rsp_en_s cn66xx; | ||
511 | struct cvmx_dpi_req_err_rsp_en_s cn68xx; | ||
512 | struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; | ||
513 | }; | ||
514 | |||
515 | union cvmx_dpi_req_err_rst { | ||
516 | uint64_t u64; | ||
517 | struct cvmx_dpi_req_err_rst_s { | ||
518 | uint64_t reserved_8_63:56; | ||
519 | uint64_t qerr:8; | ||
520 | } s; | ||
521 | struct cvmx_dpi_req_err_rst_s cn61xx; | ||
522 | struct cvmx_dpi_req_err_rst_s cn63xx; | ||
523 | struct cvmx_dpi_req_err_rst_s cn63xxp1; | ||
524 | struct cvmx_dpi_req_err_rst_s cn66xx; | ||
525 | struct cvmx_dpi_req_err_rst_s cn68xx; | ||
526 | struct cvmx_dpi_req_err_rst_s cn68xxp1; | ||
527 | }; | ||
528 | |||
529 | union cvmx_dpi_req_err_rst_en { | ||
530 | uint64_t u64; | ||
531 | struct cvmx_dpi_req_err_rst_en_s { | ||
532 | uint64_t reserved_8_63:56; | ||
533 | uint64_t en:8; | ||
534 | } s; | ||
535 | struct cvmx_dpi_req_err_rst_en_s cn61xx; | ||
536 | struct cvmx_dpi_req_err_rst_en_s cn63xx; | ||
537 | struct cvmx_dpi_req_err_rst_en_s cn63xxp1; | ||
538 | struct cvmx_dpi_req_err_rst_en_s cn66xx; | ||
539 | struct cvmx_dpi_req_err_rst_en_s cn68xx; | ||
540 | struct cvmx_dpi_req_err_rst_en_s cn68xxp1; | ||
541 | }; | ||
542 | |||
543 | union cvmx_dpi_req_err_skip_comp { | ||
544 | uint64_t u64; | ||
545 | struct cvmx_dpi_req_err_skip_comp_s { | ||
546 | uint64_t reserved_24_63:40; | ||
547 | uint64_t en_rst:8; | ||
548 | uint64_t reserved_8_15:8; | ||
549 | uint64_t en_rsp:8; | ||
550 | } s; | ||
551 | struct cvmx_dpi_req_err_skip_comp_s cn61xx; | ||
552 | struct cvmx_dpi_req_err_skip_comp_s cn66xx; | ||
553 | struct cvmx_dpi_req_err_skip_comp_s cn68xx; | ||
554 | struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; | ||
555 | }; | ||
556 | |||
557 | union cvmx_dpi_req_gbl_en { | ||
558 | uint64_t u64; | ||
559 | struct cvmx_dpi_req_gbl_en_s { | ||
560 | uint64_t reserved_8_63:56; | ||
561 | uint64_t qen:8; | ||
562 | } s; | ||
563 | struct cvmx_dpi_req_gbl_en_s cn61xx; | ||
564 | struct cvmx_dpi_req_gbl_en_s cn63xx; | ||
565 | struct cvmx_dpi_req_gbl_en_s cn63xxp1; | ||
566 | struct cvmx_dpi_req_gbl_en_s cn66xx; | ||
567 | struct cvmx_dpi_req_gbl_en_s cn68xx; | ||
568 | struct cvmx_dpi_req_gbl_en_s cn68xxp1; | ||
569 | }; | ||
570 | |||
571 | union cvmx_dpi_sli_prtx_cfg { | ||
572 | uint64_t u64; | ||
573 | struct cvmx_dpi_sli_prtx_cfg_s { | ||
574 | uint64_t reserved_25_63:39; | ||
575 | uint64_t halt:1; | ||
576 | uint64_t qlm_cfg:4; | ||
577 | uint64_t reserved_17_19:3; | ||
578 | uint64_t rd_mode:1; | ||
579 | uint64_t reserved_14_15:2; | ||
580 | uint64_t molr:6; | ||
581 | uint64_t mps_lim:1; | ||
582 | uint64_t reserved_5_6:2; | ||
583 | uint64_t mps:1; | ||
584 | uint64_t mrrs_lim:1; | ||
585 | uint64_t reserved_2_2:1; | ||
586 | uint64_t mrrs:2; | ||
587 | } s; | ||
588 | struct cvmx_dpi_sli_prtx_cfg_s cn61xx; | ||
589 | struct cvmx_dpi_sli_prtx_cfg_cn63xx { | ||
590 | uint64_t reserved_25_63:39; | ||
591 | uint64_t halt:1; | ||
592 | uint64_t reserved_21_23:3; | ||
593 | uint64_t qlm_cfg:1; | ||
594 | uint64_t reserved_17_19:3; | ||
595 | uint64_t rd_mode:1; | ||
596 | uint64_t reserved_14_15:2; | ||
597 | uint64_t molr:6; | ||
598 | uint64_t mps_lim:1; | ||
599 | uint64_t reserved_5_6:2; | ||
600 | uint64_t mps:1; | ||
601 | uint64_t mrrs_lim:1; | ||
602 | uint64_t reserved_2_2:1; | ||
603 | uint64_t mrrs:2; | ||
604 | } cn63xx; | ||
605 | struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; | ||
606 | struct cvmx_dpi_sli_prtx_cfg_s cn66xx; | ||
607 | struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; | ||
608 | struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; | ||
609 | }; | ||
610 | |||
611 | union cvmx_dpi_sli_prtx_err { | ||
612 | uint64_t u64; | ||
613 | struct cvmx_dpi_sli_prtx_err_s { | ||
614 | uint64_t addr:61; | ||
615 | uint64_t reserved_0_2:3; | ||
616 | } s; | ||
617 | struct cvmx_dpi_sli_prtx_err_s cn61xx; | ||
618 | struct cvmx_dpi_sli_prtx_err_s cn63xx; | ||
619 | struct cvmx_dpi_sli_prtx_err_s cn63xxp1; | ||
620 | struct cvmx_dpi_sli_prtx_err_s cn66xx; | ||
621 | struct cvmx_dpi_sli_prtx_err_s cn68xx; | ||
622 | struct cvmx_dpi_sli_prtx_err_s cn68xxp1; | ||
623 | }; | ||
624 | |||
625 | union cvmx_dpi_sli_prtx_err_info { | ||
626 | uint64_t u64; | ||
627 | struct cvmx_dpi_sli_prtx_err_info_s { | ||
628 | uint64_t reserved_9_63:55; | ||
629 | uint64_t lock:1; | ||
630 | uint64_t reserved_5_7:3; | ||
631 | uint64_t type:1; | ||
632 | uint64_t reserved_3_3:1; | ||
633 | uint64_t reqq:3; | ||
634 | } s; | ||
635 | struct cvmx_dpi_sli_prtx_err_info_s cn61xx; | ||
636 | struct cvmx_dpi_sli_prtx_err_info_s cn63xx; | ||
637 | struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1; | ||
638 | struct cvmx_dpi_sli_prtx_err_info_s cn66xx; | ||
639 | struct cvmx_dpi_sli_prtx_err_info_s cn68xx; | ||
640 | struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; | ||
641 | }; | ||
642 | |||
643 | #endif | ||