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authorGanesan Ramalingam <ganesanr@broadcom.com>2012-10-31 08:01:42 -0400
committerJohn Crispin <blogic@openwrt.org>2012-11-09 05:37:20 -0500
commited21cfe207276e2d2883173399dd0380db372e18 (patch)
tree99382401195a5163fc6fd2191d786034512aa874 /arch/mips/include/asm/netlogic
parent38541742da05f65d77e514a70bae9b84251c4bc4 (diff)
MIPS: Netlogic: Support for XLR/XLS Fast Message Network
On XLR/XLS, the cpu cores communicate with fast on-chip devices (e.g. network accelerator, security engine etc.) using the Fast Messaging Network(FMN). The FMN queues and credits needs to be configured and intialized before it can be used. The co-processor 2 on XLR/XLS CPU cores has registers for FMN access, and the XLR/XLS has custom instructions for sending and loading messages. The FMN can deliver also per-cpu interrupts when messages are available at the CPU. This patch adds FMN initialization, adds interrupt setup and handling, and also provides support for sending and receiving FMN messages. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4468 Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/include/asm/netlogic')
-rw-r--r--arch/mips/include/asm/netlogic/common.h1
-rw-r--r--arch/mips/include/asm/netlogic/interrupt.h2
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h137
-rw-r--r--arch/mips/include/asm/netlogic/xlr/fmn.h363
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h6
5 files changed, 504 insertions, 5 deletions
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index 1fee7eff64aa..42bfd5f1eeec 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -57,6 +57,7 @@ void nlm_smp_irq_init(int hwcpuid);
57void nlm_boot_secondary_cpus(void); 57void nlm_boot_secondary_cpus(void);
58int nlm_wakeup_secondary_cpus(void); 58int nlm_wakeup_secondary_cpus(void);
59void nlm_rmiboot_preboot(void); 59void nlm_rmiboot_preboot(void);
60void nlm_percpu_init(int hwcpuid);
60 61
61static inline void 62static inline void
62nlm_set_nmi_handler(void *handler) 63nlm_set_nmi_handler(void *handler)
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
index a85aadb6cfd7..ed5993d9b7b8 100644
--- a/arch/mips/include/asm/netlogic/interrupt.h
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -39,7 +39,7 @@
39 39
40#define IRQ_IPI_SMP_FUNCTION 3 40#define IRQ_IPI_SMP_FUNCTION 3
41#define IRQ_IPI_SMP_RESCHEDULE 4 41#define IRQ_IPI_SMP_RESCHEDULE 4
42#define IRQ_MSGRING 6 42#define IRQ_FMN 5
43#define IRQ_TIMER 7 43#define IRQ_TIMER 7
44 44
45#endif 45#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index c9f6de53d410..32ba6d95d47c 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -78,4 +78,141 @@ static inline int nlm_nodeid(void)
78 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; 78 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
79} 79}
80 80
81static inline unsigned int nlm_core_id(void)
82{
83 return (read_c0_ebase() & 0x1c) >> 2;
84}
85
86static inline unsigned int nlm_thread_id(void)
87{
88 return read_c0_ebase() & 0x3;
89}
90
91#define __read_64bit_c2_split(source, sel) \
92({ \
93 unsigned long long __val; \
94 unsigned long __flags; \
95 \
96 local_irq_save(__flags); \
97 if (sel == 0) \
98 __asm__ __volatile__( \
99 ".set\tmips64\n\t" \
100 "dmfc2\t%M0, " #source "\n\t" \
101 "dsll\t%L0, %M0, 32\n\t" \
102 "dsra\t%M0, %M0, 32\n\t" \
103 "dsra\t%L0, %L0, 32\n\t" \
104 ".set\tmips0\n\t" \
105 : "=r" (__val)); \
106 else \
107 __asm__ __volatile__( \
108 ".set\tmips64\n\t" \
109 "dmfc2\t%M0, " #source ", " #sel "\n\t" \
110 "dsll\t%L0, %M0, 32\n\t" \
111 "dsra\t%M0, %M0, 32\n\t" \
112 "dsra\t%L0, %L0, 32\n\t" \
113 ".set\tmips0\n\t" \
114 : "=r" (__val)); \
115 local_irq_restore(__flags); \
116 \
117 __val; \
118})
119
120#define __write_64bit_c2_split(source, sel, val) \
121do { \
122 unsigned long __flags; \
123 \
124 local_irq_save(__flags); \
125 if (sel == 0) \
126 __asm__ __volatile__( \
127 ".set\tmips64\n\t" \
128 "dsll\t%L0, %L0, 32\n\t" \
129 "dsrl\t%L0, %L0, 32\n\t" \
130 "dsll\t%M0, %M0, 32\n\t" \
131 "or\t%L0, %L0, %M0\n\t" \
132 "dmtc2\t%L0, " #source "\n\t" \
133 ".set\tmips0\n\t" \
134 : : "r" (val)); \
135 else \
136 __asm__ __volatile__( \
137 ".set\tmips64\n\t" \
138 "dsll\t%L0, %L0, 32\n\t" \
139 "dsrl\t%L0, %L0, 32\n\t" \
140 "dsll\t%M0, %M0, 32\n\t" \
141 "or\t%L0, %L0, %M0\n\t" \
142 "dmtc2\t%L0, " #source ", " #sel "\n\t" \
143 ".set\tmips0\n\t" \
144 : : "r" (val)); \
145 local_irq_restore(__flags); \
146} while (0)
147
148#define __read_32bit_c2_register(source, sel) \
149({ uint32_t __res; \
150 if (sel == 0) \
151 __asm__ __volatile__( \
152 ".set\tmips32\n\t" \
153 "mfc2\t%0, " #source "\n\t" \
154 ".set\tmips0\n\t" \
155 : "=r" (__res)); \
156 else \
157 __asm__ __volatile__( \
158 ".set\tmips32\n\t" \
159 "mfc2\t%0, " #source ", " #sel "\n\t" \
160 ".set\tmips0\n\t" \
161 : "=r" (__res)); \
162 __res; \
163})
164
165#define __read_64bit_c2_register(source, sel) \
166({ unsigned long long __res; \
167 if (sizeof(unsigned long) == 4) \
168 __res = __read_64bit_c2_split(source, sel); \
169 else if (sel == 0) \
170 __asm__ __volatile__( \
171 ".set\tmips64\n\t" \
172 "dmfc2\t%0, " #source "\n\t" \
173 ".set\tmips0\n\t" \
174 : "=r" (__res)); \
175 else \
176 __asm__ __volatile__( \
177 ".set\tmips64\n\t" \
178 "dmfc2\t%0, " #source ", " #sel "\n\t" \
179 ".set\tmips0\n\t" \
180 : "=r" (__res)); \
181 __res; \
182})
183
184#define __write_64bit_c2_register(register, sel, value) \
185do { \
186 if (sizeof(unsigned long) == 4) \
187 __write_64bit_c2_split(register, sel, value); \
188 else if (sel == 0) \
189 __asm__ __volatile__( \
190 ".set\tmips64\n\t" \
191 "dmtc2\t%z0, " #register "\n\t" \
192 ".set\tmips0\n\t" \
193 : : "Jr" (value)); \
194 else \
195 __asm__ __volatile__( \
196 ".set\tmips64\n\t" \
197 "dmtc2\t%z0, " #register ", " #sel "\n\t" \
198 ".set\tmips0\n\t" \
199 : : "Jr" (value)); \
200} while (0)
201
202#define __write_32bit_c2_register(reg, sel, value) \
203({ \
204 if (sel == 0) \
205 __asm__ __volatile__( \
206 ".set\tmips32\n\t" \
207 "mtc2\t%z0, " #reg "\n\t" \
208 ".set\tmips0\n\t" \
209 : : "Jr" (value)); \
210 else \
211 __asm__ __volatile__( \
212 ".set\tmips32\n\t" \
213 "mtc2\t%z0, " #reg ", " #sel "\n\t" \
214 ".set\tmips0\n\t" \
215 : : "Jr" (value)); \
216})
217
81#endif /*_ASM_NLM_MIPS_EXTS_H */ 218#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
new file mode 100644
index 000000000000..68d5167c86bb
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -0,0 +1,363 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_FMN_H_
36#define _NLM_FMN_H_
37
38#include <asm/netlogic/mips-extns.h> /* for COP2 access */
39
40/* Station IDs */
41#define FMN_STNID_CPU0 0x00
42#define FMN_STNID_CPU1 0x08
43#define FMN_STNID_CPU2 0x10
44#define FMN_STNID_CPU3 0x18
45#define FMN_STNID_CPU4 0x20
46#define FMN_STNID_CPU5 0x28
47#define FMN_STNID_CPU6 0x30
48#define FMN_STNID_CPU7 0x38
49
50#define FMN_STNID_XGS0_TX 64
51#define FMN_STNID_XMAC0_00_TX 64
52#define FMN_STNID_XMAC0_01_TX 65
53#define FMN_STNID_XMAC0_02_TX 66
54#define FMN_STNID_XMAC0_03_TX 67
55#define FMN_STNID_XMAC0_04_TX 68
56#define FMN_STNID_XMAC0_05_TX 69
57#define FMN_STNID_XMAC0_06_TX 70
58#define FMN_STNID_XMAC0_07_TX 71
59#define FMN_STNID_XMAC0_08_TX 72
60#define FMN_STNID_XMAC0_09_TX 73
61#define FMN_STNID_XMAC0_10_TX 74
62#define FMN_STNID_XMAC0_11_TX 75
63#define FMN_STNID_XMAC0_12_TX 76
64#define FMN_STNID_XMAC0_13_TX 77
65#define FMN_STNID_XMAC0_14_TX 78
66#define FMN_STNID_XMAC0_15_TX 79
67
68#define FMN_STNID_XGS1_TX 80
69#define FMN_STNID_XMAC1_00_TX 80
70#define FMN_STNID_XMAC1_01_TX 81
71#define FMN_STNID_XMAC1_02_TX 82
72#define FMN_STNID_XMAC1_03_TX 83
73#define FMN_STNID_XMAC1_04_TX 84
74#define FMN_STNID_XMAC1_05_TX 85
75#define FMN_STNID_XMAC1_06_TX 86
76#define FMN_STNID_XMAC1_07_TX 87
77#define FMN_STNID_XMAC1_08_TX 88
78#define FMN_STNID_XMAC1_09_TX 89
79#define FMN_STNID_XMAC1_10_TX 90
80#define FMN_STNID_XMAC1_11_TX 91
81#define FMN_STNID_XMAC1_12_TX 92
82#define FMN_STNID_XMAC1_13_TX 93
83#define FMN_STNID_XMAC1_14_TX 94
84#define FMN_STNID_XMAC1_15_TX 95
85
86#define FMN_STNID_GMAC 96
87#define FMN_STNID_GMACJFR_0 96
88#define FMN_STNID_GMACRFR_0 97
89#define FMN_STNID_GMACTX0 98
90#define FMN_STNID_GMACTX1 99
91#define FMN_STNID_GMACTX2 100
92#define FMN_STNID_GMACTX3 101
93#define FMN_STNID_GMACJFR_1 102
94#define FMN_STNID_GMACRFR_1 103
95
96#define FMN_STNID_DMA 104
97#define FMN_STNID_DMA_0 104
98#define FMN_STNID_DMA_1 105
99#define FMN_STNID_DMA_2 106
100#define FMN_STNID_DMA_3 107
101
102#define FMN_STNID_XGS0FR 112
103#define FMN_STNID_XMAC0JFR 112
104#define FMN_STNID_XMAC0RFR 113
105
106#define FMN_STNID_XGS1FR 114
107#define FMN_STNID_XMAC1JFR 114
108#define FMN_STNID_XMAC1RFR 115
109#define FMN_STNID_SEC 120
110#define FMN_STNID_SEC0 120
111#define FMN_STNID_SEC1 121
112#define FMN_STNID_SEC2 122
113#define FMN_STNID_SEC3 123
114#define FMN_STNID_PK0 124
115#define FMN_STNID_SEC_RSA 124
116#define FMN_STNID_SEC_RSVD0 125
117#define FMN_STNID_SEC_RSVD1 126
118#define FMN_STNID_SEC_RSVD2 127
119
120#define FMN_STNID_GMAC1 80
121#define FMN_STNID_GMAC1_FR_0 81
122#define FMN_STNID_GMAC1_TX0 82
123#define FMN_STNID_GMAC1_TX1 83
124#define FMN_STNID_GMAC1_TX2 84
125#define FMN_STNID_GMAC1_TX3 85
126#define FMN_STNID_GMAC1_FR_1 87
127#define FMN_STNID_GMAC0 96
128#define FMN_STNID_GMAC0_FR_0 97
129#define FMN_STNID_GMAC0_TX0 98
130#define FMN_STNID_GMAC0_TX1 99
131#define FMN_STNID_GMAC0_TX2 100
132#define FMN_STNID_GMAC0_TX3 101
133#define FMN_STNID_GMAC0_FR_1 103
134#define FMN_STNID_CMP_0 108
135#define FMN_STNID_CMP_1 109
136#define FMN_STNID_CMP_2 110
137#define FMN_STNID_CMP_3 111
138#define FMN_STNID_PCIE_0 116
139#define FMN_STNID_PCIE_1 117
140#define FMN_STNID_PCIE_2 118
141#define FMN_STNID_PCIE_3 119
142#define FMN_STNID_XLS_PK0 121
143
144#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s)
145#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s)
146#define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s)
147#define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s)
148#define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s)
149#define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s)
150#define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s)
151#define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s)
152#define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s)
153#define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s)
154#define nlm_read_c2_cc10(s) __read_32bit_c2_register($26, s)
155#define nlm_read_c2_cc11(s) __read_32bit_c2_register($27, s)
156#define nlm_read_c2_cc12(s) __read_32bit_c2_register($28, s)
157#define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s)
158#define nlm_read_c2_cc14(s) __read_32bit_c2_register($30, s)
159#define nlm_read_c2_cc15(s) __read_32bit_c2_register($31, s)
160
161#define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v)
162#define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v)
163#define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v)
164#define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v)
165#define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v)
166#define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v)
167#define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v)
168#define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v)
169#define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v)
170#define nlm_write_c2_cc9(s, v) __write_32bit_c2_register($25, s, v)
171#define nlm_write_c2_cc10(s, v) __write_32bit_c2_register($26, s, v)
172#define nlm_write_c2_cc11(s, v) __write_32bit_c2_register($27, s, v)
173#define nlm_write_c2_cc12(s, v) __write_32bit_c2_register($28, s, v)
174#define nlm_write_c2_cc13(s, v) __write_32bit_c2_register($29, s, v)
175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
177
178#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
179#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
180#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
181#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b)
182#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v)
183
184#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0)
185#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1)
186#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2)
187#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3)
188
189#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v)
190#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v)
191#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v)
192#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v)
193
194#define FMN_STN_RX_QSIZE 256
195#define FMN_NSTATIONS 128
196#define FMN_CORE_NBUCKETS 8
197
198static inline void nlm_msgsnd(unsigned int stid)
199{
200 __asm__ volatile (
201 ".set push\n"
202 ".set noreorder\n"
203 ".set noat\n"
204 "move $1, %0\n"
205 "c2 0x10001\n" /* msgsnd $1 */
206 ".set pop\n"
207 : : "r" (stid) : "$1"
208 );
209}
210
211static inline void nlm_msgld(unsigned int pri)
212{
213 __asm__ volatile (
214 ".set push\n"
215 ".set noreorder\n"
216 ".set noat\n"
217 "move $1, %0\n"
218 "c2 0x10002\n" /* msgld $1 */
219 ".set pop\n"
220 : : "r" (pri) : "$1"
221 );
222}
223
224static inline void nlm_msgwait(unsigned int mask)
225{
226 __asm__ volatile (
227 ".set push\n"
228 ".set noreorder\n"
229 ".set noat\n"
230 "move $8, %0\n"
231 "c2 0x10003\n" /* msgwait $1 */
232 ".set pop\n"
233 : : "r" (mask) : "$1"
234 );
235}
236
237/*
238 * Disable interrupts and enable COP2 access
239 */
240static inline uint32_t nlm_cop2_enable(void)
241{
242 uint32_t sr = read_c0_status();
243
244 write_c0_status((sr & ~ST0_IE) | ST0_CU2);
245 return sr;
246}
247
248static inline void nlm_cop2_restore(uint32_t sr)
249{
250 write_c0_status(sr);
251}
252
253static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask)
254{
255 uint32_t config;
256
257 config = (1 << 24) /* interrupt water mark - 1 msg */
258 | (irq << 16) /* irq */
259 | (tmask << 8) /* thread mask */
260 | 0x2; /* enable watermark intr, disable empty intr */
261 nlm_write_c2_config(config);
262}
263
264struct nlm_fmn_msg {
265 uint64_t msg0;
266 uint64_t msg1;
267 uint64_t msg2;
268 uint64_t msg3;
269};
270
271static inline int nlm_fmn_send(unsigned int size, unsigned int code,
272 unsigned int stid, struct nlm_fmn_msg *msg)
273{
274 unsigned int dest;
275 uint32_t status;
276 int i;
277
278 /*
279 * Make sure that all the writes pending at the cpu are flushed.
280 * Any writes pending on CPU will not be see by devices. L1/L2
281 * caches are coherent with IO, so no cache flush needed.
282 */
283 __asm __volatile("sync");
284
285 /* Load TX message buffers */
286 nlm_write_c2_tx_msg0(msg->msg0);
287 nlm_write_c2_tx_msg1(msg->msg1);
288 nlm_write_c2_tx_msg2(msg->msg2);
289 nlm_write_c2_tx_msg3(msg->msg3);
290 dest = ((size - 1) << 16) | (code << 8) | stid;
291
292 /*
293 * Retry a few times on credit fail, this should be a
294 * transient condition, unless there is a configuration
295 * failure, or the receiver is stuck.
296 */
297 for (i = 0; i < 8; i++) {
298 nlm_msgsnd(dest);
299 status = nlm_read_c2_status(0);
300 if ((status & 0x2) == 1)
301 pr_info("Send pending fail!\n");
302 if ((status & 0x4) == 0)
303 return 0;
304 }
305
306 /* If there is a credit failure, return error */
307 return status & 0x06;
308}
309
310static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
311 struct nlm_fmn_msg *msg)
312{
313 uint32_t status, tmp;
314
315 nlm_msgld(bucket);
316
317 /* wait for load pending to clear */
318 do {
319 status = nlm_read_c2_status(1);
320 } while ((status & 0x08) != 0);
321
322 /* receive error bits */
323 tmp = status & 0x30;
324 if (tmp != 0)
325 return tmp;
326
327 *size = ((status & 0xc0) >> 6) + 1;
328 *code = (status & 0xff00) >> 8;
329 *stid = (status & 0x7f0000) >> 16;
330 msg->msg0 = nlm_read_c2_rx_msg0();
331 msg->msg1 = nlm_read_c2_rx_msg1();
332 msg->msg2 = nlm_read_c2_rx_msg2();
333 msg->msg3 = nlm_read_c2_rx_msg3();
334
335 return 0;
336}
337
338struct xlr_fmn_info {
339 int num_buckets;
340 int start_stn_id;
341 int end_stn_id;
342 int credit_config[128];
343};
344
345struct xlr_board_fmn_config {
346 int bucket_size[128]; /* size of buckets for all stations */
347 struct xlr_fmn_info cpu[8];
348 struct xlr_fmn_info gmac[2];
349 struct xlr_fmn_info dma;
350 struct xlr_fmn_info cmp;
351 struct xlr_fmn_info sae;
352 struct xlr_fmn_info xgmac[2];
353};
354
355extern int nlm_register_fmn_handler(int start, int end,
356 void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *),
357 void *arg);
358extern void xlr_percpu_fmn_init(void);
359extern void nlm_setup_fmn_irq(void);
360extern void xlr_board_info_setup(void);
361
362extern struct xlr_board_fmn_config xlr_board_fmn_config;
363#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index ff4a17b0bf78..c1667e0c272a 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -51,10 +51,8 @@ static inline unsigned int nlm_chip_is_xls_b(void)
51 return ((prid & 0xf000) == 0x4000); 51 return ((prid & 0xf000) == 0x4000);
52} 52}
53 53
54/* 54/* XLR chip types */
55 * XLR chip types 55/* The XLS product line has chip versions 0x[48c]? */
56 */
57 /* The XLS product line has chip versions 0x[48c]? */
58static inline unsigned int nlm_chip_is_xls(void) 56static inline unsigned int nlm_chip_is_xls(void)
59{ 57{
60 uint32_t prid = read_c0_prid(); 58 uint32_t prid = read_c0_prid();
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 02:44:41 -0400