MIPS: Netlogic: XLP9XX PIC updates

Functions for the XLP9XX interrupt table entry format and other PIC
register changes.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6279/

1 files changed, 48 insertions, 24 deletions

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 3fcbe7409177..f10bf3bba58f 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -150,12 +150,19 @@
 #define PIC_IRT0                0x74
 #define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
 
-#define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
+#define PIC_9XX_PENDING_0       0x6
+#define PIC_9XX_PENDING_1       0x8
+#define PIC_9XX_PENDING_2       0xa
+#define PIC_9XX_PENDING_3       0xc
+
+#define PIC_9XX_IRT0            0x1c0
+#define PIC_9XX_IRT(i)          (PIC_9XX_IRT0 + ((i) * 2))
 
 /*
  *    IRT Map
  */
 #define PIC_NUM_IRTS            160
+#define PIC_9XX_NUM_IRTS        256
 
 #define PIC_IRT_WD_0_INDEX      0
 #define PIC_IRT_WD_1_INDEX      1
@@ -205,30 +212,26 @@
 
 #define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
-#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
+#define nlm_get_pic_pcibase(node)       nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
 /* We use PIC on node 0 as a timer */
 #define pic_timer_freq()                nlm_get_pic_frequency(0)
 
 /* IRT and h/w interrupt routines */
-static inline int
-nlm_pic_read_irt(uint64_t base, int irt_index)
-{
-        return nlm_read_pic_reg(base, PIC_IRT(irt_index));
-}
-
 static inline void
-nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
+nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int dt, int db, int cpu)
 {
         uint64_t val;
 
-        val = nlm_read_pic_reg(base, PIC_IRT(irt));
-        /* clear cpuset and mask */
-        val &= ~((0x7ull << 16) | 0xffff);
-        /* set DB, cpuset and cpumask */
-        val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
-        nlm_write_pic_reg(base, PIC_IRT(irt), val);
+        val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
+                        ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
+                        ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
+                        (cpu & 0x3ff);
+
+        nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
 }
 
 static inline void
@@ -249,9 +252,13 @@ static inline void
 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
         int sch, int vec, int cpu)
 {
-        nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
-                (cpu >> 4),             /* thread group */
-                1 << (cpu & 0xf));      /* thread mask */
+        if (cpu_is_xlp9xx())
+                nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
+                                                        1, 0, cpu);
+        else
+                nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
+                        (cpu >> 4),             /* thread group */
+                        1 << (cpu & 0xf));      /* thread mask */
 }
 
 static inline uint64_t
@@ -293,8 +300,13 @@ nlm_pic_enable_irt(uint64_t base, int irt)
 {
         uint64_t reg;
 
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+        }
 }
 
 static inline void
@@ -302,8 +314,15 @@ nlm_pic_disable_irt(uint64_t base, int irt)
 {
         uint64_t reg;
 
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                reg &= ~((uint64_t)1 << 22);
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                reg &= ~((uint64_t)1 << 31);
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg);
+        }
 }
 
 static inline void
@@ -311,8 +330,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
 {
         uint64_t ipi;
 
-        ipi = ((uint64_t)nmi << 31) | (irq << 20);
-        ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
+        if (cpu_is_xlp9xx())
+                ipi = (nmi << 23) | (irq << 24) |
+                        (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
+        else
+                ipi = ((uint64_t)nmi << 31) | (irq << 20) |
+                        ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
+
         nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
 }