diff options
author | Ganesan Ramalingam <ganesanr@broadcom.com> | 2013-08-11 05:13:56 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-09-03 17:22:19 -0400 |
commit | 57ceb4b02045bd677b70f9e2b3d41e8c1bb86598 (patch) | |
tree | d8745a3424a87b5fa8ca56208943a21e16282550 /arch/mips/include/asm/netlogic | |
parent | 5b6ff35d33cb0310c36f9081b9e39cd016715e9c (diff) |
MIPS: Netlogic: XLP2XX CPU and PIC frequency
Add code to calculate the CPU and PIC frequency for XLP2XX SoCs.
Since the PIC frequency on XLP2XX can be configured, add a new macro
pic_timer_freq() to be used in netlogic/common/time.c.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: Ganesan Ramalingam <ganesanr@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5701/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/netlogic')
-rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/pic.h | 5 | ||||
-rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/sys.h | 31 | ||||
-rw-r--r-- | arch/mips/include/asm/netlogic/xlr/pic.h | 2 |
3 files changed, 36 insertions, 2 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index 4b5108dfaa16..105389b79f09 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h | |||
@@ -208,13 +208,14 @@ | |||
208 | #define PIC_LOCAL_SCHEDULING 1 | 208 | #define PIC_LOCAL_SCHEDULING 1 |
209 | #define PIC_GLOBAL_SCHEDULING 0 | 209 | #define PIC_GLOBAL_SCHEDULING 0 |
210 | 210 | ||
211 | #define PIC_CLK_HZ 133333333 | ||
212 | |||
213 | #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) | 211 | #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) |
214 | #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) | 212 | #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) |
215 | #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) | 213 | #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) |
216 | #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) | 214 | #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) |
217 | 215 | ||
216 | /* We use PIC on node 0 as a timer */ | ||
217 | #define pic_timer_freq() nlm_get_pic_frequency(0) | ||
218 | |||
218 | /* IRT and h/w interrupt routines */ | 219 | /* IRT and h/w interrupt routines */ |
219 | static inline int | 220 | static inline int |
220 | nlm_pic_read_irt(uint64_t base, int irt_index) | 221 | nlm_pic_read_irt(uint64_t base, int irt_index) |
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h index 470e52bfc061..fcf2833c16ca 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h | |||
@@ -117,6 +117,36 @@ | |||
117 | #define SYS_SCRTCH2 0x4b | 117 | #define SYS_SCRTCH2 0x4b |
118 | #define SYS_SCRTCH3 0x4c | 118 | #define SYS_SCRTCH3 0x4c |
119 | 119 | ||
120 | /* PLL registers XLP2XX */ | ||
121 | #define SYS_PLL_CTRL0 0x240 | ||
122 | #define SYS_PLL_CTRL1 0x241 | ||
123 | #define SYS_PLL_CTRL2 0x242 | ||
124 | #define SYS_PLL_CTRL3 0x243 | ||
125 | #define SYS_DMC_PLL_CTRL0 0x244 | ||
126 | #define SYS_DMC_PLL_CTRL1 0x245 | ||
127 | #define SYS_DMC_PLL_CTRL2 0x246 | ||
128 | #define SYS_DMC_PLL_CTRL3 0x247 | ||
129 | |||
130 | #define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4) | ||
131 | #define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4) | ||
132 | #define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4) | ||
133 | #define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4) | ||
134 | |||
135 | #define SYS_CPU_PLL_CHG_CTRL 0x288 | ||
136 | #define SYS_PLL_CHG_CTRL 0x289 | ||
137 | #define SYS_CLK_DEV_DIS 0x28a | ||
138 | #define SYS_CLK_DEV_SEL 0x28b | ||
139 | #define SYS_CLK_DEV_DIV 0x28c | ||
140 | #define SYS_CLK_DEV_CHG 0x28d | ||
141 | #define SYS_CLK_DEV_SEL_REG 0x28e | ||
142 | #define SYS_CLK_DEV_DIV_REG 0x28f | ||
143 | #define SYS_CPU_PLL_LOCK 0x29f | ||
144 | #define SYS_SYS_PLL_LOCK 0x2a0 | ||
145 | #define SYS_PLL_MEM_CMD 0x2a1 | ||
146 | #define SYS_CPU_PLL_MEM_REQ 0x2a2 | ||
147 | #define SYS_SYS_PLL_MEM_REQ 0x2a3 | ||
148 | #define SYS_PLL_MEM_STAT 0x2a4 | ||
149 | |||
120 | #ifndef __ASSEMBLY__ | 150 | #ifndef __ASSEMBLY__ |
121 | 151 | ||
122 | #define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) | 152 | #define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) |
@@ -124,5 +154,6 @@ | |||
124 | #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) | 154 | #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) |
125 | #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) | 155 | #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) |
126 | 156 | ||
157 | unsigned int nlm_get_pic_frequency(int node); | ||
127 | #endif | 158 | #endif |
128 | #endif | 159 | #endif |
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h index 63c99176dffe..3c80a75233bd 100644 --- a/arch/mips/include/asm/netlogic/xlr/pic.h +++ b/arch/mips/include/asm/netlogic/xlr/pic.h | |||
@@ -36,6 +36,8 @@ | |||
36 | #define _ASM_NLM_XLR_PIC_H | 36 | #define _ASM_NLM_XLR_PIC_H |
37 | 37 | ||
38 | #define PIC_CLK_HZ 66666666 | 38 | #define PIC_CLK_HZ 66666666 |
39 | #define pic_timer_freq() PIC_CLK_HZ | ||
40 | |||
39 | /* PIC hardware interrupt numbers */ | 41 | /* PIC hardware interrupt numbers */ |
40 | #define PIC_IRT_WD_INDEX 0 | 42 | #define PIC_IRT_WD_INDEX 0 |
41 | #define PIC_IRT_TIMER_0_INDEX 1 | 43 | #define PIC_IRT_TIMER_0_INDEX 1 |