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authorRalf Baechle <ralf@linux-mips.org>2014-05-23 10:29:44 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-05-23 18:07:01 -0400
commitb633648c5ad3cfbda0b3daea50d2135d44899259 (patch)
tree6100185cae10f36a55e71c3b220fc79cfa14b7c0 /arch/mips/include/asm/mipsregs.h
parent8b2e62cc34feaaf1cac9440a93fb18ac0b1e81bc (diff)
MIPS: MT: Remove SMTC support
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
-rw-r--r--arch/mips/include/asm/mipsregs.h133
1 files changed, 1 insertions, 132 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 88e30d5022b3..fb2d17487ec2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1014,19 +1014,8 @@ do { \
1014#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1014#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1015 1015
1016#define read_c0_status() __read_32bit_c0_register($12, 0) 1016#define read_c0_status() __read_32bit_c0_register($12, 0)
1017#ifdef CONFIG_MIPS_MT_SMTC 1017
1018#define write_c0_status(val) \
1019do { \
1020 __write_32bit_c0_register($12, 0, val); \
1021 __ehb(); \
1022} while (0)
1023#else
1024/*
1025 * Legacy non-SMTC code, which may be hazardous
1026 * but which might not support EHB
1027 */
1028#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1018#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1029#endif /* CONFIG_MIPS_MT_SMTC */
1030 1019
1031#define read_c0_cause() __read_32bit_c0_register($13, 0) 1020#define read_c0_cause() __read_32bit_c0_register($13, 0)
1032#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1021#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
@@ -1750,11 +1739,6 @@ static inline void tlb_write_random(void)
1750/* 1739/*
1751 * Manipulate bits in a c0 register. 1740 * Manipulate bits in a c0 register.
1752 */ 1741 */
1753#ifndef CONFIG_MIPS_MT_SMTC
1754/*
1755 * SMTC Linux requires shutting-down microthread scheduling
1756 * during CP0 register read-modify-write sequences.
1757 */
1758#define __BUILD_SET_C0(name) \ 1742#define __BUILD_SET_C0(name) \
1759static inline unsigned int \ 1743static inline unsigned int \
1760set_c0_##name(unsigned int set) \ 1744set_c0_##name(unsigned int set) \
@@ -1793,121 +1777,6 @@ change_c0_##name(unsigned int change, unsigned int val) \
1793 return res; \ 1777 return res; \
1794} 1778}
1795 1779
1796#else /* SMTC versions that manage MT scheduling */
1797
1798#include <linux/irqflags.h>
1799
1800/*
1801 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1802 * header file recursion.
1803 */
1804static inline unsigned int __dmt(void)
1805{
1806 int res;
1807
1808 __asm__ __volatile__(
1809 " .set push \n"
1810 " .set mips32r2 \n"
1811 " .set noat \n"
1812 " .word 0x41610BC1 # dmt $1 \n"
1813 " ehb \n"
1814 " move %0, $1 \n"
1815 " .set pop \n"
1816 : "=r" (res));
1817
1818 instruction_hazard();
1819
1820 return res;
1821}
1822
1823#define __VPECONTROL_TE_SHIFT 15
1824#define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1825
1826#define __EMT_ENABLE __VPECONTROL_TE
1827
1828static inline void __emt(unsigned int previous)
1829{
1830 if ((previous & __EMT_ENABLE))
1831 __asm__ __volatile__(
1832 " .set mips32r2 \n"
1833 " .word 0x41600be1 # emt \n"
1834 " ehb \n"
1835 " .set mips0 \n");
1836}
1837
1838static inline void __ehb(void)
1839{
1840 __asm__ __volatile__(
1841 " .set mips32r2 \n"
1842 " ehb \n" " .set mips0 \n");
1843}
1844
1845/*
1846 * Note that local_irq_save/restore affect TC-specific IXMT state,
1847 * not Status.IE as in non-SMTC kernel.
1848 */
1849
1850#define __BUILD_SET_C0(name) \
1851static inline unsigned int \
1852set_c0_##name(unsigned int set) \
1853{ \
1854 unsigned int res; \
1855 unsigned int new; \
1856 unsigned int omt; \
1857 unsigned long flags; \
1858 \
1859 local_irq_save(flags); \
1860 omt = __dmt(); \
1861 res = read_c0_##name(); \
1862 new = res | set; \
1863 write_c0_##name(new); \
1864 __emt(omt); \
1865 local_irq_restore(flags); \
1866 \
1867 return res; \
1868} \
1869 \
1870static inline unsigned int \
1871clear_c0_##name(unsigned int clear) \
1872{ \
1873 unsigned int res; \
1874 unsigned int new; \
1875 unsigned int omt; \
1876 unsigned long flags; \
1877 \
1878 local_irq_save(flags); \
1879 omt = __dmt(); \
1880 res = read_c0_##name(); \
1881 new = res & ~clear; \
1882 write_c0_##name(new); \
1883 __emt(omt); \
1884 local_irq_restore(flags); \
1885 \
1886 return res; \
1887} \
1888 \
1889static inline unsigned int \
1890change_c0_##name(unsigned int change, unsigned int newbits) \
1891{ \
1892 unsigned int res; \
1893 unsigned int new; \
1894 unsigned int omt; \
1895 unsigned long flags; \
1896 \
1897 local_irq_save(flags); \
1898 \
1899 omt = __dmt(); \
1900 res = read_c0_##name(); \
1901 new = res & ~change; \
1902 new |= (newbits & change); \
1903 write_c0_##name(new); \
1904 __emt(omt); \
1905 local_irq_restore(flags); \
1906 \
1907 return res; \
1908}
1909#endif
1910
1911__BUILD_SET_C0(status) 1780__BUILD_SET_C0(status)
1912__BUILD_SET_C0(cause) 1781__BUILD_SET_C0(cause)
1913__BUILD_SET_C0(config) 1782__BUILD_SET_C0(config)
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